descriptionIcarus Verilog
homepage URLhttp://www.icarus.com/eda/verilog
repository URLdisabled git://icarus.com/~steve-icarus/verilog
ownersteve@icarus.com
last changeSun, 2 Dec 2007 17:09:53 +0000 (2 09:09 -0800)
last refreshTue, 4 Dec 2007 04:57:02 +0000 (4 05:57 +0100)
content tags
add:
readme
This is a mirror of the Icarus Verilog git repository. This is just to provide an off-site backup of the main Icarus Verilog repository, and also so that someone else gets to maintain a git-web interface:-)
shortlog
2007-12-02 Martic WhitakerFix for assertion error when expanding macro.master
2007-12-02 Martin WhitakerAdd support for text macros with arguments.
2007-12-02 Larry DoolittleFix compile time warnings
2007-12-01 Stephen WilliamsSupport second argument of sdf_annotate
2007-12-01 Stephen WilliamsMerge branch 'master' of ssh://steve-icarus@icarus...
2007-12-01 Stephen WilliamsClean up warnings for round() function declaration.
2007-11-30 Stephen WilliamsInclude stdlib.h to remove compile warnings.
2007-11-30 Cary RAdd vpiIterator and vpiMemory to string version of...
2007-11-30 Cary RLD should be based on $CC and not hardcoded to gcc
2007-11-30 Cary RAdd -D to iverilog-vpi and update documentation.
2007-11-29 Stephen WilliamsHandle empty INSTANCE name
2007-11-29 Stephen WilliamsIdentifers include _ and $ characters.
2007-11-28 Stephen WilliamsHandle hierarchical instances
2007-11-28 Stephen WilliamsFix parsing of hierarchical identifiers
2007-11-28 Stephen WilliamsParse TIMINGCHECK syntax
2007-11-27 Cary RAdd the ability to dump array words
...
tags
16 years ago v0_8_6 Release 0.8.6
16 years ago s20070812 Snapshot 20070812
16 years ago v0_8_5
unknown v8-s20060822
unknown v0_8_4
unknown v0_8_3
unknown v0_8_2
unknown v0_8_1
unknown v0_8
unknown v0_7
unknown v0_6_1
unknown v0_6
unknown v0_4rc1
unknown v0_4
unknown v0_3rc2
unknown v0_3rc1
...
heads
16 years ago v0_8-branch
16 years ago master
16 years ago v0_8-devel
16 years ago cvshead
22 years ago v0_6-branch
24 years ago version0_1