Fix for assertion error when expanding macro.
[iverilog.git] / pform.h
blob38757cf9faecb410e9186e7d5f92315582b3ef60
1 #ifndef __pform_H
2 #define __pform_H
3 /*
4 * Copyright (c) 1998-2000 Stephen Williams (steve@icarus.com)
6 * This source code is free software; you can redistribute it
7 * and/or modify it in source code form under the terms of the GNU
8 * General Public License as published by the Free Software
9 * Foundation; either version 2 of the License, or (at your option)
10 * any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
21 #ifdef HAVE_CVS_IDENT
22 #ident "$Id: pform.h,v 1.91 2007/05/24 04:07:12 steve Exp $"
23 #endif
25 # include "netlist.h"
26 # include "HName.h"
27 # include "named.h"
28 # include "Module.h"
29 # include "Statement.h"
30 # include "PGate.h"
31 # include "PExpr.h"
32 # include "PTask.h"
33 # include "PUdp.h"
34 # include "PWire.h"
35 # include "verinum.h"
36 # include <iostream>
37 # include <string>
38 # include <list>
39 # include <stdio.h>
42 * These classes implement the parsed form (P-form for short) of the
43 * original verilog source. the parser generates the pform for the
44 * convenience of later processing steps.
49 * Wire objects represent the named wires (of various flavor) declared
50 * in the source.
52 * Gate objects are the functional modules that are connected together
53 * by wires.
55 * Wires and gates, connected by joints, represent a netlist. The
56 * netlist is therefore a representation of the desired circuit.
58 class PGate;
59 class PExpr;
60 class PSpecPath;
61 struct vlltype;
64 * The min:typ:max expression s selected at parse time using the
65 * enumeration. When the compiler makes a choice, it also prints a
66 * warning if min_typ_max_warn > 0.
68 extern enum MIN_TYP_MAX { MIN, TYP, MAX } min_typ_max_flag;
69 extern unsigned min_typ_max_warn;
70 PExpr* pform_select_mtm_expr(PExpr*min, PExpr*typ, PExpr*max);
73 * This flag is true if the lexor thinks we are in a library source
74 * file.
76 extern bool pform_library_flag;
79 * These type are lexical types -- that is, types that are used as
80 * lexical values to decorate the parse tree during parsing. They are
81 * not in any way preserved once parsing is done.
84 /* This is information about port name information for named port
85 connections. */
87 //typedef struct named<PExpr*> named_pexpr_t;
88 typedef named<PExpr*> named_pexpr_t;
90 struct parmvalue_t {
91 svector<PExpr*>*by_order;
92 svector<named_pexpr_t*>*by_name;
95 struct str_pair_t { PGate::strength_t str0, str1; };
97 struct net_decl_assign_t {
98 char*name;
99 PExpr*expr;
100 struct net_decl_assign_t*next;
103 /* The lgate is gate instantiation information. */
104 struct lgate {
105 lgate(int =0)
106 : parms(0), parms_by_name(0), lineno(0)
107 { range[0] = 0;
108 range[1] = 0;
111 string name;
112 svector<PExpr*>*parms;
113 svector<named_pexpr_t*>*parms_by_name;
115 PExpr*range[2];
117 const char* file;
118 unsigned lineno;
121 /* The lexor calls this function to change the default nettype. */
122 extern void pform_set_default_nettype(NetNet::Type net,
123 const char*file,
124 unsigned lineno);
127 * The parser uses startmodule and endmodule together to build up a
128 * module as it parses it. The startmodule tells the pform code that a
129 * module has been noticed in the source file and the following events
130 * are to apply to the scope of that module. The endmodule causes the
131 * pform to close up and finish the named module.
133 extern void pform_startmodule(const char*, const char*file, unsigned lineno,
134 svector<named_pexpr_t*>*attr);
135 extern void pform_module_set_ports(svector<Module::port_t*>*);
137 /* This function is used to support the port definition in a
138 port_definition_list. In this case, we have everything needed to
139 define the port, all in one place. */
140 extern void pform_module_define_port(const struct vlltype&li,
141 const char*name,
142 NetNet::PortType,
143 NetNet::Type type,
144 bool signed_flag,
145 svector<PExpr*>*range,
146 svector<named_pexpr_t*>*attr);
148 extern Module::port_t* pform_module_port_reference(char*name,
149 const char*file,
150 unsigned lineno);
151 extern void pform_endmodule(const char*);
153 extern void pform_make_udp(perm_string name, list<string>*parms,
154 svector<PWire*>*decl, list<string>*table,
155 Statement*init,
156 const char*file, unsigned lineno);
158 extern void pform_make_udp(perm_string name,
159 bool sync_flag, perm_string out_name,
160 PExpr*sync_init,
161 list<perm_string>*parms,
162 list<string>*table,
163 const char*file, unsigned lineno);
166 * Enter/exit name scopes. The push_scope function pushes the scope
167 * name string onto the scope hierarchy. The pop pulls it off and
168 * deletes it. Thus, the string pushed must be allocated.
170 extern void pform_push_scope(char*name);
171 extern void pform_pop_scope();
174 extern verinum* pform_verinum_with_size(verinum*s, verinum*val,
175 const char*file, unsigned loneno);
178 * This function takes the list of names as new genvars to declare in
179 * the current module scope.
181 extern void pform_genvars(list<perm_string>*names);
183 extern void pform_start_generate_for(const struct vlltype&li,
184 char*ident1,
185 PExpr*init,
186 PExpr*test,
187 char*ident2,
188 PExpr*next);
189 extern void pform_start_generate_if(const struct vlltype&li, PExpr*test);
190 extern void pform_start_generate_else(const struct vlltype&li);
191 extern void pform_generate_block_name(char*name);
192 extern void pform_endgenerate();
196 * The makewire functions announce to the pform code new wires. These
197 * go into a module that is currently opened.
199 extern void pform_makewire(const struct vlltype&li, const char*name,
200 NetNet::Type type,
201 NetNet::PortType pt,
202 ivl_variable_type_t,
203 svector<named_pexpr_t*>*attr);
205 /* This form handles simple declarations */
206 extern void pform_makewire(const struct vlltype&li,
207 svector<PExpr*>*range,
208 bool signed_flag,
209 list<perm_string>*names,
210 NetNet::Type type,
211 NetNet::PortType,
212 ivl_variable_type_t,
213 svector<named_pexpr_t*>*attr,
214 PWSRType rt = SR_NET);
216 /* This form handles assignment declarations. */
217 extern void pform_makewire(const struct vlltype&li,
218 svector<PExpr*>*range,
219 bool signed_flag,
220 svector<PExpr*>*delay,
221 str_pair_t str,
222 net_decl_assign_t*assign_list,
223 NetNet::Type type,
224 ivl_variable_type_t);
226 extern void pform_make_reginit(const struct vlltype&li,
227 const char*name, PExpr*expr);
229 /* Look up the names of the wires, and set the port type,
230 i.e. input, output or inout. If the wire does not exist, create
231 it. The second form takes a single name. */
232 extern void pform_set_port_type(const struct vlltype&li,
233 list<perm_string>*names,
234 svector<PExpr*>*range,
235 bool signed_flag,
236 NetNet::PortType);
237 extern void pform_set_port_type(perm_string nm, NetNet::PortType pt,
238 const char*file, unsigned lineno);
240 extern void pform_set_net_range(const char* name);
241 extern void pform_set_net_range(list<perm_string>*names,
242 svector<PExpr*>*,
243 bool signed_flag,
244 ivl_variable_type_t,
245 PWSRType rt = SR_NET);
246 extern void pform_set_reg_idx(const char*name, PExpr*l, PExpr*r);
247 extern void pform_set_reg_integer(list<perm_string>*names);
248 extern void pform_set_reg_time(list<perm_string>*names);
249 extern void pform_set_task(perm_string name, PTask*);
250 extern void pform_set_function(perm_string name, PFunction*);
252 /* pform_set_attrib and pform_set_type_attrib exist to support the
253 $attribute syntax, which can only set string values to
254 attributes. The functions keep the value strings that are
255 passed in. */
256 extern void pform_set_attrib(perm_string name, perm_string key,
257 char*value);
258 extern void pform_set_type_attrib(perm_string name, const string&key,
259 char*value);
261 extern void pform_set_parameter(perm_string name,
262 bool signed_flag,
263 svector<PExpr*>*range,
264 PExpr*expr);
265 extern void pform_set_localparam(perm_string name,
266 bool signed_flag,
267 svector<PExpr*>*range,
268 PExpr*expr);
269 extern void pform_set_defparam(const pform_name_t&name, PExpr*expr);
272 * Functions related to specify blocks.
274 extern void pform_set_specparam(perm_string name, PExpr*expr);
276 extern PSpecPath*pform_make_specify_path(const struct vlltype&li,
277 list<perm_string>*src, char pol,
278 bool full_flag, list<perm_string>*dst);
279 extern PSpecPath*pform_make_specify_edge_path(const struct vlltype&li,
280 int edge_flag, /*posedge==true */
281 list<perm_string>*src, char pol,
282 bool full_flag, list<perm_string>*dst,
283 PExpr*data_source_expression);
284 extern PSpecPath*pform_assign_path_delay(PSpecPath*obj, svector<PExpr*>*delays);
286 extern void pform_module_specify_path(PSpecPath*obj);
289 * pform_make_behavior creates processes that are declared with always
290 * or initial items.
292 extern PProcess* pform_make_behavior(PProcess::Type, Statement*,
293 svector<named_pexpr_t*>*attr);
295 extern svector<PWire*>* pform_make_udp_input_ports(list<perm_string>*);
297 extern bool pform_expression_is_constant(const PExpr*);
299 extern void pform_make_events(list<perm_string>*names,
300 const char*file, unsigned lineno);
302 * Make real datum objects.
304 extern void pform_make_reals(list<perm_string>*names,
305 const char*file, unsigned lineno);
308 * The makegate function creates a new gate (which need not have a
309 * name) and connects it to the specified wires.
311 extern void pform_makegates(PGBuiltin::Type type,
312 struct str_pair_t str,
313 svector<PExpr*>*delay,
314 svector<lgate>*gates,
315 svector<named_pexpr_t*>*attr);
317 extern void pform_make_modgates(perm_string type,
318 struct parmvalue_t*overrides,
319 svector<lgate>*gates);
321 /* Make a continuous assignment node, with optional bit- or part- select. */
322 extern void pform_make_pgassign_list(svector<PExpr*>*alist,
323 svector<PExpr*>*del,
324 struct str_pair_t str,
325 const char* fn, unsigned lineno);
327 /* Given a port type and a list of names, make a list of wires that
328 can be used as task port information. */
329 extern svector<PWire*>*pform_make_task_ports(NetNet::PortType pt,
330 ivl_variable_type_t vtype,
331 bool signed_flag,
332 svector<PExpr*>*range,
333 list<perm_string>*names,
334 const char* file,
335 unsigned lineno);
339 * These are functions that the outside-the-parser code uses the do
340 * interesting things to the verilog. The parse function reads and
341 * parses the source file and places all the modules it finds into the
342 * mod list. The dump function dumps a module to the output stream.
344 extern void pform_dump(ostream&out, Module*mod);
347 * Used to report the original module location when a nested module
348 * (missing endmodule) is found by the parser.
350 extern void pform_error_nested_modules();
352 #endif