toolchain/gcc/libgloss/hp74x/diagnose.h

   1 /****************************************************************************
   2
   3                 THIS SOFTWARE IS NOT COPYRIGHTED
   4
   5    HP offers the following for use in the public domain.  HP makes no
   6    warranty with regard to the software or it's performance and the
   7    user accepts the software "AS IS" with all faults.
   8
   9    HP DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD
  10    TO THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  11    OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  12
  13 ****************************************************************************/
  14
  15                 /* Diagnose register definitions */
  16
  17
  18 #ifdef PCXL
  19
  20 #define CPU_DIAG_0_L2IHPMC_BIT           6   /* Level 2 I-cache error flag */
  21 #define CPU_DIAG_0_L2DHPMC_BIT           8   /* Level 2 D-cache error flag */
  22 #define CPU_DIAG_0_L1IHPMC_BIT          10   /* Level 1 I-cache error flag */
  23 #define CPU_DIAG_0_L2PARERR_BIT         15   /* rightmost bit */
  24 #define CPU_DIAG_0_PREV_HPMC_PREP_BIT   16   /* Previous HPMC finished */
  25 #define CPU_DIAG_0_PWR_FAIL_BIT         17
  26 #define CPU_DIAG_0_EXPECT_HPMC_BIT      18   /* Expecting HPMC */
  27
  28         /* Mask for Read/clear bits in CPU diagnose register 0 */
  29 #define CPU0_MASK       0x02AF0000
  30
  31 #else  /* PCXT */
  32
  33 #define CPU_DIAG_0_PREV_HPMC_PREP_BIT    3   /* Previous HPMC finished */
  34 #define CPU_DIAG_0_BOOTING_BIT           4
  35 #define CPU_DIAG_0_EXPECT_HPMC_BIT       5   /* Expecting HPMC */
  36
  37 #define CPU_DIAG_0_DHPMC_BIT            10
  38 #define CPU_DIAG_0_ILPMC_BIT            14
  39 #define CPU_DIAG_0_HTOC_BIT             23
  40
  41         /* Mask for Read/clear bits in CPU diagnose register 0 */
  42 #define CPU0_MASK       0x00220100
  43
  44 #endif
  45
  46                 /* Diagnose instruction macros */
  47
  48 #ifdef PCXL
  49
  50 /*** Different PCXL diagnose commands ***/
  51
  52 /* Original mfcpu replaced with the two commands mfcpu_t & mfcpu_c */
  53 mfcpu_t .macro  diag_reg,gen_reg
  54         { 0 ..  5}      = 0x5 {26 .. 31}
  55         { 6 .. 10}      = diag_reg {27 .. 31}
  56         {11 .. 15}      = 0x0 {27 .. 31}
  57         {16 .. 18}      = 0x0 {29 .. 31}
  58         {19 .. 26}      = 0xa0 {24 .. 31}
  59         {27 .. 31}      = gen_reg {27 .. 31}
  60         .endm
  61
  62 mfcpu_c .macro  diag_reg,gen_reg
  63         { 0 ..  5}      = 0x5 {26 .. 31}
  64         { 6 .. 10}      = diag_reg {27 .. 31}
  65         {11 .. 15}      = gen_reg {27 .. 31}
  66         {16 .. 18}      = 0x0 {29 .. 31}
  67         {19 .. 26}      = 0x30 {24 .. 31}
  68         {27 .. 31}      = 0x0 {27 .. 31}
  69         .endm
  70
  71 mtcpu   .macro  gen_reg,diag_reg
  72         { 0 ..  5}      = 0x5 {26 .. 31}
  73         { 6 .. 10}      = diag_reg {27 .. 31}
  74         {11 .. 15}      = gen_reg {27 .. 31}
  75         {16 .. 18}      = 0x0 {29 .. 31}
  76         {19 .. 26}      = 0x12 {24 .. 31}
  77         {27 .. 31}      = 0x0 {27 .. 31}
  78         .endm
  79
  80 shdw_gr .macro
  81         { 0 ..  5}      = 0x5 {26 .. 31}
  82         { 6 .. 10}      = 0x0 {27 .. 31}
  83         {11 .. 15}      = 0x0 {27 .. 31}
  84         {16 .. 18}      = 0x0 {29 .. 31}
  85         {19 .. 26}      = 0xd0 {24 .. 31}
  86         {27 .. 31}      = 0x0 {27 .. 31}
  87         .endm
  88
  89 gr_shdw .macro
  90         { 0 ..  5}      = 0x5 {26 .. 31}
  91         { 6 .. 10}      = 0x0 {27 .. 31}
  92         {11 .. 15}      = 0x0 {27 .. 31}
  93         {16 .. 18}      = 0x0 {29 .. 31}
  94         {19 .. 26}      = 0xd2 {24 .. 31}
  95         {27 .. 31}      = 0x0 {27 .. 31}
  96         .endm
  97
  98 #else
  99
 100 /*** original PCXT version ***/
 101
 102 /* Originally  was mfcpu without the _c */
 103 mfcpu_c .macro  diag_reg,gen_reg
 104         { 0 ..  5}      = 0x5 {26 .. 31}
 105         { 6 .. 10}      = diag_reg {27 .. 31}
 106         {11 .. 15}      = gen_reg {27 .. 31}
 107         {16 .. 18}      = 0x0 {29 .. 31}
 108         {19 .. 26}      = 0xd0 {24 .. 31}
 109         {27 .. 31}      = 0x0 {27 .. 31}
 110         .endm
 111
 112 mtcpu   .macro  gen_reg,diag_reg
 113         { 0 ..  5}      = 0x5 {26 .. 31}
 114         { 6 .. 10}      = diag_reg {27 .. 31}
 115         {11 .. 15}      = gen_reg {27 .. 31}
 116         {16 .. 18}      = 0x0 {29 .. 31}
 117         {19 .. 26}      = 0xb0 {24 .. 31}
 118         {27 .. 31}      = 0x0 {27 .. 31}
 119         .endm
 120
 121 shdw_gr .macro
 122         { 0 ..  5}      = 0x5 {26 .. 31}
 123         { 6 .. 10}      = 0x2 {27 .. 31}
 124         {11 .. 15}      = 0x0 {27 .. 31}
 125         {16 .. 18}      = 0x1 {29 .. 31}
 126         {19 .. 26}      = 0x30 {24 .. 31}
 127         {27 .. 31}      = 0x0 {27 .. 31}
 128         .endm
 129
 130 gr_shdw .macro
 131         { 0 ..  5}      = 0x5 {26 .. 31}
 132         { 6 .. 10}      = 0x2 {27 .. 31}
 133         {11 .. 15}      = 0x0 {27 .. 31}
 134         {16 .. 18}      = 0x0 {29 .. 31}
 135         {19 .. 26}      = 0x31 {24 .. 31}
 136         {27 .. 31}      = 0x0 {27 .. 31}
 137         .endm
 138
 139 #endif
 140
 141
 142         /* Actual commands used doubled instructions for cpu timing */
 143
 144
 145 #define SHDW_GR         shdw_gr ! \
 146                         shdw_gr
 147
 148
 149         /* Break instruction definitions */
 150
 151 #define i13BREAK        0xa5a   /* im13 field for specified functions */
 152 #define i5REG           0x06    /* Init registers */
 153 #define i5BP            0x09    /* GDB breakpoint */
 154 #define i5PSW           0x0b    /* Get PSW */
 155 #define i5INLINE        0x0e    /* Get INLINE */
 156
 157 BR_INIT_REGS    .macro
 158         break   i5REG,i13BREAK
 159         .endm
 160
 161 BR_GET_PSW      .macro
 162         break   i5PSW,i13BREAK
 163         .endm
 164
 165 BR_INLINE       .macro
 166         break   i5INLINE,i13BREAK
 167         .endm
 168