toolchain/gcc/gcc/config/zpu/zpu.h

   1 /* Definitions of target machine for GNU compiler for INMOS transputer family.
   2    Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
   3
   4    Written by Øyvind Harboe <oyvind.harboe@zylin.com>
   5
   6 This file is part of GNU CC.
   7
   8 GNU CC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 2, or (at your option)
  11 any later version.
  12
  13 GNU CC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GNU CC; see the file COPYING.  If not, write to
  20 the Free Software Foundation, 59 Temple Place - Suite 330,
  21 Boston, MA 02111-1307, USA.  */
  22
  23
  24 #undef LIB_SPEC
  25 #define LIB_SPEC "--start-group -lc -lbcc --end-group"
  26
  27
  28 #undef  STARTFILE_SPEC
  29 #define STARTFILE_SPEC "crt0.o%s crt_io.o%s crti%O%s crtbegin%O%s"
  30
  31 #undef  ENDFILE_SPEC
  32 #define ENDFILE_SPEC "crtend%O%s crtn%O%s"
  33
  34
  35 /* just a shorthand for those hard-to-remember options */
  36 #define TARGET_OPTION_TRANSLATE_TABLE \
  37   { "-phi", "-mboard=phi" },  \
  38   { "-abel", "-mboard=abel" },  \
  39   { "-zeta", "-mboard=zeta" }
  40
  41 #define CC1_SPEC ""
  42
  43 #define ASM_SPEC "%{Os:--defsym OPTIMIZE_SIZE=1}"
  44
  45 #define LINK_SPEC "%{mboard=phi:--defsym ZPU_ID=2} %{mboard=zeta:--defsym ZPU_ID=1} %{mboard=abel:--defsym ZPU_ID=0}"
  46
  47
  48
  49 /* The ZPU architecture is stack/0-operand architecture, so omitting the
  50  * frame pointer is fundamental to any sort of decent code quality.
  51  *
  52  * -fomit-frame-pointer will be enabled at all optimisation levels/options
  53  * with CAN_DEBUG_WITHOUT_FP defined.
  54  */
  55 #define CAN_DEBUG_WITHOUT_FP 1
  56
  57
  58
  59
  60 extern int target_flags;
  61
  62
  63 extern int target_flags;
  64
  65
  66
  67 #define ZPU_MULT (1<<0)
  68 #define ZPU_DIV (1<<1)
  69 #define ZPU_MOD (1<<2)
  70 #define ZPU_NEG (1<<3)
  71 #define ZPU_LOADSP (1<<4)
  72 #define ZPU_STORESP (1<<5)
  73 #define ZPU_PUSHSPADD (1<<6)
  74 #define ZPU_CALLPCREL (1<<7)
  75 #define ZPU_CALL (1<<8)
  76 #define ZPU_ADDSP (1<<9)
  77 #define ZPU_SUB (1<<10)
  78 #define ZPU_XOR (1<<11)
  79 #define ZPU_FLIP (1<<12)
  80 #define ZPU_ASHIFTRT (1<<13)
  81 #define ZPU_ASHIFTL (1<<14)
  82 #define ZPU_SHIFTL (1<<15)
  83 #define ZPU_NEQBRANCH (1<<16)
  84 #define ZPU_LSHIFTRT (1<<17)
  85
  86 #define ZPU_BYTEOP (1<<18)
  87 #define ZPU_SHORTOP (1<<19)
  88 #define ZPU_EQ (1<<20)
  89 #define ZPU_COMPARE (1<<21)
  90 #define ZPU_POPPCREL (1<<22)
  91 #define ZPU_BYTESBIG (1<<23)
  92 #define ZPU_BITSBIG (1<<24)
  93 #define ZPU_MEMREG (1<<25)
  94
  95
  96
  97
  98
  99 #define TARGET_SWITCHES_DEFAULT (0x7fffffff&~ZPU_BITSBIG)
 100
 101
 102
 103
 104 #define TARGET_MULT ((target_flags & ZPU_MULT)!=0)
 105 #define TARGET_DIV ((target_flags & ZPU_DIV)!=0)
 106 #define TARGET_MOD ((target_flags & ZPU_MOD)!=0)
 107 #define TARGET_NEG ((target_flags & ZPU_NEG)!=0)
 108 #define TARGET_LOADSP ((target_flags & ZPU_LOADSP)!=0)
 109 #define TARGET_STORESP ((target_flags & ZPU_STORESP)!=0)
 110 #define TARGET_ADDSP ((target_flags & ZPU_ADDSP)!=0)
 111 #define TARGET_PUSHSPADD ((target_flags & ZPU_PUSHSPADD)!=0)
 112 #define TARGET_NEQBRANCH ((target_flags & ZPU_NEQBRANCH)!=0)
 113 #define TARGET_ASHIFTRT ((target_flags & ZPU_ASHIFTRT)!=0)
 114 #define TARGET_ASHIFTL ((target_flags & ZPU_ASHIFTL)!=0)
 115 #define TARGET_LSHIFTRT ((target_flags & ZPU_LSHIFTRT)!=0)
 116 #define TARGET_CALL ((target_flags & ZPU_CALL)!=0)
 117 #define TARGET_CALLPCREL ((target_flags & ZPU_CALLPCREL)!=0)
 118 #define TARGET_BYTEOP ((target_flags & ZPU_BYTEOP)!=0)
 119 #define TARGET_SHORTOP ((target_flags & ZPU_SHORTOP)!=0)
 120 #define TARGET_EQ ((target_flags & ZPU_EQ)!=0)
 121 #define TARGET_COMPARE ((target_flags & ZPU_COMPARE)!=0)
 122 #define TARGET_POPPCREL ((target_flags & ZPU_POPPCREL)!=0)
 123 #define TARGET_BYTESBIG ((target_flags & ZPU_BYTESBIG)!=0)
 124 #define TARGET_BITSBIG ((target_flags & ZPU_BITSBIG)!=0)
 125 #define TARGET_MEMREG ((target_flags & ZPU_MEMREG)!=0)
 126
 127
 128 #define TARGET_SWITCHES \
 129 { \
 130     { "mult", ZPU_MULT, "MULT instruction" },\
 131     { "no-mult", -ZPU_MULT, "MULT instruction" },\
 132     { "div", ZPU_DIV, "DIV instruction" },\
 133     { "no-div", -ZPU_DIV, "DIV instruction" },\
 134     { "mod", ZPU_MOD, "MOD instruction" },\
 135     { "no-mod", -ZPU_MOD, "MOD instruction" },\
 136     { "neg", ZPU_NEG, "NEG instruction" },\
 137     { "no-neg", -ZPU_NEG, "NEG instruction" },\
 138     { "loadsp", ZPU_LOADSP, "LOADSP instruction" },\
 139     { "no-loadsp", -ZPU_LOADSP, "LOADSP instruction" },\
 140     { "storesp", ZPU_STORESP, "STORESP instruction" },\
 141     { "no-storesp", -ZPU_STORESP, "STORESP instruction" },\
 142     { "pushspadd", ZPU_PUSHSPADD, "PUSHSPADD instruction" },\
 143     { "no-pushspadd", -ZPU_PUSHSPADD, "PUSHSPADD instruction" },\
 144     { "neqbranch", ZPU_NEQBRANCH, "NEQBRANCH instruction" },\
 145     { "no-neqbranch", -ZPU_NEQBRANCH, "NEQBRANCH instruction" },\
 146     { "addsp", ZPU_ADDSP, "ADDSP instruction" },\
 147     { "no-addsp", -ZPU_ADDSP, "ADDSP instruction" },\
 148     { "ashiftrt", ZPU_ASHIFTRT, "ASHIFTRIGHT instruction" },\
 149     { "no-ashiftrt", -ZPU_ASHIFTRT, "ASHIFTRIGHT instruction" },\
 150     { "ashiftl", ZPU_ASHIFTL, "ASHIFTLEFT instruction" },\
 151     { "no-ashiftl", -ZPU_ASHIFTL, "ASHIFTLEFT instruction" },\
 152     { "lshiftrt", ZPU_LSHIFTRT, "LSHIFTRIGHT instruction" },\
 153     { "no-lshiftrt", -ZPU_LSHIFTRT, "LSHIFTRIGHT instruction" },\
 154     { "call", ZPU_CALL, "CALL instruction" },\
 155     { "no-call", -ZPU_CALL, "CALL instruction" },\
 156     { "callpcrel", ZPU_CALLPCREL, "CALLPCREL instruction" },\
 157     { "no-callpcrel", -ZPU_CALLPCREL, "CALLPCREL instruction" },\
 158     { "shortop", ZPU_SHORTOP, "LOADH/STOREH instructions" },\
 159     { "no-shortop", -ZPU_SHORTOP, "LOADH/STOREH instructions" },\
 160     { "byteop", ZPU_BYTEOP, "LOADB/STOREB insructions" },\
 161     { "no-byteop", -ZPU_BYTEOP, "LOADB/STOREB insructions" },\
 162     { "eq", ZPU_EQ, "EQ insructions" },\
 163     { "no-eq", -ZPU_EQ, "EQ insructions" },\
 164     { "compare", ZPU_COMPARE, "COMPARE insructions" },\
 165     { "no-compare", -ZPU_COMPARE, "COMPARE insructions" },\
 166     { "poppcrel", ZPU_POPPCREL, "POPPCREL insructions" },\
 167     { "no-poppcrel", -ZPU_POPPCREL, "POPPCREL insructions" },\
 168     { "memreg", ZPU_MEMREG, "Store r0-r3 in memory location 0-15" },\
 169     { "no-memreg", -ZPU_MEMREG, "CALL _regpush and _regpop for r0-r3" },\
 170     { "", TARGET_SWITCHES_DEFAULT, "" }\
 171 }
 172
 173 extern const char *zpu_board_name;
 174
 175 #define TARGET_OPTIONS {                                                      \
 176  { "board=", &zpu_board_name, N_("Specify the ZPU board name"), 0} }
 177
 178
 179 #define MULTILIB_DEFAULTS { "O0" }
 180
 181
 182 #define TARGET_VERSION fprintf (stderr, " (ZPU syntax)");
 183
 184
 185 #define BITS_BIG_ENDIAN                 0 /* TARGET_BITSBIG */
 186 #define BYTES_BIG_ENDIAN                1 /* TARGET_BYTESBIG */
 187 #define WORDS_BIG_ENDIAN                1 /* TARGET_BYTESBIG */
 188 #define BITS_PER_UNIT                   8
 189 #define BITS_PER_WORD                   32
 190 #define UNITS_PER_WORD                  4
 191
 192 /* Define this macro if it is advisable to hold scalars in registers
 193    in a wider mode than that declared by the program.  In such cases,
 194    the value is constrained to be within the bounds of the declared
 195    type, but kept valid in the wider mode.  The signedness of the
 196    extension may differ from that of the type.  */
 197 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
 198 if (GET_MODE_CLASS (MODE) == MODE_INT           \
 199     && GET_MODE_SIZE (MODE) < UNITS_PER_WORD)   \
 200 {                                               \
 201   (MODE) = word_mode;                           \
 202 }
 203 #define PROMOTE_FUNCTION_ARGS
 204 #define PROMOTE_FUNCTION_RETURN
 205
 206
 207 #define POINTER_SIZE                    BITS_PER_WORD
 208
 209 #define PARM_BOUNDARY            BITS_PER_WORD
 210 #define STACK_BOUNDARY           BITS_PER_WORD
 211 #define FUNCTION_BOUNDARY        BITS_PER_UNIT
 212 #define BIGGEST_ALIGNMENT        BITS_PER_WORD
 213 #define BIGGEST_FIELD_ALIGNMENT  BITS_PER_WORD
 214
 215 #define EMPTY_FIELD_BOUNDARY  BITS_PER_WORD
 216
 217 #define CONSTANT_ALIGNMENT(EXP, ALIGN) BITS_PER_WORD
 218 #define DATA_ALIGNMENT(TYPE, ALIGN) BITS_PER_WORD
 219 #define LOCAL_ALIGNMENT(TYPE, ALIGN) BITS_PER_WORD
 220
 221 #define STRICT_ALIGNMENT  1
 222
 223 #define MAX_FIXED_MODE_SIZE 32
 224
 225 #define TARGET_FLOAT_FORMAT  IEEE_FLOAT_FORMAT
 226
 227
 228 #define SHORT_TYPE_SIZE 16
 229 #define INT_TYPE_SIZE 32
 230 #define FLOAT_TYPE_SIZE 32
 231 #define LONG_TYPE_SIZE BITS_PER_WORD
 232 #define MAX_WCHAR_TYPE_SIZE 32
 233 #define DOUBLE_TYPE_SIZE 64
 234 #define LONG_LONG_TYPE_SIZE 64
 235
 236 #define DEFAULT_SIGNED_CHAR  0
 237
 238 #define DEFAULT_SHORT_ENUMS  0
 239
 240 #define TARGET_BELL                     007
 241 #define TARGET_BS                       010
 242 #define TARGET_TAB                      011
 243 #define TARGET_NEWLINE                  012
 244 #define TARGET_VT                       013
 245 #define TARGET_FF                       014
 246 #define TARGET_CR                       015
 247
 248 #define R_R0          (0)
 249 #define R_R1          (1)
 250 #define R_R2          (2)
 251 #define R_R3          (3)
 252 #define R_NUM         (32)
 253
 254
 255 #define FIRST_PSEUDO_REGISTER     36
 256
 257 #define FIXED_REGISTERS \
 258   /*0,1,2,3,4,5,6,7                                                    SP,PC,fp,ap*/ \
 259   { 1,1,1,1,1,1,1,1, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 1, 1, 1, 1}
 260
 261 #define CALL_USED_REGISTERS \
 262   /*0,1,2,3,4,5,6,7, 0,1,2,3,4,5,6,7, 0,1,2,3,4,5,6,7, 0,1,2,3,4,5,6,7,SP,PC,fp,ap*/ \
 263   { 1,0,1,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 0,0,0,0,0,0,0,0, 1, 1, 1, 1}
 264
 265 /* KLUDGE!
 266  *
 267  * We don't want GCC to use the memory mapped register r0-r7. Normally it
 268  * won't unless it has to.
 269  *
 270  * However, somewhere in GCC there is a clever mechanism to make the hard frame
 271  * register availble for general allocation even though it is marked as a
 272  * fixed register.
 273  *
 274  * Using R3(memory mapped register) is harmless, but not optimal.
 275  */
 276 #define REG_ALLOC_ORDER {\
 277         8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31, \
 278         0,1,2,3,4,5,6,7, \
 279         32, 33, 34, 35 }
 280
 281
 282 #define HARD_REGNO_NREGS(REGNO, MODE) ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD -1)/UNITS_PER_WORD)
 283
 284 /* we only allow >32 bits in non-memory mapped registers */
 285 #define HARD_REGNO_MODE_OK(REGNO, MODE) ((REGNO>=R_STACK_REG)||(GET_MODE_SIZE(MODE)<=UNITS_PER_WORD))
 286
 287 #define MODES_TIEABLE_P(MODE1, MODE2) 1
 288
 289 #define AVOID_CCMODE_COPIES
 290
 291 enum reg_class
 292 {
 293     NO_REGS,
 294     GENERAL_REGS,
 295     ALL_REGS,
 296     LIM_REG_CLASSES
 297 };
 298
 299 #define N_REG_CLASSES                   (int) LIM_REG_CLASSES
 300
 301 #define REG_CLASS_NAMES \
 302   { "NO_REGS",                                          \
 303     "GENERAL_REGS",                                     \
 304     "ALL_REGS" }
 305
 306 #define REG_CLASS_CONTENTS \
 307   {\
 308         {0, 0},              \
 309     {0xffffff0d, 0xf}, \
 310     {0xffffff0d, 0xf}, }
 311
 312 #define REGNO_REG_CLASS(REGNO) (((REGNO)<FIRST_PSEUDO_REGISTER)?GENERAL_REGS:ALL_REGS)
 313 #define BASE_REG_CLASS GENERAL_REGS
 314 #define INDEX_REG_CLASS GENERAL_REGS
 315 #define REG_CLASS_FROM_LETTER(C) NO_REGS
 316
 317 #define REGNO_OK_FOR_INDEX_P(REGNO) 1
 318
 319 #define REGNO_OK_FOR_BASE_P(REGNO) 1
 320
 321 #define PREFERRED_RELOAD_CLASS(X,CLASS) GENERAL_REGS
 322
 323 /* #define SMALL_REGISTER_CLASSES 0 */
 324
 325 /* #define CLASS_LIKELY_SPILLED_P(class)  1 */
 326
 327 #define CLASS_MAX_NREGS(CLASS, MODE) HARD_REGNO_NREGS(CLASS, MODE)
 328
 329 #define CONST_OK_FOR_LETTER_P(VALUE, C) 0
 330
 331 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 0
 332
 333 #define EXTRA_CONSTRAINT(X, C) 0
 334 #define EXTRA_MEMORY_CONSTRAINT(C,STR) 0
 335 #define EXTRA_ADDRESS_CONSTRAINT(C,STR) 0
 336
 337 #define STACK_GROWS_DOWNWARD
 338 #undef ARGS_GROW_DOWNWARD
 339
 340
 341 /* By letting the frame grow downwards, we'll have the
 342  * final stack slot assignments, the pseudo registers,
 343  * with the smallest offsets. This has a major impact
 344  * on code size
 345  */
 346 #define FRAME_GROWS_DOWNWARD
 347
 348
 349 #define STARTING_FRAME_OFFSET 0
 350
 351 #define FIRST_PARM_OFFSET(FUNDECL)  (0)
 352
 353 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) ((COUNT) == 0 \
 354    ? zpu_return_addr_rtx() \
 355    : NULL_RTX)
 356
 357 /* rtx for return address *before* prologue */
 358 #define INCOMING_RETURN_ADDR_RTX \
 359   gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM))
 360
 361 #define INCOMING_FRAME_SP_OFFSET 4
 362
 363
 364
 365 #define STACK_POINTER_REGNUM  R_SP
 366
 367 /* this will be eliminated. The magic trick here is to use a "fake frame pointer" that
 368  * is eliminated.
 369  *
 370  * Additional voodoo is to have the hard frame pointer late amongst the registers
 371  * so it isn't allocated when it is impossible to replace the
 372  * frame pointer with the stack pointer.
 373  *
 374  * It would be disaterous not to eliminate R_FAKE_FP, since it
 375  * doesn't actually exist
 376  */
 377 #define FRAME_POINTER_REGNUM  R_FAKE_FP
 378 #define HARD_FRAME_POINTER_REGNUM  R_R3
 379
 380 /* this will be eliminated*/
 381 #define ARG_POINTER_REGNUM  R_FAKE_AP
 382
 383 #define STATIC_CHAIN_REGNUM  R_R2
 384
 385 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca || current_function_has_nonlocal_goto)
 386
 387 #define ELIMINABLE_REGS {                                       \
 388         {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
 389         {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
 390         {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
 391         {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} \
 392                 }
 393
 394 /* avoid reload happily eliminating the arg pointer when
 395  * the frame pointer can't be eliminted.
 396  */
 397 #define CAN_ELIMINATE(FROM, TO) \
 398   ((TO) == STACK_POINTER_REGNUM ? ! frame_pointer_needed : 1)
 399
 400 #define INITIAL_ELIMINATION_OFFSET(from_reg,to_reg,offset) {offset=zpu_initial_elimination_offset(from_reg, to_reg);}
 401
 402 #define HAVE_POST_INCREMENT 1
 403
 404 #define HAVE_PRE_DECREMENT 1
 405
 406 #define PROMOTE_PROTOTYPES 1
 407
 408 #define ACCUMULATE_OUTGOING_ARGS 1
 409
 410 /* What does GCC do differently if we tell it that these registers are part of a
 411  * register window?
 412  */
 413 #define LOCAL_REGNO(REGNO) (((REGNO) >= R_STACK_REG) && ((REGNO) <= R_STACK_REG_LAST))
 414
 415
 416 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
 417
 418
 419 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
 420
 421 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED)  0
 422
 423 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED)  0
 424
 425 typedef struct {
 426   /* The first arg_regno free after scanning the arguments so far.  */
 427   int lst_free_reg;
 428
 429   /* The flag set by FUNCTION_ARG_PRESCAN saying we dont want to pass
 430      anything in registers for current call.  */
 431   int must_pass_in_stack;
 432 } CUMULATIVE_ARGS;
 433
 434
 435 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS)
 436
 437 #define RESET_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME)
 438
 439 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED)
 440
 441 #define FUNCTION_ARG_REGNO_P(REGNO)  0
 442
 443 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx (REG, TYPE_MODE (VALTYPE), R_R0)
 444
 445 #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, R_R0)
 446
 447 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R_R0 )
 448
 449
 450
 451 #define STRUCT_VALUE  0
 452 #define STRUCT_VALUE_INCOMING  0
 453
 454
 455 #define FUNCTION_PROFILER(FILE, LABELNO)
 456
 457 #define NO_PROFILE_COUNTERS     1
 458
 459
 460 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) {}
 461
 462
 463 /* Linktime relaxing is not an issue here w.r.t. making
 464  * sure that the trampoline is of constant size. Firstly
 465  * the trampoline template is placed in the read-only segment, so
 466  * there is no link-time relaxing, secondly, the machine code
 467  * below does not use any relaxable relocations.
 468  *
 469  * The fun part here is that we have to save & restore
 470  * the static chain register without screwing up the stack frame.
 471  *
 472  * We poke the return address to return to the trampoline in order to
 473  * restore the static chain register.
 474  *
 475  */
 476 #define TRAMPOLINE_TEMPLATE(FILE) \
 477 {                                               \
 478   fprintf ((FILE), "; save return address\n");  \
 479   fprintf ((FILE), "    nop\n");        \
 480   fprintf ((FILE), "    nop\n");        \
 481   fprintf ((FILE), "    nop\n");        \
 482   fprintf ((FILE), "    nop\n");        \
 483   fprintf ((FILE), "; save static chain register\n");   \
 484   fprintf ((FILE), "    nop\n");        \
 485   fprintf ((FILE), "    nop\n");        \
 486   fprintf ((FILE), "    nop\n");        \
 487   fprintf ((FILE), "    nop\n");        \
 488   fprintf ((FILE), "; load static chain register\n");   \
 489   fprintf ((FILE), "    pushpc ; 24 \n");       \
 490   fprintf ((FILE), "    im 4+24\n");    \
 491   fprintf ((FILE), "    add\n");        \
 492   fprintf ((FILE), "    load\n");       \
 493   fprintf ((FILE), "    im %d\n", STATIC_CHAIN_REGNUM*4);       \
 494   fprintf ((FILE), "    store\n");      \
 495   fprintf ((FILE), "; call function\n");        \
 496   fprintf ((FILE), "    pushpc ; 18\n");        \
 497   fprintf ((FILE), "    im 18\n");      \
 498   fprintf ((FILE), "    add\n");        \
 499   fprintf ((FILE), "    load\n");       \
 500   fprintf ((FILE), "    poppc\n");      \
 501   fprintf ((FILE), "; restore static chain register\n");        \
 502   fprintf ((FILE), "    nop\n");        \
 503   fprintf ((FILE), "    nop\n");        \
 504   fprintf ((FILE), "    nop\n");        \
 505   fprintf ((FILE), "    nop\n");        \
 506   fprintf ((FILE), "    nop\n");        \
 507   fprintf ((FILE), "; return to original caller\n");    \
 508   fprintf ((FILE), "    nop\n");        \
 509   fprintf ((FILE), "    nop\n");        \
 510   fprintf ((FILE), "    nop\n");        \
 511   fprintf ((FILE), "    nop\n");        \
 512   fprintf ((FILE), "    nop\n");        \
 513   fprintf ((FILE), "    nop\n");        \
 514   fprintf ((FILE), "    nop\n");        \
 515   fprintf ((FILE), "    nop\n");        \
 516   fprintf ((FILE), "    .long   0 ; address\n");                \
 517   fprintf ((FILE), "    .long   0 ; static chain value\n");             \
 518   fprintf ((FILE), "    .long   0 ; save area for static chain register\n");            \
 519   fprintf ((FILE), "    .long   0 ; saved return address\n");           \
 520 }
 521
 522 #define TRAMPOLINE_SIZE (32+16)
 523 /* The alignment of a trampoline, in bits.  */
 524 #define TRAMPOLINE_ALIGNMENT  32
 525
 526 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT)  \
 527 {                                                                       \
 528   emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 32+4)), \
 529                   (CXT));                                               \
 530   emit_move_insn (gen_rtx (MEM, SImode, plus_constant ((TRAMP), 32+0)), \
 531                   (FNADDR));                                            \
 532 }
 533
 534
 535 #define TARGET_MEM_FUNCTIONS
 536
 537 #define CONSTANT_ADDRESS_P(X)  CONSTANT_P(X)
 538
 539 /* reload can fail if we use more. This limit does not
 540  * apply to PC/SP. Reducing this from 10 to 2 had no measureable
 541  * impact on code size.
 542  */
 543 #define MAX_REGS_PER_ADDRESS  2
 544
 545
 546 #ifdef REG_OK_STRICT
 547 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL)   {if (zpu_legitimate_address(MODE, X, 1)) goto LABEL;}
 548 /* Nonzero if X is a hard reg that can be used as a base reg.  */
 549 #define REG_OK_FOR_BASE_P(X) (REGNO(X)<FIRST_PSEUDO_REGISTER)
 550 #else
 551 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL)   {if (zpu_legitimate_address(MODE, X, 0)) goto LABEL;}
 552 /* Nonzero if X is a hard reg that can be used as a base reg
 553    or if it is a pseudo reg.  */
 554 #define REG_OK_FOR_BASE_P(X) 1
 555 #endif
 556
 557 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
 558
 559
 560 #define LEGITIMIZE_ADDRESS(x, oldx, mode, win)
 561
 562 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)        \
 563  if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
 564
 565
 566 #define LEGITIMATE_CONSTANT_P(X) 1
 567
 568 /* We need to print registers here as they are valid addresses
 569  * that can be sent to __asm() blocks as arguments
 570  */
 571 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
 572 {\
 573     if (GET_CODE (X) == REG)    \
 574       {                                                                 \
 575         print_operand(STREAM, X, 0); \
 576       }                                                                 \
 577     else                                                                \
 578       goto FAIL;                                                        \
 579 }
 580
 581 #define NOTICE_UPDATE_CC(exp, insn) CC_STATUS_INIT
 582
 583
 584 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2)        4
 585
 586 #define MEMORY_MOVE_COST(MODE,CLASS,IN)         1
 587
 588 #define BRANCH_COST  2
 589 #define SLOW_BYTE_ACCESS  1
 590 #define MOVE_RATIO                          (1+1)
 591 #define NO_FUNCTION_CSE  1
 592 #define NO_RECURSIVE_FUNCTION_CSE  1
 593
 594
 595 #define TEXT_SECTION_ASM_OP  ".text"
 596 #define DATA_SECTION_ASM_OP  ".data"
 597
 598 #define BSS_SECTION_ASM_OP  ".bss"
 599
 600
 601 #define ASM_COMMENT_START                   "//"
 602 #define ASM_APP_ON                          ""
 603 #define ASM_APP_OFF                         ""
 604
 605 #define REGISTER_NAMES \
 606   { "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \
 607         "R8", "R9", "R10","R11","R12","R13","R14","R15", \
 608         "R16","R17","R18","R19","R20","R21","R22","R23", \
 609         "R24","R25","R26","R27","R28","R29","R30","R31", \
 610         "SP","PC", "*FAKEFRAMEPOINTER", "*FAKEARGPOINTER"}
 611
 612
 613 #define PRINT_OPERAND(STREAM, X, CODE) print_operand(STREAM, X, CODE)
 614
 615 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
 616   output_addr_const (STREAM, X);
 617
 618
 619 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) fprintf(STREAM, "im %d\nload\n", REGNO*4)
 620 #define ASM_OUTPUT_REG_POP(STREAM, REGNO)  fprintf(STREAM, "im %d\nstore\n", REGNO*4)
 621
 622 /* This is how to output an element of a case-vector that is absolute.  */
 623
 624 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE)  \
 625   fprintf (FILE, "\t.long .L%d\n", VALUE)
 626
 627 /* This is how to output an element of a case-vector that is relative.  */
 628
 629 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)  \
 630   fprintf (FILE, "\t.long .L%d-.L%d\n", VALUE, REL)
 631
 632
 633 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \
 634   fprintf (STREAM, "\t.balign %u;\n", 1 << (POWER));
 635
 636 #define DBX_REGISTER_NUMBER(REGNO)  (REGNO)
 637
 638
 639 #define CASE_VECTOR_MODE                    SImode
 640
 641
 642 #define CASE_VECTOR_PC_RELATIVE 0
 643
 644
 645 #define WORD_REGISTER_OPERATIONS
 646
 647
 648 #define LOAD_EXTEND_OP(MODE)  ZERO_EXTEND
 649
 650 #define MOVE_MAX  UNITS_PER_WORD
 651
 652 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)  1
 653
 654 #define STORE_FLAG_VALUE  1
 655
 656
 657 #define Pmode          SImode
 658
 659 #define FUNCTION_MODE  QImode
 660
 661 #define WORKSPACE_RESERVED_BYTES  (7 * UNITS_PER_WORD)
 662
 663 #define IN_WORDS(SIZE_IN_BYTES) \
 664   (((SIZE_IN_BYTES) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
 665
 666 #define WORD_ROUND(VALUE) \
 667   (((VALUE) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD)
 668
 669 #define FLOAT_OPERAND(N) \
 670   (GET_MODE_CLASS (GET_MODE (operands[N])) == MODE_FLOAT)
 671
 672 extern
 673 struct zpu_compare {
 674   struct rtx_def *op[2];   /* comparison operands */
 675   int fp;                  /* floating comparison required */
 676 } zpu_compare;
 677
 678 /* Point that a function's arguments should be processed (in calls.c)
 679    from last to first, so that the integer regstack will be in the
 680    proper order before a call insn; no stack rearrangement will be needed.
 681    It is not quite right to define this macro here as it was not
 682    intended for user redefinition, but this yields the desired effect. */
 683
 684 #define PUSH_ARGS_REVERSED 1    /* If it's last to first */
 685
 686
 687
 688 /* This is called before generating rtl for every function.  */
 689
 690 #define INIT_EXPANDERS
 691
 692
 693
 694
 695 #define TARGET_CPU_CPP_BUILTINS()               \
 696   do                                            \
 697     {                                           \
 698       builtin_define_std ("zpu");               \
 699     }                                           \
 700   while (0)
 701
 702
 703 #define GLOBAL_ASM_OP   "\t.globl\t"
 704
 705
 706 /* we use setjmp/longjmp for C++ exception handling... */
 707 #define DWARF2_UNWIND_INFO 0
 708
 709 /* ZPU hack! We have modified GCC to allow -fomit-frame-pointer to be more powerful */
 710 #define ALLOW_REF_TO_SP_IN_CHANGE_SP_INSN 1
 711
 712
 713 #undef DBX_OUTPUT_MAIN_SOURCE_FILE_END
 714 #define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME)                 \
 715   fprintf (FILE,                                                        \
 716            "\t.text\n.stabs \"\",%d,0,0,.Letext\n.Letext:\n", N_SO)
 717
 718
 719 /* see config/mips/elf.h */
 720
 721 /* Use __main method of constructor invocation.  */
 722 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
 723 /* On elf, we *do* have support for the .init and .fini sections, and we
 724    can put stuff in there to be executed before and after `main'.  We let
 725    crtstuff.c and other files know this by defining the following symbols.
 726    The definitions say how to change sections to the .init and .fini
 727    sections.  This is the same for all known elf assemblers.  */
 728
 729 #undef  INIT_SECTION_ASM_OP
 730 #define INIT_SECTION_ASM_OP     "\t.section\t.init"
 731 #undef  FINI_SECTION_ASM_OP
 732 #define FINI_SECTION_ASM_OP     "\t.section\t.fini"
 733
 734
 735 #undef  ASM_APP_ON
 736 #define ASM_APP_ON "#APP\n"
 737
 738 #undef  ASM_APP_OFF
 739 #define ASM_APP_OFF "#NO_APP\n"