toolchain/gcc/gcc/config/zpu/zpu.c

   1 /* Subroutines used for code generation on transputer.
   2    Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
   3
   4    Written by Øyvind Harboe <oyvind.harboe@zylin.com>
   5
   6 This file is part of GNU CC.
   7
   8 GNU CC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 2, or (at your option)
  11 any later version.
  12
  13 GNU CC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GNU CC; see the file COPYING.  If not, write to
  20 the Free Software Foundation, 59 Temple Place - Suite 330,
  21 Boston, MA 02111-1307, USA.  */
  22
  23 #include <stdio.h>
  24 #include <limits.h>
  25 #include "config.h"
  26 #include "system.h"
  27 #include "coretypes.h"
  28 #include "tm.h"
  29 #include "rtl.h"
  30 #include "tree.h"
  31 #include "tm_p.h"
  32 #include "regs.h"
  33 #include "real.h"
  34 #include "insn-config.h"
  35 #include "insn-flags.h"
  36 #include "expr.h"
  37 #include "recog.h"
  38 #include "reload.h"
  39 #include "output.h"
  40 #include "hard-reg-set.h"
  41 #include "real.h"
  42 #include "insn-config.h"
  43 #include "conditions.h"
  44 #include "output.h"
  45 #include "insn-attr.h"
  46 #include "flags.h"
  47 #include "libfuncs.h"
  48 #include "toplev.h"
  49 #include "basic-block.h"
  50 #include "function.h"
  51 #include "ggc.h"
  52
  53 #include "target.h"
  54 #include "target-def.h"
  55
  56 const char *zpu_board_name;
  57
  58
  59
  60 static const int MAX_ADDSP=15*4;
  61 /* GCC's concept of registers and the ZPU's concept of registers sometimes,
  62  * but not always refer to the same
  63  *
  64  * Hence we have a table of rtx expressions that redirect to the correct
  65  * location
  66  */
  67 static GTY(()) rtx reg[R_NUM];
  68 static unsigned int regStackTop;
  69
  70 static int regMapper[R_NUM-R_STACK_REG];
  71 static int debug_output=0;
  72 static rtx current_insn;
  73 static int stackOffset; /* when the RTL references the SP, we need to track the offset */
  74
  75 #define missingOperand() \
  76 {\
  77                 fprintf(stderr, "Instruction emit failure:\n"); \
  78                 debug_rtx (current_insn); \
  79                 fprintf(stderr, "\n"); \
  80                 abort(); \
  81 }
  82
  83 static int zpu_first_only_push(rtx x, rtx find);
  84 static int loadstoresp_offset(rtx operand, int *found);
  85 static void zpu_storesp(int offset);
  86 static int prevImmediate;
  87 static void zpu_asm(const char *format, rtx *operands);
  88 static void store_to_operand(rtx *operand);
  89 static void zpu_loadsp(int offset);
  90 static const char *zpu_immediate(rtx *operand);
  91 static int calcStackRegSize(void);
  92 static int totalStackOffset(void);
  93
  94 static int stackSlotNum(int regNo)
  95 {
  96         if (regMapper[regNo-R_STACK_REG]==-1)
  97         {
  98                 missingOperand();
  99         }
 100         return regMapper[regNo-R_STACK_REG];
 101 }
 102
 103 /* sp + offset to stack register */
 104 static int stackRegOffset(rtx operand)
 105 {
 106         int num;
 107         num=stackSlotNum(REGNO(operand));
 108         return current_function_outgoing_args_size+num*4-totalStackOffset();
 109 }
 110
 111 static int addSpRange(rtx operand, int *found)
 112 {
 113         *found=0;
 114
 115         if (current_function_calls_alloca)
 116         {
 117                 /* no way to know in this case */
 118                 return -1;
 119         }
 120
 121         if ((GET_CODE(operand)==REG)&&(REGNO(operand)<R_NUM))
 122         {
 123                 if (GET_CODE(reg[REGNO(operand)])==MEM)
 124                 {
 125                         return loadstoresp_offset(reg[REGNO(operand)], found)-totalStackOffset();
 126                 } else
 127                 {
 128                         if ((REGNO(operand)>=R_STACK_REG)&&
 129                                 (REGNO(operand)<=R_STACK_REG_LAST))
 130                         {
 131                                 *found=1;
 132                                 return stackRegOffset(operand);
 133                         }
 134                 }
 135         } else
 136         {
 137                 return loadstoresp_offset(operand, found)-totalStackOffset();
 138         }
 139         return -1;
 140 }
 141
 142 static void pushRegAddress(rtx operand)
 143 {
 144         /* painful handling of compatiblity with obscure case
 145          * of alloca or dynamically sized objects on stack
 146          */
 147         int num;
 148         rtx offset;
 149         rtx regAddr;
 150
 151         num=stackSlotNum(REGNO(operand));
 152         regAddr=GEN_INT(REGNO(hard_frame_pointer_rtx)*4);
 153         zpu_asm("im %0", &regAddr);
 154         zpu_asm("load", NULL);
 155         offset=GEN_INT(-(get_frame_size()+calcStackRegSize())+num*4);
 156         zpu_immediate(&offset);
 157         stackOffset+=4;
 158         zpu_asm("add", NULL);
 159 }
 160
 161
 162 static void pushreg(rtx operand)
 163 {
 164         if (REGNO(operand)<R_STACK_REG)
 165         {
 166                 if (REGNO(operand)<R_NUM)
 167                 {
 168                         rtx addr;
 169                         addr=GEN_INT(REGNO(operand)*4);
 170                         zpu_asm("im %0", &addr);
 171                         zpu_asm("load", &operand);
 172                 } else
 173                 {
 174                         missingOperand();
 175                 }
 176         } else if (REGNO(operand)<R_NUM)
 177         {
 178                 if (current_function_calls_alloca)
 179                 {
 180                         pushRegAddress(operand);
 181                         zpu_asm("load", NULL);
 182                 } else
 183                 {
 184                         int num;
 185                         num=stackSlotNum(REGNO(operand));
 186                         zpu_loadsp(current_function_outgoing_args_size+num*4);
 187                         stackOffset+=4;
 188                 }
 189         } else
 190         {
 191                 missingOperand();
 192         }
 193 }
 194
 195 static void popreg(rtx operand)
 196 {
 197         if (REGNO(operand)<R_STACK_REG)
 198         {
 199                 if (REGNO(operand)<R_NUM)
 200                 {
 201                         rtx addr;
 202                         addr=GEN_INT(REGNO(operand)*4);
 203                         zpu_asm("im %0", &addr);
 204                         zpu_asm("store", &operand);
 205                 }
 206         } else if (REGNO(operand)<R_NUM)
 207         {
 208                 if (current_function_calls_alloca)
 209                 {
 210                         pushRegAddress(operand);
 211                         zpu_asm("store", NULL);
 212                 } else
 213                 {
 214                         int num;
 215                         num=stackSlotNum(REGNO(operand));
 216                         zpu_storesp(current_function_outgoing_args_size+num*4);
 217                 }
 218         } else
 219         {
 220                 missingOperand();
 221         }
 222 }
 223
 224
 225 /* returns true if both are registers and they are the same register*/
 226 static int compareReg(rtx a, rtx b)
 227 {
 228         if (GET_CODE(a)!=REG)
 229         {
 230                 return 0;
 231         }
 232         if (GET_CODE(b)!=REG)
 233         {
 234                 return 0;
 235         }
 236
 237         return REGNO(a)==REGNO(b);
 238 }
 239
 240 static void comment(const char *format ATTRIBUTE_UNUSED, rtx *operands ATTRIBUTE_UNUSED)
 241 {
 242 #if 0
 243         /* the testsuite chokes on this */
 244         output_asm_insn(format, operands);
 245 #endif
 246 }
 247
 248 const char * zpu_asm_multi(const char *format, rtx *operands, int byteCount ATTRIBUTE_UNUSED)
 249 {
 250         int im;
 251         /* imX, matches IM & IMPCREL */
 252         im=strncmp("im", format, 2)==0;
 253
 254         if (im&&prevImmediate)
 255         {
 256                 /* we need to break the pipe when two immediate instructions follow eachother */
 257                 output_asm_insn("nop", operands);
 258         }
 259         output_asm_insn(format, operands);
 260
 261         prevImmediate=im;
 262         return "";
 263 }
 264
 265 static void zpu_asm(const char *format, rtx *operands)
 266 {
 267         zpu_asm_multi(format, operands, 1);
 268 }
 269
 270
 271
 272 struct RegStackEntry GTY(())
 273 {
 274         rtx reg; /* the current location of the register */
 275 };
 276
 277 static GTY(()) struct RegStackEntry regStack[R_NUM*2];
 278 static const unsigned int regStackSize=sizeof(regStack)/sizeof(*regStack);
 279
 280 static rtx next_insn_saved;
 281 static rtx current_insn_saved;
 282
 283 static void storeToReg(rtx newLocation, rtx origReg)
 284 {
 285         comment("; explicit pop", &newLocation);
 286         if (GET_CODE(newLocation)==REG)
 287         {
 288                 popreg(newLocation);
 289         } else
 290         {
 291                 int found;
 292                 int loadsp_offset=loadstoresp_offset(newLocation, &found);
 293                 if (!found)
 294                 {
 295                         fprintf(stderr, "\nZPU: corrupt regStack\n");
 296                         missingOperand();
 297                 }
 298
 299                 comment("; store to register on stack %0", &origReg);
 300                 zpu_storesp(loadsp_offset);
 301         }
 302 }
 303
 304
 305 static void persistReg(rtx t)
 306 {
 307         storeToReg(reg[REGNO(t)], t);
 308         stackOffset+=4;
 309 }
 310
 311
 312 static void discardRegStackTop(int persist)
 313 {
 314         rtx newLocation;
 315         int i;
 316         if ((regStackTop>regStackSize)||(regStackTop<=0))
 317         {
 318                 fprintf(stderr, "ZPU: corrupt regStack\n");
 319                 missingOperand();
 320         }
 321
 322         /* this is where we pop the register to... */
 323         newLocation=gen_rtx_REG(SImode, REGNO(regStack[regStackTop-1].reg));
 324
 325         /* ...or is it still on the stack? */
 326         for (i=regStackTop-2; i>=0; i--)
 327         {
 328                 if (compareReg(regStack[regStackTop-1].reg, regStack[i].reg))
 329                 {
 330                         newLocation=gen_rtx_MEM(SImode,
 331                                 gen_rtx_PLUS(SImode, gen_rtx_REG(SImode, R_SP), GEN_INT(-(i+1)*4)));
 332                         break;
 333                 }
 334         }
 335
 336         reg[REGNO(regStack[regStackTop-1].reg)]=newLocation;
 337
 338         if (persist)
 339         {
 340                 /* pop the register into the current location */
 341                 storeToReg(newLocation, regStack[regStackTop-1].reg);
 342         }
 343
 344         regStackTop--;
 345 }
 346
 347 static void popRegStack(void)
 348 {
 349         discardRegStackTop(1);
 350 }
 351
 352 static void pushRegStack(rtx t)
 353 {
 354         if (regStackTop>=regStackSize)
 355         {
 356                 fprintf(stderr, "ZPU: corrupt regStack\n");
 357                 missingOperand();
 358         }
 359
 360         regStack[regStackTop].reg=t;
 361         regStackTop++;
 362
 363         /* GCC does not know that we are changing the stack pointer.
 364          *
 365          * Hence the saved registers are at a negative offset to GCC's concept of
 366          * SP
 367          */
 368         reg[REGNO(t)]=gen_rtx_MEM(SImode,
 369                 gen_rtx_PLUS(SImode, gen_rtx_REG(SImode, R_SP), GEN_INT(-regStackTop*4)));
 370 }
 371
 372
 373 static int zpu_noop_set(rtx insn)
 374 {
 375         rtx set;
 376         set=single_set(insn);
 377         if (set!=NULL_RTX)
 378         {
 379                 return
 380                     GET_CODE (SET_SRC (set)) == REG
 381             && GET_CODE (SET_DEST (set)) == REG
 382             && REGNO (SET_SRC (set)) == REGNO (SET_DEST (set));
 383         }
 384         return 0;
 385 }
 386
 387 static int zpu_can_be_split(rtx insn)
 388 {
 389         rtx set;
 390         set=single_set(insn);
 391         if (set!=NULL_RTX)
 392         {
 393                 return (GET_MODE(SET_SRC (set)) != SImode);
 394         }
 395         return 0;
 396 }
 397
 398
 399 /* it is safe to err on the side of caution here and return 0
 400  * if we don't know.
 401  */
 402 static rtx zpu_next_insn(rtx insn)
 403 {
 404   while (insn)
 405     {
 406       insn = NEXT_INSN (insn);
 407       switch (GET_CODE(insn))
 408       {
 409         case JUMP_INSN:
 410         return insn;
 411
 412         case INSN:
 413                         if (zpu_noop_set(insn))
 414                         {
 415                         /* DRAGONS! we must skip noop moves, because they
 416                          * are eliminated by the emitter
 417                          */
 418                          break;
 419                 }
 420
 421                 if (zpu_can_be_split(insn))
 422                 {
 423                         return NULL;
 424                 }
 425
 426                         return insn;
 427
 428                 /* skip */
 429                 case NOTE:
 430         break;
 431
 432         default:
 433         /* we don't handle these */
 434         return NULL;
 435       }
 436     }
 437
 438   return insn;
 439 }
 440
 441 static int stackPlusConst(rtx operand, int *found)
 442 {
 443         rtx op0,op1;
 444         *found=0;
 445         if(GET_CODE(operand) != PLUS)
 446         {
 447                 return 0;
 448         }
 449         op0=XEXP (operand, 0);
 450         op1=XEXP (operand, 1);
 451         if((GET_CODE(op0)==REG) &&(REGNO(op0)==R_SP)
 452                                         && (GET_CODE(op1)==CONST_INT))
 453         {
 454                 *found=1;
 455                 return INTVAL(op1);
 456         }
 457         if((GET_CODE(op1)==REG) &&(REGNO(op1)==R_SP)
 458                                         && (GET_CODE(op0)==CONST_INT))
 459         {
 460                 *found=1;
 461                 return INTVAL(op0);
 462         }
 463         return 0;
 464 }
 465
 466 static int loadstoresp_offset(rtx operand, int *found)
 467 {
 468         *found=0;
 469         if (GET_MODE(operand)!=SImode)
 470         {
 471                 return -1;
 472         }
 473         if (GET_CODE(operand)!=MEM)
 474         {
 475                 return -1;
 476         }
 477         operand=XEXP(operand, 0);
 478
 479         if ((GET_CODE(operand)==REG)&&(REGNO(operand)==R_SP))
 480         {
 481                 *found=1;
 482                 return 0;
 483         }
 484         return stackPlusConst(operand, found);
 485 }
 486
 487
 488
 489 int zpu_binary_operator (rtx op  ATTRIBUTE_UNUSED, enum machine_mode mode ATTRIBUTE_UNUSED)
 490 {
 491         if (GET_MODE(op)!=SImode)
 492         {
 493                 return 0;
 494         }
 495
 496         switch (GET_CODE(op))
 497         {
 498                 case LE:
 499                 case GE:
 500                 case LEU:
 501                 case GEU:
 502                 case GT:
 503                 case LT:
 504                 case GTU:
 505                 case LTU:
 506             case COMPARE:
 507             case ASHIFT:
 508             case XOR:
 509
 510
 511                 case IOR:
 512                 case AND:
 513                 case MINUS:
 514                 case PLUS:
 515
 516                 return 1;
 517             case ASHIFTRT:
 518               return TARGET_ASHIFTRT;
 519             case LSHIFTRT:
 520               return TARGET_LSHIFTRT;
 521                 case MULT:
 522                   return TARGET_MULT;
 523                 case DIV:
 524                   return TARGET_DIV;
 525                 case MOD:
 526                   return TARGET_MOD;
 527
 528                 default:
 529                 break;
 530         }
 531         return 0;
 532 }
 533
 534
 535
 536
 537 int zpu_unary_operator (rtx op  ATTRIBUTE_UNUSED, enum machine_mode mode ATTRIBUTE_UNUSED)
 538 {
 539         if (GET_MODE(op)!=SImode)
 540         {
 541                 return 0;
 542         }
 543
 544         switch (GET_CODE(op))
 545         {
 546                 case NEG:
 547                 case NOT:
 548                 return 1;
 549
 550                 default:
 551                 break;
 552         }
 553         return 0;
 554 }
 555
 556 static int countReg;
 557
 558 static int opCheckTerminal(rtx op, enum machine_mode mode ATTRIBUTE_UNUSED, int strict)
 559 {
 560         if (CONSTANT_P(op)&&(GET_CODE(op)!=CONST_DOUBLE))
 561         {
 562                 return 1;
 563         }
 564
 565         switch (GET_CODE(op))
 566         {
 567             case REG:
 568                 if ((REGNO(op)<FIRST_PSEUDO_REGISTER)||!strict)
 569                 {
 570                         if ((REGNO(op)!=R_PC)&&(REGNO(op)!=R_SP))
 571                         {
 572                                 countReg++;
 573                         }
 574                         return 1;
 575                 }
 576                 break;
 577
 578             default:
 579             break;
 580         }
 581
 582         return 0;
 583 }
 584
 585 /* This function is not about what the ZPU is capable of, but what
 586  * the GCC & the backend wants/needs.
 587  */
 588 static int opCheck(rtx op, enum machine_mode mode, int strict)
 589 {
 590         switch (GET_CODE(op))
 591         {
 592                 /* we support only *2,4,8 */
 593             case MULT:
 594                 if (opCheckTerminal(XEXP(op, 0), mode, strict))
 595                 {
 596                                 if (GET_CODE(XEXP(op, 1))==CONST_INT)
 597                                 {
 598                                         int c=INTVAL(XEXP(op, 1));
 599                                         if ((c==2)||(c==4)||(c==8))
 600                                         {
 601                                                 return 1;
 602                                         }
 603                                 }
 604                 }
 605                 return 0;
 606             case PLUS:
 607                 return opCheckTerminal(XEXP(op, 0), mode, strict)&&
 608                 opCheckTerminal(XEXP(op, 1), mode, strict);
 609
 610             case PRE_DEC:
 611                 if (REG_P(XEXP(op, 0))&&(REGNO(XEXP(op, 0))==R_SP))
 612                 {
 613                         return 1;
 614                 }
 615                 break;
 616
 617             case POST_INC:
 618                 if (((mode==DFmode)||(mode==DImode))&&
 619                         REG_P(XEXP(op, 0))&&
 620                         (REGNO(XEXP(op, 0))==R_SP))
 621                 {
 622                         return 1;
 623                 }
 624
 625                 if ((mode!=SImode)&&(mode!=HImode)&&(mode!=QImode))
 626                 {
 627                         return 0;
 628                 }
 629                 if (REG_P(XEXP(op, 0))&&
 630                 ((REGNO(XEXP(op, 0))<=R_SP)
 631                 ||
 632                 (!strict&&(REGNO(XEXP(op, 0))>=FIRST_PSEUDO_REGISTER))
 633
 634                 ))
 635
 636                 {
 637                         return 1;
 638                 }
 639                 break;
 640
 641             default:
 642             return opCheckTerminal(op, mode, strict);
 643         }
 644
 645         return 0;
 646 }
 647
 648
 649
 650 int zpu_legitimate_address(enum machine_mode mode ATTRIBUTE_UNUSED, rtx x ATTRIBUTE_UNUSED, int strict ATTRIBUTE_UNUSED)
 651 {
 652         countReg=0;
 653
 654         if (opCheck(x, SImode, strict))
 655         {
 656                 return countReg<MAX_REGS_PER_ADDRESS;
 657         }
 658         return 0;
 659 }
 660
 661 void print_operand (FILE *file, rtx op, int letter)
 662 {
 663
 664         if (letter=='R')
 665         {
 666                 print_rtl (file, op);
 667                 return;
 668         }
 669
 670         switch (GET_CODE (op))
 671         {
 672                 case PLUS:
 673                 print_operand(file, XEXP(op, 0), letter);
 674                 fprintf(file, "+");
 675                 print_operand(file, XEXP(op, 1), letter);
 676                 break;
 677                 case REG:
 678                         if (letter=='X')
 679                         {
 680                         fprintf(file, "%d", REGNO(op)*4);
 681                         } else
 682                         {
 683                         fprintf(file, "%s", reg_names[REGNO (op)]);
 684                         }
 685                 break;
 686
 687             case CONST_DOUBLE:
 688             {
 689                 if (GET_MODE(op)==SFmode)
 690                 {
 691                               REAL_VALUE_TYPE r;
 692                               long l;
 693
 694                               REAL_VALUE_FROM_CONST_DOUBLE (r, op);
 695                               REAL_VALUE_TO_TARGET_SINGLE (r, l);
 696                               asm_fprintf (file, "%I0x%lx", l);
 697                 }
 698                 #if 0
 699                 else if (GET_MODE(op)==DFmode)
 700                 {
 701                               REAL_VALUE_TYPE r;
 702                               long l[2];
 703
 704                               REAL_VALUE_FROM_CONST_DOUBLE (r, op);
 705                               REAL_VALUE_TO_TARGET_DOUBLE (r, l);
 706                               asm_fprintf (file, "0x%08x%08x", l[0], l[1]);
 707                 }
 708                 #endif
 709                 else
 710                 {
 711                                 output_addr_const(file, op);
 712                 }
 713                 break;
 714             }
 715             case CONST_INT:
 716                 fprintf(file, "%d", (int)INTVAL (op));
 717                         break;
 718
 719             case LABEL_REF:
 720             case SYMBOL_REF:
 721                 case CODE_LABEL:
 722                 output_addr_const(file, op);
 723                         break;
 724
 725                 case MEM:
 726                         if (letter!='X')
 727                         {
 728                                 fprintf(file, "(");
 729                         }
 730                         print_operand(file, XEXP (op, 0), letter);
 731                         if (letter!='X')
 732                         {
 733                                 fprintf(file, ")");
 734                         }
 735                         break;
 736
 737
 738                 default:
 739                         output_addr_const(file, op);
 740                         break;
 741         }
 742 }
 743
 744
 745
 746
 747
 748
 749 static void initGenerate(rtx insn  ATTRIBUTE_UNUSED)
 750 {
 751         current_insn=insn;
 752
 753         if ((next_insn_saved!=NULL) && (current_insn!=next_insn_saved))
 754         {
 755                 rtx t;
 756                 fprintf(stderr, "ZPU: zpu_next_insn() broken\n");
 757
 758                 debug_rtx(current_insn_saved);
 759
 760                 /* for debugging purposes it is useful to look this up again so as
 761                  * to be able to step through the code
 762                  */
 763                 t=zpu_next_insn(current_insn_saved);
 764
 765                 missingOperand();
 766         }
 767
 768         stackOffset=0;
 769 }
 770
 771 static int totalStackOffset(void)
 772 {
 773         int t;
 774         /* this is the absolute difference between the ZPU stack
 775          * pointer and GCC's concept of a stack pointer
 776          */
 777         t=stackOffset-regStackTop*4;
 778         if (t>0)
 779         {
 780                 fprintf(stderr, "ZPU: illegal stack offset %d\n", -t);
 781                 missingOperand();
 782         }
 783         return t;
 784 }
 785
 786 static void zpu_pushspadd(int offset)
 787 {
 788   rtx t;
 789         if (TARGET_PUSHSPADD)
 790         {
 791                 t=GEN_INT((offset+4)/4);
 792                 zpu_asm("im %0", &t);
 793                 zpu_asm("pushspadd", &t);
 794         } else
 795         {
 796                 t=GEN_INT(offset);
 797                 zpu_asm("pushsp", &t);
 798                 if (offset!=0)
 799                   {
 800                     zpu_asm("im %0", &t);
 801                     zpu_asm("add", &t);
 802                   }
 803         }
 804 }
 805
 806 static void zpu_addsp(int offset)
 807 {
 808   rtx t;
 809                 t=GEN_INT(offset);
 810                         if (TARGET_ADDSP)
 811                           {
 812                             zpu_asm("addsp %0", &t);
 813                           } else
 814                             {
 815                             zpu_asm("pushsp", NULL);
 816                             if (offset!=0)
 817                               {
 818                             zpu_asm("im %0", &t);
 819                             zpu_asm("add", NULL);
 820                               }
 821                             zpu_asm("load", NULL);
 822                             zpu_asm("add", NULL);
 823                             }
 824 }
 825
 826 static void zpu_coreloadsp(int offset)
 827 {
 828   rtx t;
 829         if (offset<0)
 830         {
 831                 missingOperand();
 832         }
 833
 834         t=GEN_INT(offset);
 835         if (TARGET_LOADSP&&(offset/4<32))
 836         {
 837                 zpu_asm("loadsp %0", &t);
 838         } else
 839         {
 840                 zpu_pushspadd(offset);
 841                 zpu_asm("load", &t);
 842         }
 843
 844 }
 845
 846
 847 static void zpu_loadsp(int offset)
 848 {
 849
 850         offset-=totalStackOffset();
 851
 852         zpu_coreloadsp(offset);
 853         stackOffset-=4;
 854 }
 855
 856
 857 static void zpu_storesp(int offset)
 858 {
 859         rtx t;
 860         offset-=totalStackOffset();
 861
 862         if (offset<0)
 863         {
 864                 missingOperand();
 865         }
 866
 867         if (TARGET_STORESP&&(offset/4<32))
 868         {
 869                 t=GEN_INT(offset);
 870                 zpu_asm("storesp %0", &t);
 871         } else
 872         {
 873                 zpu_pushspadd(offset);
 874                 zpu_asm("store", &t);
 875         }
 876 }
 877
 878
 879
 880 static int zpu_stack_change(rtx x)
 881 {
 882         rtx set;
 883         set=single_set(x);
 884         if (set!=NULL_RTX)
 885         {
 886                 rtx dest=SET_DEST(set);
 887                 rtx src=SET_SRC(set);
 888                 if ((GET_CODE(dest)==REG)&&(REGNO(dest)==R_SP))
 889                 {
 890                         return 1;
 891                 }
 892
 893                 if (GET_CODE(dest)==MEM)
 894                 {
 895                         if (GET_CODE(XEXP(dest, 0))==PRE_DEC)
 896                         {
 897                                 if (REG_P(XEXP(XEXP(dest, 0), 0))&&REGNO(XEXP(XEXP(dest, 0), 0))==R_SP)
 898                                 {
 899                                         return 1;
 900                                 }
 901                         }
 902                 }
 903                 if ((GET_CODE(dest)==REG)&&(REGNO(dest)==R_SP))
 904                 {
 905                         return 1;
 906                 }
 907                 if (GET_CODE(src)==MEM)
 908                 {
 909                         if (GET_CODE(XEXP(src, 0))==POST_INC)
 910                         {
 911                                 if (REG_P(XEXP(XEXP(src, 0), 0))&&REGNO(XEXP(XEXP(src, 0), 0))==R_SP)
 912                                 {
 913                                         return 1;
 914                                 }
 915                         }
 916                 }
 917         }
 918         return 0;
 919 }
 920
 921
 922 static int isInBasicBlock(rtx insn)
 923 {
 924         if (insn==NULL_RTX)
 925         {
 926                 return 0;
 927         }
 928         if (GET_CODE(insn)==INSN)
 929         {
 930                 if (!zpu_stack_change(insn))
 931                 {
 932                         rtx set;
 933                         set=single_set(insn);
 934                         if (set!=NULL_RTX)
 935                         {
 936                                 if (GET_CODE(SET_SRC(set))!=ASM_OPERANDS)
 937                                 {
 938                                         return 1;
 939                                 }
 940                         }
 941                 }
 942         }
 943         return 0;
 944 }
 945
 946
 947
 948
 949 static void cleanupGenerate(void)
 950 {
 951         rtx t;
 952         if (stackOffset!=0)
 953         {
 954                 fprintf(stderr, "ZPU: stackOffset %d\n", stackOffset);
 955                 missingOperand();
 956         }
 957
 958         /* purge all dead registers off the stack */
 959         while ((regStackTop>0)&&find_regno_note(current_insn, REG_DEAD, REGNO(regStack[regStackTop-1].reg)))
 960         {
 961                 popRegStack();
 962         }
 963
 964         /* if we are at the end of the basic block, we must clean up
 965          * any unpopped registers
 966          */
 967         t=zpu_next_insn (current_insn);
 968         next_insn_saved=NULL_RTX;
 969         current_insn_saved=current_insn;
 970
 971         if (isInBasicBlock(t))
 972         {
 973                 next_insn_saved=t;
 974         } else
 975         {
 976                 comment("; barrier, purge regstack", &current_insn);
 977                 while (regStackTop>0)
 978                 {
 979                         popRegStack();
 980                 }
 981         }
 982 }
 983
 984
 985 static void push_operand_address(rtx *operand);
 986 static void push_operand_value(rtx *operand);
 987
 988
 989 static const char *zpu_immediate(rtx *operand)
 990 {
 991         zpu_asm("im %0", operand);
 992         stackOffset-=4;
 993         return "";
 994 }
 995
 996 static void zpu_neg(rtx *operand)
 997 {
 998   if (TARGET_NEG)
 999     {
1000         zpu_asm("neg", operand);
1001     } else
1002       {
1003         /* FIX!!! is this the right sequence? */
1004         zpu_asm("im 1", operand);
1005         zpu_asm("add", operand);
1006         zpu_asm("not", operand);
1007       }
1008 }
1009
1010
1011 /* is "find" the first operand to be pushed in "x".
1012  *
1013  * It is safe to err on the side of caution and say "no", it will
1014  * only potentially make the code ever so slightly less efficient.
1015  */
1016 static int zpu_first_push(rtx x, rtx find)
1017 {
1018   int i, j;
1019   enum rtx_code code;
1020   const char *format_ptr;
1021   int count;
1022
1023   if (x==NULL)
1024         return 0;
1025
1026         if (CONSTANT_P(x))
1027         {
1028                 return 0;
1029         }
1030
1031
1032         code=GET_CODE(x);
1033   switch (code)
1034     {
1035         case EXPR_LIST:
1036         return 0;
1037
1038         case SET:
1039                 return zpu_first_push(SET_SRC(x), find);
1040
1041                 case PLUS:
1042                 case XOR:
1043                 case AND:
1044                 case IOR:
1045                 return zpu_first_push(XEXP(x, 0), find)||zpu_first_push(XEXP(x, 1), find);
1046
1047                 case REG:
1048                 return (x==find);
1049
1050                 /* these are handled by the generic code below */
1051                 case INSN:
1052                 break;
1053
1054         default:
1055         /* err on the side of caution */
1056         return 0;
1057     }
1058
1059
1060   format_ptr = GET_RTX_FORMAT (code);
1061   count = 0;
1062
1063   for (i = 0; i < GET_RTX_LENGTH (code); i++)
1064     {
1065       switch (*format_ptr++)
1066         {
1067         case 'e':
1068           return zpu_first_push (XEXP (x, i), find);
1069
1070         case 'E':
1071           for (j = 0; j < XVECLEN (x, i); j++)
1072             return zpu_first_push (XVECEXP (x, i, j), find);
1073         }
1074     }
1075   return 0;
1076 }
1077
1078 static void zpu_call_asm(void)
1079 {
1080   if (TARGET_CALL)
1081     {
1082    zpu_asm("call", NULL);
1083     } else
1084       {
1085
1086    zpu_asm("pushsp ; CALL insn - duplicate top of stack", NULL);
1087    zpu_asm("load", NULL);
1088    zpu_asm("im 6 ; post POPC address", NULL);
1089    zpu_asm("pushpc", NULL);
1090    zpu_asm("add", NULL);
1091    zpu_asm("pushsp", NULL);
1092    zpu_asm("im 4", NULL);
1093    zpu_asm("add", NULL);
1094    zpu_asm("store", NULL);
1095    zpu_asm("poppc ; call function ", NULL);
1096
1097       }
1098 }
1099
1100
1101 static void zpu_gen_call(rtx *operand)
1102 {
1103         comment("/* call %R0 */", operand);
1104
1105         if (GET_CODE(operand[0])!=MEM)
1106         {
1107                 missingOperand();
1108         }
1109
1110         if (TARGET_CALLPCREL&&CONSTANT_P(XEXP(operand[0], 0)))
1111         {
1112                 zpu_asm("impcrel %0", operand);
1113                 zpu_asm("callpcrel", operand);
1114         } else
1115         {
1116                 /* address to call... */
1117                 push_operand_address(operand);
1118
1119                 if (regStackTop!=0)
1120                 {
1121                         fprintf(stderr, "ZPU: regStackTop %d\n", regStackTop);
1122                         missingOperand();
1123                 }
1124                 zpu_call_asm();
1125
1126
1127                 stackOffset+=4;
1128         }
1129 }
1130
1131
1132 static int
1133 zpu_count_occurrences (rtx x, rtx find)
1134 {
1135   int i, j;
1136   enum rtx_code code;
1137   const char *format_ptr;
1138   int count;
1139
1140   if (x==NULL)
1141         return 0;
1142
1143         code=GET_CODE(x);
1144   switch (code)
1145     {
1146         case EXPR_LIST:
1147         return 0;
1148         default:
1149         break;
1150     }
1151
1152   if ((GET_CODE(x) == REG)&&(REGNO(x)==REGNO(find)))
1153     return 1;
1154
1155
1156   format_ptr = GET_RTX_FORMAT (code);
1157   count = 0;
1158
1159   for (i = 0; i < GET_RTX_LENGTH (code); i++)
1160     {
1161       switch (*format_ptr++)
1162         {
1163         case 'e':
1164           count += zpu_count_occurrences (XEXP (x, i), find);
1165           break;
1166
1167         case 'E':
1168           for (j = 0; j < XVECLEN (x, i); j++)
1169             count += zpu_count_occurrences (XVECEXP (x, i, j), find);
1170           break;
1171         }
1172     }
1173   return count;
1174 }
1175
1176 /* we must err on the side of caution here. */
1177 static int zpu_first_only_push(rtx x, rtx find)
1178 {
1179         int result=0;
1180         if (zpu_first_push(x, find))
1181         {
1182           enum rtx_code code;
1183           code=GET_CODE(x);
1184           if (code==SET)
1185           {
1186                 x=SET_SRC(x);
1187           }
1188
1189                 if (zpu_count_occurrences(x, find)==1)
1190                 {
1191                         result=1;
1192                 }
1193         }
1194         return result;
1195 }
1196
1197
1198
1199
1200
1201
1202 /* if:
1203  * - the GCC-register is REG_DEAD or overwritten
1204  * - the GCC-register is on top of the stack
1205  * - the first push in the instruction is the GCC-register
1206  * - we only use the register once in the operation
1207  *
1208  * then we can simply remove the instructions that pop/push
1209  */
1210 static int dead_or_overwritten(rtx insn, rtx op)
1211 {
1212         int result=0;
1213         if (find_regno_note(insn, REG_DEAD, REGNO (op)))
1214         {
1215                 result=1;
1216         } else
1217         {
1218                 rtx set = single_set (insn);
1219                 if (set!=NULL_RTX)
1220                 {
1221                         if (SET_DEST(set)==op)
1222                         {
1223                                 result=1;
1224                         }
1225                 }
1226         }
1227
1228         return result;
1229 }
1230
1231 /* Check if the operand on the regStack is one of the operands and
1232  * push it first
1233  */
1234 static void push_assosiative(rtx operand)
1235 {
1236         if ((regStackTop>0)&&compareReg(regStack[regStackTop-1].reg, XEXP(operand, 1)))
1237         {
1238                 push_operand_value(&XEXP(operand, 1));
1239                 push_operand_value(&XEXP(operand, 0));
1240         } else
1241         {
1242                 /* either this is the other correct way, or it doesn't matter which way we
1243                  * do it.
1244                  */
1245                 push_operand_value(&XEXP(operand, 0));
1246                 push_operand_value(&XEXP(operand, 1));
1247         }
1248 }
1249
1250
1251 static int isFreePopPush(rtx *operand)
1252 {
1253         int freePopPush=0;
1254         if ((GET_CODE(*operand)==REG)&&(REGNO(*operand)<R_NUM)&&(GET_CODE(reg[REGNO(*operand)])==MEM))
1255         {
1256                 /* the GCC-register must be on top of the stack for a free push */
1257                 if (stackOffset==0)
1258                 {
1259                         if (regStackTop<=0)
1260                         {
1261                                 fprintf(stderr, "ZPU: regStack corrupted\n");
1262                                 missingOperand();
1263                         }
1264
1265                         if (dead_or_overwritten(current_insn, *operand))
1266                         {
1267                                 if (zpu_first_only_push(current_insn, *operand))
1268                                 {
1269                                         comment("; stripping regstack until free pop&push is found %0", operand);
1270                                         /* strip the regstack until we have a free pop */
1271                                         while (!compareReg(regStack[regStackTop-1].reg, *operand))
1272                                         {
1273                                                 popRegStack();
1274                                         }
1275
1276                                         if (regStackTop<=0)
1277                                         {
1278                                                 missingOperand();
1279                                         }
1280                                         comment("; eliminated pop&push %0", operand);
1281                                         if (debug_output)
1282                                         {
1283                                                 fprintf(stderr, "ZPU: eliminated poppush!\n");
1284                                                 debug_rtx (current_insn);
1285                                         }
1286                                         freePopPush=1;
1287                                 }
1288                         }
1289                 }
1290         }
1291         return freePopPush;
1292 }
1293
1294 static int postIncMemSize;
1295 static void push_operand_value(rtx *operand)
1296 {
1297         if (CONSTANT_P(*operand))
1298         {
1299                 zpu_immediate(operand);
1300                 return;
1301         }
1302
1303
1304         if (GET_CODE(*operand)==REG)
1305         {
1306                 if (REGNO(*operand)==R_PC)
1307                 {
1308                         zpu_asm("pushpc", operand);
1309                         stackOffset-=4;
1310                 } else if (REGNO(*operand)==R_SP)
1311                 {
1312                         zpu_asm("pushsp", operand);
1313
1314                         if (stackOffset>0)
1315                         {
1316                                 missingOperand();
1317                         }
1318
1319                         if (totalStackOffset()<0)
1320                         {
1321                                 rtx offset=GEN_INT(-totalStackOffset());
1322                                 comment("; stack adjustment offset", &offset);
1323                                 zpu_asm("im %0", &offset);
1324                                 zpu_asm("add", operand);
1325                         }
1326
1327                         stackOffset-=4;
1328                 } else if (REGNO(*operand)<R_NUM)
1329                 {
1330                         /* push GCC-register */
1331                         if (GET_CODE(reg[REGNO(*operand)])==MEM)
1332                         {
1333                                 if (isFreePopPush(operand))
1334                                 {
1335                                         /* we pretend we pushed it into the stack and clear the top
1336                                          * stack slot
1337                                          */
1338                                         discardRegStackTop(0);
1339                                         stackOffset-=4;
1340                                 } else
1341                                 {
1342                                         comment("; referring to unpopped register %0", operand);
1343                                         if (debug_output)
1344                                         {
1345                                                 fprintf(stderr, "ZPU: unpopped register\n");
1346                                                 debug_rtx (reg[REGNO(*operand)]);
1347                                         }
1348                                         push_operand_value(&reg[REGNO(*operand)]);
1349                                 }
1350                         } else
1351                         {
1352                                 pushreg(*operand);
1353                                 stackOffset-=4;
1354                         }
1355                 } else
1356                 {
1357                         missingOperand();
1358                 }
1359                 return;
1360         } else if (GET_CODE (*operand) == POST_INC)
1361         {
1362                 rtx reg;
1363                 rtx size;
1364                 reg=XEXP (*operand, 0);
1365                 if (GET_CODE(reg)!=REG)
1366                 {
1367                         missingOperand();
1368                 }
1369
1370                 if (REGNO(reg)>=R_SP)
1371                 {
1372                         missingOperand();
1373                 }
1374
1375                 push_operand_value(&reg);
1376
1377                 zpu_coreloadsp(0);
1378                 stackOffset-=4;
1379                 size=GEN_INT(postIncMemSize);
1380                 zpu_asm("im %0", &size);
1381                 zpu_asm("add", operand);
1382
1383                 /* we must not leave anything on the stack here */
1384                 persistReg(reg);
1385         } else if (GET_CODE (*operand) == MEM)
1386         {
1387                 int found;
1388                 int loadsp_offset=loadstoresp_offset(*operand, &found);
1389                 if ((GET_CODE(XEXP (*operand, 0))==POST_INC)&&(GET_CODE(XEXP (XEXP (*operand, 0), 0))==REG)&&(REGNO(XEXP (XEXP (*operand, 0), 0))==R_SP))
1390                 {
1391                         /* NOTE!!! We pop this off the stack even though it was placed there before we entered
1392                          * this tree expansion. */
1393                         stackOffset-=4;
1394                 } else if (found)
1395                 {
1396                         zpu_loadsp(loadsp_offset);
1397                 } else
1398                 {
1399                         postIncMemSize=GET_MODE_SIZE(GET_MODE(*operand));
1400
1401                         push_operand_value(&XEXP (*operand, 0));
1402                         switch (GET_MODE(*operand))
1403                         {
1404                                 case SFmode:
1405                                 case SImode:
1406                                         zpu_asm("load", operand);
1407                                         break;
1408                                 case HImode:
1409                                   if (TARGET_SHORTOP)
1410                                     {
1411                                         zpu_asm("loadh", NULL);
1412                                     } else
1413                                       {
1414                                         zpu_asm("im _loadh", NULL);
1415                                         zpu_call_asm();
1416                                       }
1417                                         break;
1418                                 case QImode:
1419                                   if (TARGET_BYTEOP)
1420                                     {
1421                                         zpu_asm("loadb", NULL);
1422                                     } else
1423                                       {
1424                                         zpu_asm("im _loadb", NULL);
1425                                         zpu_call_asm();
1426                                       }
1427
1428                                         break;
1429                                 default:
1430                                         fprintf(stderr, "FIX!!!! miissing operand\n");
1431                                         print_rtl(stderr, *operand);
1432                                         fprintf(stderr, "\n");
1433                                         break;
1434                         }
1435                 }
1436         } else if (GET_CODE(*operand)==PLUS)
1437         {
1438                 int found;
1439                 int offset;
1440                 offset=stackPlusConst(*operand, &found);
1441                 if (found&&((offset%4)==0))
1442                 {
1443                         offset-=totalStackOffset();
1444                         zpu_pushspadd(offset);
1445                         stackOffset-=4;
1446                 } else
1447                 if (isFreePopPush(&XEXP(*operand, 0))||isFreePopPush(&XEXP(*operand, 1)))
1448                 {
1449                         push_assosiative(*operand);
1450                         zpu_asm("add", operand);
1451                         stackOffset+=4;
1452                 } else
1453                 {
1454                         offset=addSpRange(XEXP(operand[0], 0), &found);
1455                         if ((!found)||((offset+4)>MAX_ADDSP))
1456                         {
1457                                 push_operand_value(&XEXP(operand[0], 0));
1458                                 offset=addSpRange(XEXP(operand[0], 1), &found);
1459                                 if (found&&(offset<=MAX_ADDSP))
1460                                 {
1461                                         zpu_addsp(offset);
1462                                 } else
1463                                 {
1464                                         push_operand_value(&XEXP(operand[0], 1));
1465                                         zpu_asm("add", NULL);
1466                                         stackOffset+=4;
1467                                 }
1468                         } else
1469                         {
1470                                 push_operand_value(&XEXP(operand[0], 1));
1471                                 zpu_addsp(offset+4);
1472                         }
1473                 }
1474         } else if ((GET_CODE(*operand)==COMPARE)||(GET_CODE(*operand)==MINUS))
1475         {
1476                 push_operand_value(&XEXP (*operand, 0));
1477                 push_operand_value(&XEXP (*operand, 1));
1478                 zpu_asm("sub", operand);
1479                 stackOffset+=4;
1480         } else if (GET_CODE(*operand)==LABEL_REF)
1481         {
1482                 zpu_immediate(operand);
1483         } else if (GET_CODE(*operand)==SYMBOL_REF)
1484         {
1485                 zpu_immediate(operand);
1486         } else  if (GET_CODE(*operand)==CODE_LABEL)
1487         {
1488                 zpu_immediate(operand);
1489         } else if (GET_CODE(*operand)==XOR)
1490         {
1491                 push_assosiative(*operand);
1492                 zpu_asm("xor", operand);
1493                 stackOffset+=4;  /* lost one */
1494         } else if (GET_CODE(*operand)==AND)
1495         {
1496                 push_assosiative(*operand);
1497                 zpu_asm("and", operand);
1498                 stackOffset+=4;  /* lost one */
1499         } else if (GET_CODE(*operand)==IOR)
1500         {
1501                 push_assosiative(*operand);
1502                 zpu_asm("or", operand);
1503                 stackOffset+=4;  /* lost one */
1504         } else if (GET_CODE(*operand)==NOT)
1505         {
1506                 push_operand_value(&XEXP (*operand, 0));
1507                 zpu_asm("not", operand);
1508         } else if (GET_CODE(*operand)==NEG)
1509         {
1510                 push_operand_value(&XEXP (*operand, 0));
1511                 zpu_neg(operand);
1512         } else if ((GET_CODE(*operand)==EQ)||(GET_CODE(*operand)==NE))
1513         {
1514                 push_operand_value(&XEXP (*operand, 0));
1515                 push_operand_value(&XEXP (*operand, 1));
1516                 if (TARGET_EQ)
1517                   {
1518                 zpu_asm("eq", operand);
1519                   } else
1520                     {
1521                 zpu_asm("im _eq", NULL);
1522                 zpu_call_asm();
1523                     }
1524                 if (GET_CODE(*operand)==NE)
1525                 {
1526
1527                         zpu_asm("not", operand);
1528                         zpu_asm("im 1", operand);
1529                         zpu_asm("and", operand);
1530                 }
1531                 stackOffset+=4;  /* lost one */
1532         } else if ((GET_CODE(*operand)==LE)||(GET_CODE(*operand)==GE)||
1533                    (GET_CODE(*operand)==LEU)||(GET_CODE(*operand)==GEU)||
1534                    (GET_CODE(*operand)==GT)||(GET_CODE(*operand)==LT)||
1535                    (GET_CODE(*operand)==GTU)||(GET_CODE(*operand)==LTU))
1536         {
1537                 int sign;
1538                 int flip_args;
1539                 int equal;
1540                 int code=GET_CODE(*operand);
1541
1542                 comment("/* %R0 */", operand);
1543
1544                 /* 'less than' is the base case here and then we tweak it into the
1545                  * other cases
1546                  */
1547                 sign        =(code==GE) || (code==LE) || (code==GT) || (code==LT);
1548                 flip_args   =(code==GT) || (code==GE) || (code==GTU) || (code==GEU);
1549                 equal       =(code==GE) || (code==LE) || (code==GEU) || (code==LEU);
1550
1551                 push_operand_value(&XEXP (*operand, flip_args?0:1)); /* b */
1552                 push_operand_value(&XEXP (*operand, flip_args?1:0)); /* a */
1553
1554                 if (!sign)
1555                 {
1556                         if (equal)
1557                         {
1558                           if (TARGET_COMPARE)
1559                             {
1560                                 zpu_asm("ulessthanorequal", operand);
1561                             } else
1562                               {
1563                                 zpu_asm("im _ulessthanorequal", NULL);
1564                                 zpu_call_asm();
1565                               }
1566                         } else
1567                         {
1568                           if (TARGET_COMPARE)
1569                             {
1570                                 zpu_asm("ulessthan", operand);
1571                             } else
1572                               {
1573                                 zpu_asm("im _ulessthan", NULL);
1574                                 zpu_call_asm();
1575                               }
1576                         }
1577                 } else
1578                 {
1579                         if (equal)
1580                         {
1581                           if (TARGET_COMPARE)
1582                             {
1583                                 zpu_asm("lessthanorequal", operand);
1584                             } else
1585                               {
1586                                 zpu_asm("im _lessthanorequal", NULL);
1587                                 zpu_call_asm();
1588                               }
1589                         } else
1590                         {
1591                           if (TARGET_COMPARE)
1592                             {
1593                                 zpu_asm("lessthan", operand);
1594                             } else
1595                               {
1596                                 zpu_asm("im _lessthan", NULL);
1597                                 zpu_call_asm();
1598                               }
1599                         }
1600                 }
1601
1602                 stackOffset+=4;  /* lost one */
1603         } else if (GET_CODE(*operand)==LSHIFTRT)
1604         {
1605           push_operand_value(&XEXP (*operand, 0));
1606           push_operand_value(&XEXP (*operand, 1));
1607           zpu_asm("lshiftright", operand);
1608           stackOffset+=4;  /* lost one */
1609         } else if (GET_CODE(*operand)==ASHIFTRT)
1610         {
1611                 push_operand_value(&XEXP (*operand, 0));
1612                 push_operand_value(&XEXP (*operand, 1));
1613                 zpu_asm("ashiftright", operand);
1614                 stackOffset+=4;  /* lost one */
1615         } else if (GET_CODE(*operand)==ASHIFT)
1616         {
1617                 if ((GET_CODE(XEXP (*operand, 1))==CONST_INT)&&(INTVAL(XEXP (*operand, 1))==1))
1618                 {
1619                         push_operand_value(&XEXP (*operand, 0));
1620                         zpu_addsp(0);
1621                 } else
1622                 {
1623                         push_operand_value(&XEXP (*operand, 0));
1624                         push_operand_value(&XEXP (*operand, 1));
1625                         zpu_asm("ashiftleft", operand);
1626                         stackOffset+=4;  /* lost one */
1627                 }
1628         } else if (GET_CODE(operand[0])==MULT)
1629         {
1630                 int mult=1;
1631                 /* NOTE! This is a most crucial optimisation as MULT is used in
1632                  * address modes.
1633                  */
1634                 if ((GET_CODE(XEXP(*operand, 1))==CONST_INT))
1635                 {
1636                         int c=INTVAL(XEXP(*operand, 1));
1637                         if ((c==0)||(c==1))
1638                         {
1639                                 missingOperand();
1640                         }
1641
1642                         if ((c==2)||((optimize&&!optimize_size)&&((c==4)||(c==8))))
1643                         {
1644                                 mult=0;
1645                                 push_operand_value(&XEXP (*operand, 0));
1646                                 while (c>1)
1647                                 {
1648                                         zpu_addsp(0);
1649                                         c/=2;
1650                                 }
1651                         }
1652                 }
1653
1654                 if (mult)
1655                 {
1656                         push_operand_value(&XEXP (*operand, 0));
1657                         push_operand_value(&XEXP (*operand, 1));
1658                         zpu_asm("mult", operand);
1659                         stackOffset+=4;
1660                 }
1661         } else if (GET_CODE(operand[0])==DIV)
1662         {
1663                 push_operand_value(&XEXP (*operand, 1));
1664                 push_operand_value(&XEXP (*operand, 0));
1665                 zpu_asm("div", operand);
1666                 stackOffset+=4;
1667         } else if (GET_CODE(operand[0])==MOD)
1668         {
1669                 push_operand_value(&XEXP (*operand, 1));
1670                 push_operand_value(&XEXP (*operand, 0));
1671                 zpu_asm("mod", operand);
1672                 stackOffset+=4;
1673         } else if (GET_CODE(operand[0])==ZERO_EXTEND)
1674         {
1675                 push_operand_value(&XEXP (*operand, 0));
1676                 if (GET_CODE(XEXP (*operand, 0))!=MEM)
1677                 {
1678                         switch (GET_MODE(XEXP (*operand, 0)))
1679                         {
1680                                 case VOIDmode:
1681                                 /* its a bit silly to extend a VOIDmode, i.e. a constant,
1682                                  *
1683                                  * This is a no-op.
1684                                  */
1685                                 break;
1686                                 case QImode:
1687                                 zpu_asm("im 0xff", operand);
1688                                 zpu_asm("and", operand);
1689                                 break;
1690                                 case HImode:
1691                                 zpu_asm("im 0xffff", operand);
1692                                 zpu_asm("and", operand);
1693                                 break;
1694                                 default:
1695                                 missingOperand();
1696                         }
1697                 }
1698         } else
1699         {
1700                 print_rtl(stderr, *operand);
1701                 missingOperand();
1702         }
1703 }
1704
1705
1706
1707
1708
1709 /* even registers have addresses on a ZPU that we can push onto the stack */
1710 static void push_operand_address(rtx *operand)
1711 {
1712         if (GET_CODE (*operand) == MEM)
1713         {
1714                 push_operand_value(&XEXP (*operand, 0));
1715         } else  if (GET_CODE(*operand)==SYMBOL_REF)
1716         {
1717                 zpu_immediate(operand);
1718         }  else if (GET_CODE (*operand) == REG)
1719         {
1720                 push_operand_value(operand);
1721         } else
1722         {
1723                 missingOperand();
1724         }
1725 }
1726
1727
1728 static void store_to_operand(rtx *operand)
1729 {
1730         if (GET_CODE(*operand)==PC)
1731         {
1732                 zpu_asm("poppc ; jump", operand);
1733                 stackOffset+=4;
1734         } else if (GET_CODE(*operand)==REG)
1735         {
1736                 if (REGNO(*operand)==R_SP)
1737                 {
1738                         zpu_asm("popsp", operand);
1739                         stackOffset+=4;
1740                 } else if (REGNO(*operand)==R_PC)
1741                 {
1742                         zpu_asm("poppc ; jump", operand);
1743                         stackOffset+=4;
1744                 } else if (REGNO(*operand)<R_NUM)
1745                 {
1746                         if (regStackTop<regStackSize)
1747                         {
1748                                 /* we always leave the value on the stack, if there is space
1749                                  *
1750                                  * The cleanupGenerate() handles this case.
1751                                  */
1752                                 comment("; left %0 on stack", operand);
1753                                 pushRegStack(*operand);
1754                                 stackOffset+=4;
1755                         } else
1756                         {
1757                                 comment("; regStack full", operand);
1758                                 persistReg(*operand);
1759                         }
1760                 } else
1761                 {
1762                         missingOperand();
1763                 }
1764         } else if (GET_CODE(operand[0])==MEM)
1765         {
1766                 int found;
1767                 int loadsp_offset=loadstoresp_offset(*operand, &found);
1768                 if ((GET_MODE(operand[0])!=SFmode)&&(GET_MODE(operand[0])!=SImode)&&(GET_MODE(operand[0])!=HImode)&&(GET_MODE(operand[0])!=QImode))
1769                 {
1770                         fprintf(stderr, "\nUnsupported dest\n");
1771                         print_rtl (stderr, *operand);
1772                         fprintf(stderr, "\n");
1773                         abort();
1774                 }
1775
1776
1777                 if (GET_CODE(XEXP (operand[0], 0))==PRE_DEC)
1778                 {
1779                         rtx reg=XEXP(XEXP(operand[0], 0), 0);
1780                         if (!REG_P(reg))
1781                         {
1782                                 missingOperand();
1783                         }
1784                         if (REGNO(reg)==R_SP)
1785                         {
1786                                 /* we've already pushed the result onto the stack. */
1787                                 /* we tell a small lie. We change the SP during tree expansion, but we intended to */
1788                                 stackOffset+=4;
1789                         } else
1790                         {
1791                                 missingOperand();
1792                         }
1793                 } else if (found)
1794                 {
1795                         zpu_storesp(loadsp_offset);
1796                         stackOffset+=4;
1797                 } else
1798                 {
1799                         postIncMemSize=GET_MODE_SIZE(GET_MODE(*operand));
1800
1801                         push_operand_address(operand);
1802                         switch (GET_MODE(operand[0]))
1803                         {
1804                                 case SFmode:
1805                                 case SImode:
1806                                         zpu_asm("store", operand);
1807                                         break;
1808                                 case HImode:
1809                                   if (TARGET_SHORTOP)
1810                                     {
1811                                         zpu_asm("storeh", NULL);
1812                                     } else
1813                                       {
1814                                         zpu_asm("im _storeh", NULL);
1815                                         zpu_call_asm();
1816                                       }
1817                                         break;
1818                                 case QImode:
1819                                   if (TARGET_BYTEOP)
1820                                     {
1821                                         zpu_asm("storeb", NULL);
1822                                     } else
1823                                       {
1824                                         zpu_asm("im _storeb", NULL);
1825                                         zpu_call_asm();
1826                                       }
1827
1828                                         break;
1829                                 default:
1830                                         fprintf(stderr, "FIX!!!! Missing operand\n");
1831                                         print_rtl(stderr, *operand);
1832                                         fprintf(stderr, "\n");
1833                                         break;
1834                         }
1835                         stackOffset+=8;
1836                 }
1837         } else
1838         {
1839                 fprintf(stderr, "\nUnsupported dest\n");
1840                 print_rtl (stderr, *operand);
1841                 fprintf(stderr, "\n");
1842                 abort();
1843
1844                 stackOffset+=4;
1845         }
1846
1847 }
1848
1849
1850 const char *zpu_generate_move(rtx operands[], rtx insn ATTRIBUTE_UNUSED)
1851 {
1852         initGenerate(insn);
1853
1854         comment("/* move %R1, %R0 */", operands);
1855
1856         /* first we push the source onto the stack, then we figure out the
1857          * destination
1858          */
1859         push_operand_value(operands+1);
1860
1861         store_to_operand(operands+0);
1862
1863         cleanupGenerate();
1864
1865         return "";
1866 }
1867
1868 const char *zpu_generate_set(rtx insn)
1869 {
1870         rtx set;
1871         initGenerate(insn);
1872
1873         set=single_set(insn);
1874         comment("/* %R0 */", &set);
1875
1876         /* first we push the source onto the stack, then we figure out the
1877          * destination
1878          */
1879         push_operand_value(&SET_SRC(set));
1880
1881         store_to_operand(&SET_DEST(set));
1882
1883         cleanupGenerate();
1884
1885         return "";
1886 }
1887
1888 static void zpu_neqbranch(rtx operand)
1889 {
1890
1891   zpu_asm("impcrel %0", &operand);
1892   if (TARGET_NEQBRANCH)
1893     {
1894
1895         zpu_asm("neqbranch", NULL);
1896     } else
1897       {
1898         zpu_asm("im _neqbranch", NULL);
1899         zpu_call_asm();
1900       }
1901
1902 }
1903
1904 const char *zpu_generate_if_then_else(rtx operands[], rtx insn ATTRIBUTE_UNUSED)
1905 {
1906         initGenerate(insn);
1907
1908         comment("/* if_then_else %R0 */", operands);
1909
1910         /* evaluate boolean expression. this RTL contains the two suboperands */
1911         push_operand_value(&operands[0]);
1912
1913         if (regStackTop!=0)
1914         {
1915                 fprintf(stderr, "ZPU: regStackTop %d\n", regStackTop);
1916                 missingOperand();
1917         }
1918
1919         zpu_neqbranch(operands[3]);
1920
1921         stackOffset+=4;
1922
1923         cleanupGenerate();
1924
1925         return "";
1926 }
1927
1928
1929 const char *zpu_generate_if_not_zero_then_else(rtx operands[], rtx insn ATTRIBUTE_UNUSED)
1930 {
1931         if ((GET_CODE(operands[2])!=CONST_INT)||INTVAL(operands[2])!=0)
1932         {
1933                 return zpu_generate_if_then_else(operands, insn);
1934         } else
1935         {
1936                 initGenerate(insn);
1937
1938                 /* evaluate boolean expression. this RTL contains the two suboperands */
1939                 push_operand_value(&operands[0]);
1940
1941                 zpu_neqbranch(operands[1]);
1942                 stackOffset+=4;
1943
1944                 cleanupGenerate();
1945         }
1946
1947         return "";
1948 }
1949
1950
1951 static const char *zpu_jump_core(rtx operands[], rtx insn ATTRIBUTE_UNUSED, int table)
1952 {
1953         initGenerate(insn);
1954         comment("/* jump %R0 */", operands);
1955
1956         /* put address on stack */
1957         push_operand_value(operands+0);
1958
1959         if (table)
1960         {
1961                 comment("/* tablejump */", operands);
1962         }
1963
1964         zpu_asm("poppc", operands);
1965         stackOffset+=4;
1966
1967         cleanupGenerate();
1968
1969         return "";
1970 }
1971
1972 const char *zpu_jump(rtx operands[], rtx insn ATTRIBUTE_UNUSED)
1973 {
1974         return zpu_jump_core(operands, insn, 0);
1975 }
1976
1977 const char *zpu_table_jump(rtx operands[], rtx insn ATTRIBUTE_UNUSED)
1978 {
1979         return zpu_jump_core(operands, insn, 1);
1980 }
1981
1982
1983 const char *zpu_jump_pcrel(rtx operands[], rtx insn ATTRIBUTE_UNUSED)
1984 {
1985         initGenerate(insn);
1986
1987         if (regStackTop!=0)
1988         {
1989                 fprintf(stderr, "ZPU: regStackTop %d\n", regStackTop);
1990                 missingOperand();
1991         }
1992
1993         /* put address on stack */
1994         if (TARGET_POPPCREL)
1995           {
1996         zpu_asm("impcrel %0", operands);
1997         zpu_asm("poppcrel", operands);
1998           } else
1999             {
2000         zpu_asm("im %0", operands);
2001         zpu_asm("poppc", NULL);
2002             }
2003
2004         cleanupGenerate();
2005
2006         return "";
2007 }
2008
2009
2010 const char *generate_branch(enum rtx_code code ATTRIBUTE_UNUSED, rtx loc, rtx insn)
2011 {
2012         return zpu_jump(&loc, insn);
2013 }
2014
2015 const char *zpu_push(rtx operands[], rtx insn ATTRIBUTE_UNUSED)
2016 {
2017         initGenerate(insn);
2018         comment("/* push %R0 */", operands);
2019         push_operand_value(operands+0);
2020
2021         /* we tell a small lie. We change the SP during tree expansion, but we intended to */
2022         stackOffset+=4;
2023
2024         cleanupGenerate();
2025
2026         return "";
2027 }
2028
2029
2030 static int reg_save(int regno)
2031 {
2032         int result=0;
2033     if (regs_ever_live[regno]&&!call_used_regs[regno])
2034         {
2035                 result=1;
2036         }
2037         /* FIX!!! how do we check if we've eliminated the argument pointer? */
2038         return result;
2039 }
2040
2041 static int calcSavedSize(void)
2042 {
2043         int regno;
2044         int savedSize=0;
2045   for (regno = 0; regno < R_STACK_REG; regno++)
2046     if (reg_save(regno))
2047       {
2048         savedSize+=4;
2049       }
2050         return savedSize;
2051 }
2052
2053 static int calcStackRegSize(void)
2054 {
2055         int regno;
2056         int savedSize=0;
2057   for (regno = R_STACK_REG; regno < FIRST_PSEUDO_REGISTER; regno++)
2058     if (reg_save(regno))
2059       {
2060         savedSize+=4;
2061       }
2062         return savedSize;
2063 }
2064
2065
2066 /* Define the offset between two registers, one to be eliminated, and the
2067    other its replacement, at the start of a routine.  */
2068 int zpu_initial_elimination_offset (int from, int to)
2069 {
2070         int offset;
2071         /* The difference between the argument pointer and the stack pointer is
2072          * the sum of the size of this function's frame, the callee register save
2073          * area, and the fixed stack space needed for function calls (if any).
2074          */
2075         if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2076         {
2077         offset=current_function_outgoing_args_size + calcStackRegSize() + get_frame_size () + calcSavedSize() + 4 ;
2078         } else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
2079     {
2080         offset=calcSavedSize() + 4;
2081     } else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
2082         {
2083                 offset=current_function_outgoing_args_size + calcStackRegSize() + get_frame_size ();
2084         } else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
2085         {
2086                 offset=0;
2087         } else
2088         {
2089                 abort ();
2090         }
2091     return offset;
2092 }
2093
2094 static int allocFrameSize(void)
2095 {
2096         return current_function_outgoing_args_size+calcStackRegSize()+get_frame_size();
2097 }
2098
2099 void zpu_expand_prologue (void)
2100 {
2101         int i;
2102   int regno;
2103   rtx insn;
2104   rtx mem_push_rtx;
2105         HOST_WIDE_INT frameSize;
2106         int mapper=0;
2107
2108         prevImmediate=0;
2109         for (i=R_STACK_REG; i<R_NUM; i++)
2110         {
2111         regMapper[i-R_STACK_REG]=-1;
2112         }
2113
2114         for (i=0; i<R_NUM; i++)
2115         {
2116                 if ((i>=R_STACK_REG)&&reg_save(i))
2117             {
2118                 regMapper[i-R_STACK_REG]=mapper++;
2119             }
2120                 reg[i]=gen_rtx_REG(SImode, i);
2121         }
2122         regStackTop=0;
2123
2124
2125   mem_push_rtx = gen_rtx_MEM (SImode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
2126
2127   /* Push each of the registers to save.  */
2128   for (regno = 0; regno < R_STACK_REG; regno++)
2129     if (reg_save(regno))
2130       {
2131         insn = emit_move_insn (mem_push_rtx, gen_rtx_REG (SImode, regno));
2132         RTX_FRAME_RELATED_P (insn) = 1;
2133       }
2134
2135   /* Set up the frame pointer, if required.  */
2136   if (frame_pointer_needed)
2137     {
2138       insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
2139           RTX_FRAME_RELATED_P (insn) = 1;
2140     }
2141         /* DANGER!!!! I believe that we can trust the GCC compiler to
2142          * always eliminate the argument pointer register, if not we're
2143          * in trouble, because we do not emit any code here */
2144
2145         frameSize=allocFrameSize();
2146         if (frameSize>0)
2147         {
2148           insn=emit_move_insn (stack_pointer_rtx,
2149           gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (-frameSize)));
2150           RTX_FRAME_RELATED_P (insn) = 1;
2151         }
2152
2153 }
2154
2155 void zpu_expand_epilogue (void)
2156 {
2157   rtx mem_pop_rtx, insn;
2158   int regno;
2159         HOST_WIDE_INT frameSize;
2160         rtx mem_push_rtx;
2161
2162   mem_pop_rtx = gen_rtx_MEM (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
2163
2164         frameSize=allocFrameSize();
2165         if (frameSize>0)
2166           {
2167           insn = emit_move_insn (stack_pointer_rtx,
2168           gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (frameSize)));
2169           RTX_FRAME_RELATED_P (insn) = 1;
2170           }
2171
2172   /* Restore any call-saved registers.  */
2173   for (regno = R_STACK_REG - 1; regno >= 0; regno--)
2174     if (reg_save(regno))
2175       {
2176         insn = emit_move_insn (gen_rtx_REG (SImode, regno), mem_pop_rtx);
2177           }
2178
2179         /* FIX! a single poppc should suffice for no argument fn's */
2180         mem_push_rtx = gen_rtx_MEM (SImode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
2181     insn = emit_jump_insn (gen_zpu_return());
2182 }
2183
2184 rtx zpu_return_addr_rtx(void)
2185 {
2186   return gen_rtx_MEM (Pmode, plus_constant (virtual_incoming_args_rtx, -4));
2187 }
2188
2189
2190 const char *zpu_call(rtx operands[], rtx insn ATTRIBUTE_UNUSED)
2191 {
2192         initGenerate(insn);
2193
2194         zpu_gen_call(operands);
2195
2196         cleanupGenerate();
2197         return "";
2198 }
2199
2200
2201 const char *zpu_call_value(rtx operands[], rtx insn ATTRIBUTE_UNUSED)
2202 {
2203         initGenerate(insn);
2204
2205         zpu_gen_call(operands+1);
2206
2207         if ((GET_CODE(operands[0])!=REG)&&(REGNO(operands[0])!=R_R0))
2208         {
2209                 rtx reg=gen_rtx_REG(SImode, 0);
2210                 pushreg(reg);
2211                 stackOffset-=4;
2212
2213                 store_to_operand(operands+0);
2214         }
2215
2216         cleanupGenerate();
2217         return "";
2218 }
2219
2220 /* change all QImode and HImode to SImode load's*/
2221
2222 void zpu_expand_set(enum machine_mode mode, rtx operands[])
2223 {
2224         emit_insn(gen_rtx_SET(mode, operands[0], operands[1]));
2225 }
2226
2227
2228
2229 static void
2230 zpu_file_start (void)
2231 {
2232         default_file_start ();
2233 }
2234
2235 /* Value is the number of bytes of arguments automatically
2236    popped when returning from a subroutine call.
2237    FUNDECL is the declaration node of the function (as a tree),
2238    FUNTYPE is the data type of the function (as a tree),
2239    or for a library call it is an identifier node for the subroutine name.
2240    SIZE is the number of bytes of arguments passed on the stack.
2241
2242    On the ZPU, the RET insn may be used to pop them if the number
2243      of args is fixed, but if the number is variable then the caller
2244      must pop them all.
2245    Use of RET is should be a selectable option, since it is incompatible with
2246    standard Unix calling sequences.  If the option is not selected,
2247    the caller must always pop the args.
2248
2249     */
2250
2251 int
2252 zpu_return_pops_args (tree fundecl ATTRIBUTE_UNUSED, tree funtype, int size)
2253 {
2254   if (TREE_CODE (funtype) == IDENTIFIER_NODE)
2255     return size;
2256
2257   if (TYPE_ARG_TYPES (funtype) == NULL_TREE
2258       || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype))) == void_type_node))
2259         return size;
2260
2261   return 0;
2262 }
2263
2264
2265
2266
2267
2268 int
2269 move_double_src_operand (rtx op, enum machine_mode mode)
2270 {
2271   switch (GET_CODE (op))
2272     {
2273     case CONST_INT :
2274     case CONST_DOUBLE :
2275       return 1;
2276
2277         case SUBREG:
2278         /* FIX! not entirely sure why this isn't
2279          * handled by register_operand
2280          */
2281         return 1;
2282
2283     case REG :
2284       return register_operand (op, mode);
2285
2286     #if 0
2287       /* (subreg (mem ...) ...) can occur here if the inner part was once a
2288          pseudo-reg and is now a stack slot.  */
2289       if (GET_CODE (SUBREG_REG (op)) == MEM)
2290         return move_double_src_operand (SUBREG_REG (op), mode);
2291       else
2292         return register_operand (op, mode);
2293         #endif
2294     case MEM :
2295       /* Disallow auto inc/dec for now.  */
2296       if ((GET_CODE (XEXP (op, 0)) == POST_INC)&&
2297       (!REG_P(XEXP (XEXP (op, 0), 0))||
2298       REGNO(XEXP (XEXP (op, 0), 0)))!=R_SP)
2299                 return 0;
2300       return memory_operand (op, mode);
2301     default :
2302       return 0;
2303     }
2304 }
2305
2306 /* Return true if OP is an acceptable argument for a move destination.  */
2307
2308 int
2309 move_double_dest_operand (rtx op, enum machine_mode mode)
2310 {
2311   switch (GET_CODE (op))
2312     {
2313     case REG :
2314     case SUBREG :
2315       return register_operand (op, mode);
2316       #if 0
2317     case SUBREG :
2318       /* (subreg (mem ...) ...) can occur here if the inner part was once a
2319          pseudo-reg and is now a stack slot.  */
2320       if (GET_CODE (SUBREG_REG (op)) == MEM)
2321         return address_operand (XEXP (SUBREG_REG (op), 0), mode);
2322       else
2323         return register_operand (op, mode);
2324         #endif
2325     case MEM :
2326       /* Disallow auto inc for now.  */
2327       if (GET_CODE (XEXP (op, 0)) == POST_INC)
2328         return 0;
2329 #if 0
2330         /* FIX!!!! a) why isn't this necessary? b) why does it break compilation? */
2331       if ((GET_CODE (XEXP (op, 0)) == PRE_DEC)&&
2332       ((!REG_P(XEXP (XEXP (op, 0), 0))||
2333       REGNO(XEXP (XEXP (op, 0), 0)))!=R_SP))
2334                 return 0;
2335 #endif
2336       return memory_operand (op, mode);
2337     default :
2338       return 0;
2339     }
2340 }
2341
2342
2343 /* Split a 2 word move (DI or DF) into component parts.  */
2344
2345 rtx
2346 gen_split_move_double (rtx operands[])
2347 {
2348   enum machine_mode mode = GET_MODE (operands[0]);
2349   rtx dest = operands[0];
2350   rtx src  = operands[1];
2351   rtx val;
2352
2353   /* We might have (SUBREG (MEM)) here, so just get rid of the
2354      subregs to make this code simpler.  It is safe to call
2355      alter_subreg any time after reload.  */
2356   if (GET_CODE (dest) == SUBREG)
2357     alter_subreg (&dest);
2358   if (GET_CODE (src) == SUBREG)
2359     alter_subreg (&src);
2360
2361   start_sequence ();
2362   if (GET_CODE (dest) == REG)
2363     {
2364       int dregno = REGNO (dest);
2365
2366       /* Reg = reg.  */
2367       if (GET_CODE (src) == REG)
2368         {
2369           int sregno = REGNO (src);
2370
2371           int reverse = (dregno == sregno + 1);
2372
2373           /* We normally copy the low-numbered register first.  However, if
2374              the first register operand 0 is the same as the second register of
2375              operand 1, we must copy in the opposite order.  */
2376           emit_insn (gen_rtx_SET (VOIDmode,
2377                                   operand_subword (dest, reverse, TRUE, mode),
2378                                   operand_subword (src,  reverse, TRUE, mode)));
2379
2380           emit_insn (gen_rtx_SET (VOIDmode,
2381                                   operand_subword (dest, !reverse, TRUE, mode),
2382                                   operand_subword (src,  !reverse, TRUE, mode)));
2383         }
2384
2385       /* Reg = constant.  */
2386       else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
2387         {
2388           rtx words[2];
2389           split_double (src, &words[0], &words[1]);
2390           emit_insn (gen_rtx_SET (VOIDmode,
2391                                   operand_subword (dest, 0, TRUE, mode),
2392                                   words[0]));
2393
2394           emit_insn (gen_rtx_SET (VOIDmode,
2395                                   operand_subword (dest, 1, TRUE, mode),
2396                                   words[1]));
2397         }
2398
2399       /* Reg = mem.  */
2400       else if (GET_CODE (src) == MEM)
2401         {
2402           /* If the high-address word is used in the address, we must load it
2403              last.  Otherwise, load it first.  */
2404           int reverse
2405             = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
2406
2407           /* We used to optimize loads from single registers as
2408
2409                 ld r1,r3+; ld r2,r3
2410
2411              if r3 were not used subsequently.  However, the REG_NOTES aren't
2412              propagated correctly by the reload phase, and it can cause bad
2413              code to be generated.  We could still try:
2414
2415                 ld r1,r3+; ld r2,r3; addi r3,-4
2416
2417              which saves 2 bytes and doesn't force longword alignment.  */
2418           emit_insn (gen_rtx_SET (VOIDmode,
2419                                   operand_subword (dest, reverse, TRUE, mode),
2420                                   adjust_address (src, SImode,
2421                                                   reverse * UNITS_PER_WORD)));
2422
2423           emit_insn (gen_rtx_SET (VOIDmode,
2424                                   operand_subword (dest, !reverse, TRUE, mode),
2425                                   adjust_address (src, SImode,
2426                                                   !reverse * UNITS_PER_WORD)));
2427         }
2428       else
2429         abort ();
2430     }
2431
2432   /* Mem = reg.  */
2433   /* We used to optimize loads from single registers as
2434
2435         st r1,r3; st r2,+r3
2436
2437      if r3 were not used subsequently.  However, the REG_NOTES aren't
2438      propagated correctly by the reload phase, and it can cause bad
2439      code to be generated.  We could still try:
2440
2441         st r1,r3; st r2,+r3; addi r3,-4
2442
2443      which saves 2 bytes and doesn't force longword alignment.  */
2444   else if (GET_CODE (dest) == MEM && (GET_CODE(XEXP(dest, 0))==PRE_DEC) && GET_CODE (src) == REG)
2445     {
2446       emit_insn (gen_rtx_SET (VOIDmode,
2447                               gen_rtx_MEM(SImode, XEXP(dest, 0)),
2448                               operand_subword (src, 1, TRUE, mode)));
2449
2450       emit_insn (gen_rtx_SET (VOIDmode,
2451                               gen_rtx_MEM(SImode, XEXP(dest, 0)),
2452                               operand_subword (src, 0, TRUE, mode)));
2453
2454     } else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
2455     {
2456       emit_insn (gen_rtx_SET (VOIDmode,
2457                               adjust_address (dest, SImode, 0),
2458                               operand_subword (src, 0, TRUE, mode)));
2459
2460       emit_insn (gen_rtx_SET (VOIDmode,
2461                               adjust_address (dest, SImode, UNITS_PER_WORD),
2462                               operand_subword (src, 1, TRUE, mode)));
2463     }
2464
2465   else
2466   {
2467         debug_rtx(operands[0]);
2468         debug_rtx(operands[1]);
2469         abort();
2470   }
2471
2472   val = get_insns ();
2473   end_sequence ();
2474   return val;
2475 }
2476
2477
2478 const char *zpu_changestackpointer(rtx operands[], rtx insn)
2479 {
2480   rtx t[2];
2481   rtx set;
2482
2483   set=single_set(insn);
2484   if (set==NULL_RTX)
2485     {
2486       abort();
2487     }
2488
2489   t[0]=stack_pointer_rtx;
2490   t[1]=SET_SRC(set);
2491
2492   return zpu_generate_move(t, insn);
2493 }
2494
2495
2496
2497
2498
2499
2500 #undef TARGET_ASM_FILE_START
2501 #define TARGET_ASM_FILE_START zpu_file_start
2502 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
2503 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
2504
2505
2506 struct gcc_target targetm = TARGET_INITIALIZER;
2507
2508
2509 #include "gt-zpu.h"