README.html

   1 <h1>YARI -- Yet Another RISC Implementation</h1>
   2
   3 <h2>INTRODUCTION</h2>
   4
   5 <p>YARI is an high performance softcore RISC implementation, binary
   6 compatible with a subset of MIPS R3000.</p>
   7
   8 YARI is still under active development, but the implementation
   9 currently comprises:
  10
  11 <ul>
  12 <li>
  13 A reference simulator which can check the RTL implementation through
  14 co-simulation.
  15
  16 </li><li>
  17
  18 A few regression and tests programs
  19 </li><li>
  20 An RTL (Verilog) implementation
  21
  22   Core features:
  23     <ul><li>
  24     an eight stage pipeline.
  25     </li><li>
  26     a 4-way associative instruction cache (default 8 KiB)
  27     </li><li>
  28     a 4-way associative write-through data cache (default 16 KiB)
  29     </li><li>
  30     a store buffer
  31     </li><li>
  32     all of the integer user-level instructions supported
  33     </li></ul>
  34
  35   Peripherals (depending on the target)
  36     <ul><li>SRAM interface
  37     </li><li>Serial in/out
  38     </li></ul>
  39
  40   Simulation
  41   <ul><li>
  42   Enough support to fully simulate the RTL with Icarus Verilog.
  43   </li><li>
  44   Co-simulation against the reference simulator supported
  45   </li></ul>
  46
  47   Synthesis
  48   <ul><li>
  49   Targeted at the Altera Nios Dev Kit (Cyclone ed.), Cycore, and the LPRP, but more in future.
  50   </li><li>
  51   Runs at around 50+ MHz (soon 70+ MHz) in a EP1C20.
  52   </li></ul>
  53
  54   </li><li>A boot loader pre-loaded into the I$ - will load programs over the
  55   serial port.
  56
  57   </li><li>Assorted tools to turn the elf binaries into ROM and RAM images.
  58 </li></ul>
  59
  60
  61
  62
  63 <h2>GETTING STARTED</h2>
  64
  65 There are a few prerequisites for full YARI enjoyment:
  66
  67 <ul><li>For building any test programs: Cross compilation tool much be built
  68   (mips-elf-gcc, etc).  The script xtools/BUILD is what I used to
  69   build them
  70 </li><li>For simulation: Icarus Verilog.  Great stuff.  Get the most recent
  71   version from http://www.icarus.com/eda/verilog
  72
  73 For synthesis: currently I've only tested with Quartus 7.2sp1.  Get it
  74 for free from http://www.altera.com (alas, only works with Windows,
  75 whereas everything else here expects Unix, Linux, or MacOSX).
  76 </li></ul>
  77
  78 With the Icarus Verilog installed you should be able to simply run
  79 <pre>
  80   make rtlsim
  81 </pre>
  82
  83 and see the trace of instructions as the Verilog implementation makes
  84 it through a small self-checking regression test. <p>
  85
  86 For more interesting workloads, try </p>
  87
  88 <pre>
  89   make -C testcases VERB= PROG=buzzard isasim
  90 </pre>
  91
  92 or try co-simulation
  93
  94 <pre>
  95   make -C testcases VERB= PROG=fib cosim
  96 </pre>
  97
  98
  99
 100 <br></br>
 101 <br></br>
 102 Tommy