2 * Coprocessor 0 register names
6 #define CP0_ENTRYLO0 $2
7 #define CP0_ENTRYLO1 $3
10 #define CP0_PAGEMASK $5
13 #define CP0_BADVADDR $8
15 #define CP0_ENTRYHI $10
16 #define CP0_COMPARE $11
17 #define CP0_STATUS $12
21 #define CP0_CONFIG $16
22 #define CP0_LLADDR $17
23 #define CP0_WATCHLO $18
24 #define CP0_WATCHHI $19
25 #define CP0_XCONTEXT $20
26 #define CP0_FRAMEMASK $21
27 #define CP0_DIAGNOSTIC $22
30 #define CP0_PERFORMANCE $25
32 #define CP0_CACHEERR $27
35 #define CP0_ERROREPC $30
36 #define CP0_DESAVE $31
41 * Test the eret instructions
44 #define SRAM 0x40000000
46 #define FAILURE la $2, .; mtlo $2; .word 0x48000000; 99: b 99b; nop
47 #define SUCCESS li $2, 0x87654321; mtlo $2; .word 0x48000000
48 #define EXPECT(r, v) li $30, v; beq $30,r,13f;nop;FAILURE;13:
49 #define EXPECT_ADDR(r, a) la $30, a; beq $30,r,13f;nop;FAILURE;13:
56 /* Test EPC return. Set ERL=1 and ErrorPC = good1. */
59 xori t0,0x1b /* Lower 5 bits are KSU:2, ERL, EXL, and IE. */
75 /* Test ErrorPC return. Set ERL=0 and EPC = good2. */