1 YARI -- Yet Another RISC Implementation
3 Last update: 2007-12-12
7 YARI is an high performance soft core RISC implementation, binary
8 compatible with a subset of MIPS R3000.
10 This README will be out of date at the time you read this, but the
11 implementation currently comprises:
13 - A reference simulator which closely matches the RTL implementation
14 (in fact they co-simulate).
16 - A few regression and tests programs
17 - An RTL (Verilog) implementation
20 + an eight stage pipeline.
21 + a 4-way associative write-through instruction cache (default 8 KiB)
22 + a 4-way associative write-through data cache (default 16 KiB)
24 + all of the integer user-level instructions supported (current
27 Peripherals (depending on the target)
29 + 640x480x1 video interface
31 + 8 LED out put for debugging.
34 + Enough support to fully simulate the RTL with Icarus Verilog.
35 + Co-simulation against the reference simulator supported
38 + Targeted at the Altera Nios Dev Kit, Cyclone edition, and
41 + Runs (last it ran) happily at 50+ MHz.
43 - A boot loader pre-loaded into the I$ - will load programs over the
46 - Assorted tools to turn the elf binaries into ROM and RAM images.
52 There are a few prerequisites for full YARI enjoyment:
54 - For building any test programs: Cross compilation tool much be built
55 (mips-elf-gcc, etc). The script xtools/BUILD is what I used to
58 - For simulation: Icarus Verilog. Great stuff. Get the most recent
59 version from http://www.icarus.com/eda/verilog
61 - For synthesis: currently I've only tested with Quartus 7.2sp1. Get it
62 for free from http://www.altera.com (alas, only works with Windows,
63 whereas everything else here expects Linux).
65 With the Icarus Verilog installed you should be able to simply run
69 and see the trace of instructions as the Verilog implementation makes
70 it through a small self-checking regression test.
72 For more interesting workloads, try
74 make -C testcases VERB= PROG=buzzard isasim
78 make -C testcases VERB= PROG=fib cosim