rtl/onnama/dmem.v

   1 `timescale 1ns/10ps
   2 `include "pipeconnect.h"
   3
   4 module dmem(input  wire        clk,
   5             input  wire        rst,
   6
   7             input  wire `REQ   dmem_req,
   8             output wire `RES   dmem_res,
   9
  10             output wire `REQ   dc_ctrl_req,
  11             input  wire `RES   dc_ctrl_res,
  12
  13             output wire `REQ   bus_ctrl_d_req,
  14             input  wire `RES   bus_ctrl_d_res);
  15
  16    parameter       debug = 0;
  17
  18    demux2 demux2(clk,
  19                  (dmem_req`A & 'hFFFF_E000) == 'h1000_0000, // XXX Get rid of this!
  20                  dmem_req,       dmem_res,
  21                  dc_ctrl_req,    dc_ctrl_res,
  22                  bus_ctrl_d_req, bus_ctrl_d_res);
  23
  24 `ifdef SIMULATE_MAIN
  25    pipechecker check1("dmem",            clk,       dmem_req,       dmem_res);
  26    pipechecker check2("dmem dc_ctrl_d",  clk,    dc_ctrl_req,    dc_ctrl_res);
  27    pipechecker check3("dmem bus_ctrl_d", clk, bus_ctrl_d_req, bus_ctrl_d_res);
  28 `endif
  29
  30    reg             r_ = 0;
  31    always @(posedge clk) if (debug) begin
  32       r_ <= dmem_req`R;
  33       if (dmem_res`HOLD)
  34         $display("%5d DMEM: Stall in data memory: %d %d %d", $time,
  35                  dmem_res`HOLD, dc_ctrl_res`HOLD, bus_ctrl_d_res`HOLD);
  36       else begin
  37          if (dmem_req`R)
  38            $display("%5d DMEM: load [%x]", $time, dmem_req`A);
  39
  40          if (r_)
  41            $display("%5d DMEM: load -> %x", $time, dmem_res`RD);
  42
  43          if (dmem_req`W)
  44            $display("%5d DMEM: store %x->[%x] (bytena %x)",
  45                     $time, dmem_req`WD, dmem_req`A, dmem_req`WBE);
  46       end
  47    end
  48 endmodule // dmem