rtl/target/ML401/top.v

   1 // -----------------------------------------------------------------------
   2 //
   3 //   Copyright 2004,2007-2009 Tommy Thorn - All Rights Reserved
   4 //
   5 //   This program is free software; you can redistribute it and/or modify
   6 //   it under the terms of the GNU General Public License as published by
   7 //   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
   8 //   Bostom MA 02111-1307, USA; either version 2 of the License, or
   9 //   (at your option) any later version; incorporated herein by reference.
  10 //
  11 // -----------------------------------------------------------------------
  12
  13 `timescale 1ns/10ps
  14 `include "../../soclib/pipeconnect.h"
  15 module main
  16    (input         iSYS_CLK_100
  17    ,input         iSYS_RST
  18
  19    ,input         iUART_RXD
  20    ,output        oUART_TXD
  21
  22    );
  23
  24    parameter FREQ = 100_000_000; // match clock frequency
  25    parameter BPS  =       9_600; // Serial speed
  26
  27    // Copied from yari.v
  28    parameter   ID_DC              = 2'd1;
  29    parameter   ID_IC              = 2'd2;
  30    parameter   ID_FB              = 2'd3;
  31
  32    wire        clock; // The master clock
  33
  34    /*
  35    wire        video_clock;
  36    wire        clock_locked;
  37
  38    // Actually, just a 1-1 clock filter for c0
  39    // and a 65 MHz for video_clock
  40    pll  pll_inst(.inclk0(iCLK_50)
  41                 ,.c0(clock)
  42                 ,.c2(video_clock)
  43                 ,.locked(clock_locked));
  44    reg           iSW17_, iSW17, manual_reset;
  45    */
  46    assign      clock = iSYS_CLK_100;
  47    wire        reset = iSYS_RST;
  48
  49    wire [ 7:0]   rs232out_transmit_data;
  50    wire          rs232out_write_enable;
  51    wire          rs232out_busy;
  52
  53    wire [ 7:0]   rs232in_received_data;
  54    wire          rs232in_received_data_valid;
  55
  56    wire          mem_waitrequest;
  57    wire    [1:0] mem_id;
  58    wire   [29:0] mem_address;
  59    wire          mem_read;
  60    wire          mem_write;
  61    wire   [31:0] mem_writedata;
  62    wire    [3:0] mem_writedatamask;
  63    wire   [31:0] mem_readdata;
  64    wire    [1:0] mem_readdataid;
  65
  66    wire          yari_mem_waitrequest;
  67    wire    [1:0] yari_mem_id;
  68    wire   [29:0] yari_mem_address;
  69    wire          yari_mem_read;
  70    wire          yari_mem_write;
  71    wire   [31:0] yari_mem_writedata;
  72    wire    [3:0] yari_mem_writedatamask;
  73
  74    wire `REQ     rs232_req;
  75    wire `RES     rs232_res;
  76
  77    yari yari_inst(
  78          .clock(clock)
  79         ,.rst(reset)
  80
  81         // Inputs
  82         ,.mem_waitrequest  (yari_mem_waitrequest)
  83         ,.mem_readdata     (mem_readdata)
  84         ,.mem_readdataid   (mem_readdataid)
  85
  86         // Outputs
  87         ,.mem_id           (yari_mem_id)
  88         ,.mem_address      (yari_mem_address)
  89         ,.mem_read         (yari_mem_read)
  90         ,.mem_write        (yari_mem_write)
  91         ,.mem_writedata    (yari_mem_writedata)
  92         ,.mem_writedatamask(yari_mem_writedatamask)
  93
  94         ,.peripherals_req(rs232_req)
  95         ,.peripherals_res(rs232_res)
  96         );
  97
  98    rs232out rs232out_inst
  99       (.clock        (clock),
 100        .serial_out   (oUART_TXD),
 101        .transmit_data(rs232out_transmit_data),
 102        .we           (rs232out_write_enable),
 103        .busy         (rs232out_busy));
 104
 105    defparam rs232out_inst.frequency = FREQ,
 106             rs232out_inst.bps       = BPS;
 107
 108
 109    rs232in rs232in_inst
 110       (.clock        (clock),
 111        .serial_in    (iUART_RXD),
 112        .received_data(rs232in_received_data),
 113        .attention    (rs232in_received_data_valid));
 114
 115    defparam rs232in_inst.frequency = FREQ,
 116             rs232in_inst.bps       = BPS;
 117
 118    wire [31:0] vsynccnt;
 119
 120    rs232 rs232_inst(.clk(clock),
 121                .rst(reset),
 122
 123                .iKEY(0),
 124                .vsynccnt(vsynccnt),
 125
 126                .rs232_req(rs232_req),
 127                .rs232_res(rs232_res),
 128
 129                .rs232in_attention(rs232in_received_data_valid),
 130                .rs232in_data     (rs232in_received_data),
 131
 132                .rs232out_busy(rs232out_busy),
 133                .rs232out_w   (rs232out_write_enable),
 134                .rs232out_d   (rs232out_transmit_data));
 135
 136
 137    assign      mem_id             = yari_mem_id;
 138    assign      mem_address        = yari_mem_address;
 139    assign      mem_read           = yari_mem_read;
 140    assign      mem_write          = yari_mem_write;
 141    assign      mem_writedata      = yari_mem_writedata;
 142    assign      mem_writedatamask  = yari_mem_writedatamask;
 143    assign      yari_mem_waitrequest = mem_waitrequest;
 144 endmodule