rtl/target/ML401/rs232.v

   1 `timescale 1ns/10ps
   2 module rs232(input  wire        clk,
   3              input  wire        rst,
   4
   5              input  wire [3:0]  iKEY,
   6              input  wire [31:0] vsynccnt,
   7
   8              // Master connections
   9              input  wire `REQ   rs232_req,
  10              output wire `RES   rs232_res,
  11
  12              input  wire        rs232in_attention,
  13              input  wire [7:0]  rs232in_data,
  14
  15              input  wire        rs232out_busy,
  16              output wire        rs232out_w,
  17              output wire [7:0]  rs232out_d);
  18
  19    parameter debug = 1;
  20
  21    reg [31:0] tsc = 0;  // A free running counter....
  22    reg [ 7:0] rs232in_cnt = 0;
  23
  24    wire [31:0] addr = rs232_req`A;
  25    reg [31:0] rd_data = 0;
  26    assign     rs232_res`RD = rd_data;
  27    assign     rs232_res`HOLD = 0;
  28
  29    reg [3:0]  iKEY_;
  30
  31
  32    always @(posedge clk)
  33      if (rst) begin
  34         rd_data     <= 0;
  35         tsc         <= 0;
  36         rs232in_cnt <= 0;
  37      end else begin
  38         iKEY_ <= iKEY;
  39
  40         rd_data <= 0;
  41         tsc <= tsc + 1;
  42         if (rs232in_attention)
  43           rs232in_cnt <= rs232in_cnt + 1'h1;
  44
  45         if (rs232_req`R) begin
  46            case (addr[4:2])
  47            0: rd_data <= {31'h0,rs232out_busy};//  0
  48            1: rd_data <= {24'h0,rs232in_data}; //  4
  49            2: rd_data <= {24'h0,rs232in_cnt};  //  8
  50            3: rd_data <= tsc;                  // 12
  51            4: rd_data <= ~iKEY_;
  52            5: rd_data <= vsynccnt;
  53            endcase
  54         end
  55      end
  56
  57    assign rs232out_d    = rs232_req`WD;
  58    assign rs232out_w    = rs232_req`W & addr[3:0] == 0;
  59 endmodule