1 `timescale 1 ns / 10 ps
4 address_a
, byteena_a
, wrdata_a
, wren_a
, rddata_a
,
5 address_b
, byteena_b
, wrdata_b
, wren_b
, rddata_b
);
7 parameter DATA_WIDTH
= 32;
8 parameter ADDR_WIDTH
= 7;
9 parameter INIT_FILE
= "dummy"; // This is ignored right now
13 input [ADDR_WIDTH
-1:0] address_a
;
14 input [DATA_WIDTH
/8-1:0] byteena_a
;
15 input [DATA_WIDTH
-1:0] wrdata_a
;
17 output [DATA_WIDTH
-1:0] rddata_a
;
19 input [ADDR_WIDTH
-1:0] address_b
;
20 input [DATA_WIDTH
-1:0] wrdata_b
;
21 input [DATA_WIDTH
/8-1:0] byteena_b
;
23 output [DATA_WIDTH
-1:0] rddata_b
;
25 dpram_simple
s0(clock
,
26 address_a
, wrdata_a
[ 7: 0], byteena_a
[0] & wren_a
, rddata_a
[ 7: 0],
27 address_b
, wrdata_b
[ 7: 0], byteena_b
[0] & wren_b
, rddata_b
[ 7: 0]);
28 defparam s0.DATA_WIDTH
= DATA_WIDTH
/ 4,
29 s0.DATA_WIDTH
= DATA_WIDTH
;
31 dpram_simple
s1(clock
,
32 address_a
, wrdata_a
[15: 8], byteena_a
[1] & wren_a
, rddata_a
[15: 8],
33 address_b
, wrdata_b
[15: 8], byteena_b
[1] & wren_b
, rddata_b
[15: 8]);
34 defparam s1.DATA_WIDTH
= DATA_WIDTH
/ 4,
35 s1.DATA_WIDTH
= DATA_WIDTH
;
37 dpram_simple
s2(clock
,
38 address_a
, wrdata_a
[23:16], byteena_a
[2] & wren_a
, rddata_a
[23:16],
39 address_b
, wrdata_b
[23:16], byteena_b
[2] & wren_b
, rddata_b
[23:16]);
40 defparam s2.DATA_WIDTH
= DATA_WIDTH
/ 4,
41 s2.DATA_WIDTH
= DATA_WIDTH
;
43 dpram_simple
s3(clock
,
44 address_a
, wrdata_a
[31:24], byteena_a
[3] & wren_a
, rddata_a
[31:24],
45 address_b
, wrdata_b
[31:24], byteena_b
[3] & wren_b
, rddata_b
[31:24]);
46 defparam s3.DATA_WIDTH
= DATA_WIDTH
/ 4,
47 s3.DATA_WIDTH
= DATA_WIDTH
;