1 YARI -- Yet Another RISC Implementation
3 Last update: 2008-11-24
7 YARI is an high performance soft core RISC implementation, binary
8 compatible with a subset of MIPS R3000.
10 This README will be out of date at the time you read this, but the
11 implementation currently comprises:
13 - A reference simulator which closely matches the RTL implementation
14 (in fact they co-simulate).
16 - A few regression and tests programs
17 - An RTL (Verilog) implementation
20 + an eight stage pipeline.
21 + a 4-way associative write-through instruction cache (default 8 KiB)
22 + a 4-way associative write-through data cache (default 16 KiB)
24 + all of the integer user-level instructions supported
26 Peripherals (depending on the target)
27 + Async SRAM interface (32-bit and 16-bit)
28 + Sync burst SRAM interface (32-bit)
30 + 1024x768x8 video interface
33 + Enough support to fully simulate the RTL with Icarus Verilog.
34 + Co-simulation against the reference simulator supported
37 + Multiple target platforms supported (currently only Altera based)
40 - A boot loader pre-loaded into the I$ - will load programs over the
43 - Assorted tools to turn the elf binaries into ROM and RAM images.
49 There are a few prerequisites for full YARI enjoyment:
51 - For building any test programs: Cross compilation tool much be built
52 (mips-elf-gcc, etc). The script xtools/BUILD is what I used to
55 - For simulation: Icarus Verilog. Great stuff. Get the most recent
56 version from http://www.icarus.com/eda/verilog
58 - For synthesis: currently I've only tested with Quartus 7.2sp1, 8.0,
59 and 8.0sp1. Get it for free from http://www.altera.com (alas, only
60 works with Windows, whereas everything else here expects Linux).
62 With the Icarus Verilog installed you should be able to simply run
66 and see the trace of instructions as the Verilog implementation makes
67 it through a small self-checking regression test.
69 For more interesting workloads, try
71 make -C testcases VERB= PROG=buzzard isasim
75 make -C testcases VERB= PROG=fib cosim