3 MIPS32R2 opcode map (incomplete)
5 Root map: instr [31:26] (6 bit)
8 00 SPECIAL REGIMM j jal beq bne blez bgtz
9 08 addi addiu slti sltiu andi ori xori lui
10 10 cp0 cp1 cp2 cp1x beql bnel blezl bgtzl
11 18 - - - - - - - rdhwr
12 20 lb lh lwl lw lbu lhu lwr -
13 28 sb sh swl sw - - swr cache
14 30 ll lwc1 lwc2 pref - ldc1 ldc2 -
15 38 sc swc1 lwc2 - - sdc1 sdc2 -
17 Reg map: instr[5:0] (6 bit)
20 00 sll movci srl sra sllv - srlv srav
21 08 jr jalr movz movn syscall break - sync
22 10 mfhi mthi mflo mtlo - - - -
23 18 mult multu div divu - - - -
24 20 add addu sub subu and or xor nor
25 28 - - slt sltu - - - -
26 30 tge tgeu tlt tltu teq - tne -
29 Regimm map: instr[20:16] (5 bit)
32 00 bltz bgez - - - - - -
33 08 tgei tgeiu tlti tltiu teqi - tnei -
34 10 bltzal bgezal bltzall bgezall - - - -
35 18 - - - - - - - synci
42 typedef enum root_map
{
43 SPECIAL
=0x00, REGIMM
, J
, JAL
, BEQ
, BNE
, BLEZ
, BGTZ
,
44 ADDI
=0x08, ADDIU
, SLTI
, SLTIU
, ANDI
, ORI
, XORI
, LUI
,
45 CP0
=0x10, CP1
, CP2
, CP1X
, BEQL
, BNEL
, BLEZL
, BGTZL
,
47 LB
=0x20, LH
, LWL
, LW
, LBU
, LHU
, LWR
,
48 SB
=0x28, SH
, SWL
, SW
, SWR
=0x2e, CACHE
,
49 LL
=0x30, LWC1
, LWC2
, PREF
, LDC1
=0x35, LDC2
,
50 SC
=0x38, SWC1
, SWC2
, SDC1
=0x3d, SDC2
,
53 typedef enum reg_map
{
54 SLL
=0x00, SRL
= 2, SRA
, SLLV
, SRLV
= 6, SRAV
,
55 JR
=0x08, JALR
, SYSCALL
= 0x0c, BREAK
= 0x0d,
56 MFHI
=0x10, MTHI
, MFLO
, MTLO
,
57 MULT
=0x18, MULTU
, DIV
, DIVU
,
58 ADD
=0x20, ADDU
, SUB
, SUBU
, AND
, OR
, XOR
, NOR
,
63 typedef enum regimm_map
{
73 CP1_ADD
, CP1_SUB
, CP1_MUL
, CP1_DIV
, CP1_SQRT
, CP1_ABS
, CP1_MOV
, CP1_NEG
,
74 CP1_ROUND_W
= 12, CP1_TRUNC_W
, CP1_CEIL_W
, CP1_FLOOR_W
,
80 move from coprocessor 0
81 cop0=#10:6 MF=#0:5 rt:5 rd:5 0:8 sel:2
84 cop0=#10:6 MT=#4:5 rt:5 rd:5 0:8 sel:2
87 cop0=#10:6 co:1 0:19 ERET=#18:6
89 debug exception return
90 cop0=#10:6 co:1 0:19 DERET=#1F:6
92 probe tlb for matching entry
93 cop0=#10:6 co:1 0:19 TLBP=#08:6
95 read indexed tlb entry
96 cop0=#10:6 co:1 0:19 TLBR=#01:6
98 write indexed tlb entry
99 cop0=#10:6 co:1 0:19 TLBWI=#02:6
101 write random tlb entry
102 cop0=#10:6 co:1 0:19 TLBWR=#06:6
105 cop0=#10:6 co:1 impl.dep.:19 WAIT=#20:6
108 typedef enum c0_map
{
118 typedef union mips_instruction
{
125 root_map_t opcode
: 6;
131 root_map_t opcode
: 6;
137 root_map_t opcode
: 6;
140 unsigned offset
: 26;
141 root_map_t opcode
: 6;
149 union cp0_context_reg
{
151 unsigned pad
: 4; // LSB 0
152 unsigned badVPN2
: 21;
153 unsigned PTEbase
: 7; // MSB 31
158 union cp0_status_reg
{
161 unsigned ie
: 1; // Interrupt enable
162 unsigned exl
: 1; // Exception level
163 unsigned erl
: 1; // Error level
166 KSU_USER
} ksu
: 2; // Operating mode
167 unsigned ux
: 1; // Not used
168 unsigned sx
: 1; // Not used
169 unsigned kx
: 1; // Not used
170 unsigned im
: 8; // Interrupt Mask
171 unsigned ds_de
: 1; // Not used
172 unsigned ds_ce
: 1; // Not used
173 unsigned ds_ch
: 1; // CP0 condition bit
175 unsigned ds_sr
: 1; // Soft Reset or NMI occured
176 unsigned ds_ts
: 1; // TLB shutdown
177 unsigned ds_bev
: 1; // Bootstrap TLB Refill Vector
188 union cp0_cause_reg
{
192 enum { EXC_INT
, // Interrupt
193 EXC_MOD
, // TBL Modified
194 EXC_TLBL
, // TBL Refill (load & fetch)
195 EXC_TLBS
, // TBL Modified (store)
196 EXC_ADEL
, // Address Error (load & fetch)
197 EXC_ADES
, // Address Error (store)
198 EXC_IBE
, // Bus Error (fetch)
199 EXC_DBE
, // Bus Error (load & store)
200 EXC_SYS
, // System Call
201 EXC_BP
, // Breakpoint
202 EXC_RI
, // Reserved Instruction
203 EXC_CPU
, // Coprocessor Unusable
204 EXC_OV
, // Integer Overflow
206 EXC_WATCH
= 23 // Watch
207 } exc_code
: 5; // Exception code
209 unsigned ip
: 8; // Interrupt pending
211 unsigned ce
: 2; // Coprocessor # of unusable exception
213 unsigned bd
: 1; // Exception in a branch delay slot
223 /* Based on mipsregs.h in the linux distributions */
225 #define _ULCAST_ (unsigned long)
228 * Coprocessor 0 register names
232 #define CP0_ENTRYLO0 2
233 #define CP0_ENTRYLO1 3
235 #define CP0_CONTEXT 4
236 #define CP0_PAGEMASK 5
239 #define CP0_BADVADDR 8
241 #define CP0_ENTRYHI 10
242 #define CP0_COMPARE 11
243 #define CP0_STATUS 12
247 #define CP0_CONFIG 16
248 #define CP0_LLADDR 17
249 #define CP0_WATCHLO 18
250 #define CP0_WATCHHI 19
251 #define CP0_XCONTEXT 20
252 #define CP0_FRAMEMASK 21
253 #define CP0_DIAGNOSTIC 22
256 #define CP0_PERFORMANCE 25
258 #define CP0_CACHEERR 27
261 #define CP0_ERROREPC 30
262 #define CP0_DESAVE 31
265 * R4x00 interrupt enable / cause bits
267 #define IE_SW0 (_ULCAST_(1) << 8)
268 #define IE_SW1 (_ULCAST_(1) << 9)
269 #define IE_IRQ0 (_ULCAST_(1) << 10)
270 #define IE_IRQ1 (_ULCAST_(1) << 11)
271 #define IE_IRQ2 (_ULCAST_(1) << 12)
272 #define IE_IRQ3 (_ULCAST_(1) << 13)
273 #define IE_IRQ4 (_ULCAST_(1) << 14)
274 #define IE_IRQ5 (_ULCAST_(1) << 15)
277 * R4x00 interrupt cause bits
279 #define C_SW0 (_ULCAST_(1) << 8)
280 #define C_SW1 (_ULCAST_(1) << 9)
281 #define C_IRQ0 (_ULCAST_(1) << 10)
282 #define C_IRQ1 (_ULCAST_(1) << 11)
283 #define C_IRQ2 (_ULCAST_(1) << 12)
284 #define C_IRQ3 (_ULCAST_(1) << 13)
285 #define C_IRQ4 (_ULCAST_(1) << 14)
286 #define C_IRQ5 (_ULCAST_(1) << 15)
289 * Bitfields in the R4xx0 cp0 status register
291 #define ST0_IE 0x00000001
292 #define ST0_EXL 0x00000002
293 #define ST0_ERL 0x00000004
294 #define ST0_KSU 0x00000018
295 # define KSU_USER 0x00000010
296 # define KSU_SUPERVISOR 0x00000008
297 # define KSU_KERNEL 0x00000000
298 #define ST0_UX 0x00000020
299 #define ST0_SX 0x00000040
300 #define ST0_KX 0x00000080
301 #define ST0_DE 0x00010000
302 #define ST0_CE 0x00020000
305 * Status register bits available in all MIPS CPUs.
307 #define ST0_IM 0x0000ff00
308 #define STATUSB_IP0 8
309 #define STATUSF_IP0 (_ULCAST_(1) << 8)
310 #define STATUSB_IP1 9
311 #define STATUSF_IP1 (_ULCAST_(1) << 9)
312 #define STATUSB_IP2 10
313 #define STATUSF_IP2 (_ULCAST_(1) << 10)
314 #define STATUSB_IP3 11
315 #define STATUSF_IP3 (_ULCAST_(1) << 11)
316 #define STATUSB_IP4 12
317 #define STATUSF_IP4 (_ULCAST_(1) << 12)
318 #define STATUSB_IP5 13
319 #define STATUSF_IP5 (_ULCAST_(1) << 13)
320 #define STATUSB_IP6 14
321 #define STATUSF_IP6 (_ULCAST_(1) << 14)
322 #define STATUSB_IP7 15
323 #define STATUSF_IP7 (_ULCAST_(1) << 15)
324 #define STATUSB_IP8 0
325 #define STATUSF_IP8 (_ULCAST_(1) << 0)
326 #define STATUSB_IP9 1
327 #define STATUSF_IP9 (_ULCAST_(1) << 1)
328 #define STATUSB_IP10 2
329 #define STATUSF_IP10 (_ULCAST_(1) << 2)
330 #define STATUSB_IP11 3
331 #define STATUSF_IP11 (_ULCAST_(1) << 3)
332 #define STATUSB_IP12 4
333 #define STATUSF_IP12 (_ULCAST_(1) << 4)
334 #define STATUSB_IP13 5
335 #define STATUSF_IP13 (_ULCAST_(1) << 5)
336 #define STATUSB_IP14 6
337 #define STATUSF_IP14 (_ULCAST_(1) << 6)
338 #define STATUSB_IP15 7
339 #define STATUSF_IP15 (_ULCAST_(1) << 7)
340 #define ST0_CH 0x00040000
341 #define ST0_SR 0x00100000
342 #define ST0_TS 0x00200000
343 #define ST0_BEV 0x00400000
344 #define ST0_RE 0x02000000
345 #define ST0_FR 0x04000000
346 #define ST0_CU 0xf0000000
347 #define ST0_CU0 0x10000000
348 #define ST0_CU1 0x20000000
349 #define ST0_CU2 0x40000000
350 #define ST0_CU3 0x80000000
351 #define ST0_XX 0x80000000 /* MIPS IV naming */
354 * Bitfields and bit numbers in the coprocessor 0 cause register.
356 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
358 #define CAUSEB_EXCCODE 2
359 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
361 #define CAUSEF_IP (_ULCAST_(255) << 8)
363 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
365 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
366 #define CAUSEB_IP2 10
367 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
368 #define CAUSEB_IP3 11
369 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
370 #define CAUSEB_IP4 12
371 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
372 #define CAUSEB_IP5 13
373 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
374 #define CAUSEB_IP6 14
375 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
376 #define CAUSEB_IP7 15
377 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
379 #define CAUSEF_IV (_ULCAST_(1) << 23)
381 #define CAUSEF_CE (_ULCAST_(3) << 28)
383 #define CAUSEF_BD (_ULCAST_(1) << 31)
386 * Bits in the coprocessor 0 config register.
389 #define CONF_CM_CACHABLE_NO_WA 0
390 #define CONF_CM_CACHABLE_WA 1
391 #define CONF_CM_UNCACHED 2
392 #define CONF_CM_CACHABLE_NONCOHERENT 3
393 #define CONF_CM_CACHABLE_CE 4
394 #define CONF_CM_CACHABLE_COW 5
395 #define CONF_CM_CACHABLE_CUW 6
396 #define CONF_CM_CACHABLE_ACCELERATED 7
397 #define CONF_CM_CMASK 7
398 #define CONF_BE (_ULCAST_(1) << 15)
400 /* Bits common to various processors. */
401 #define CONF_CU (_ULCAST_(1) << 3)
402 #define CONF_DB (_ULCAST_(1) << 4)
403 #define CONF_IB (_ULCAST_(1) << 5)
404 #define CONF_DC (_ULCAST_(7) << 6)
405 #define CONF_IC (_ULCAST_(7) << 9)
406 #define CONF_EB (_ULCAST_(1) << 13)
407 #define CONF_EM (_ULCAST_(1) << 14)
408 #define CONF_SM (_ULCAST_(1) << 16)
409 #define CONF_SC (_ULCAST_(1) << 17)
410 #define CONF_EW (_ULCAST_(3) << 18)
411 #define CONF_EP (_ULCAST_(15)<< 24)
412 #define CONF_EC (_ULCAST_(7) << 28)
413 #define CONF_CM (_ULCAST_(1) << 31)
415 /* Bits specific to the VR41xx. */
416 #define VR41_CONF_CS (_ULCAST_(1) << 12)
417 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
418 #define VR41_CONF_AD (_ULCAST_(1) << 23)
422 /* All the architectual state */
423 typedef struct MIPS_state
{
431 u_int32_t fcr0
, fcr25
, fcr26
, fcr28
, fcsr
;
435 // union cp0_context_reg cp0_context = { .raw = 0 };
436 // unsigned cp0_badvaddr = 0;
437 // unsigned cp0_count = 0;
438 // unsigned cp0_compare = 0;
439 union cp0_status_reg cp0_status
;
440 union cp0_cause_reg cp0_cause
;