rtl/soclib/rs232out.v

   1 // -----------------------------------------------------------------------
   2 //
   3 //   Copyright 2004,2006 Tommy Thorn - All Rights Reserved
   4 //
   5 //   This program is free software; you can redistribute it and/or modify
   6 //   it under the terms of the GNU General Public License as published by
   7 //   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
   8 //   Bostom MA 02111-1307, USA; either version 2 of the License, or
   9 //   (at your option) any later version; incorporated herein by reference.
  10 //
  11 // -----------------------------------------------------------------------
  12
  13 `timescale 1ns/10ps
  14
  15 module rs232out(// Control
  16                 input wire         clk25MHz,
  17                 input wire         reset,
  18
  19                 // Serial line
  20                 output wire        serial_out,
  21
  22                 // Wishbone Interface
  23                 input  wire  [7:0] transmit_data,
  24                 input  wire        we,
  25                 output wire        busy);
  26
  27    //parameter         bps         =    9_600;
  28    parameter           bps        =     57_600;
  29    //parameter           bps         =  115_200;
  30    parameter           frequency   = 25_000_000;
  31 `ifndef __ICARUS__
  32    parameter           period      = frequency / bps;
  33 `else
  34    // One of the very few simulation artifacts we have to deal with at the source level.
  35    parameter           period      = 0;
  36 `endif
  37    parameter           TTYCLK_SIGN = 12; // 2^TTYCLK_SIGN > period * 2
  38    parameter           COUNT_SIGN  = 4;
  39
  40    reg [TTYCLK_SIGN:0] ttyclk      = 0; // [-4096; 4095]
  41    reg [8:0]           shift_out   = 0;
  42    reg [COUNT_SIGN:0]  count       = 0; // [-16; 15]
  43
  44    assign              serial_out  = shift_out[0];
  45    assign              busy        = ~count[COUNT_SIGN] | ~ttyclk[TTYCLK_SIGN];
  46
  47    always @(posedge clk25MHz)
  48      if (reset) begin
  49         shift_out  <= 9'h1F;
  50         ttyclk     <= ~0;
  51         count      <= ~0;
  52      end else if (~ttyclk[TTYCLK_SIGN]) begin
  53         ttyclk     <= ttyclk - 1;
  54      end else if (~count[COUNT_SIGN]) begin
  55         ttyclk     <= period - 2;
  56         count      <= count - 1;
  57         shift_out  <= {1'b1, shift_out[8:1]};
  58      end else if (we) begin
  59         ttyclk     <= period - 2;
  60         count      <= 9; // 1 start bit + 8 data + 1 stop - 1 due to SIGN trick
  61         shift_out  <= {transmit_data, 1'b0};
  62      end
  63 endmodule