2 `include "pipeconnect.h"
10 . unknown,undetermined,unimportant
11 # valid data (held stable)
18 Fasttarget presents the request address as the result data after one
19 cycle. Wait is never asserted.
21 WISHBONE - no wait states
23 clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
24 addr ........<#### A1 ####><#### A2 ####>.........................
25 read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
26 wait _____________________________________________________________
27 readdata _____________<#### D1 ####><#### D2 ####>____________________
30 PIPECONNECT - no wait states
31 Request noticed by target
32 | Response captured by initiator
34 clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
35 addr ........<#### A1 ####><#### A2 ####>.........................
36 read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
37 wait _____________________________________________________________
38 readdata ___________________________<#### D1 ####><#### D2 ####>______
41 PIPECONNECT - some wait states
42 Request noticed by target
43 | Response captured by initiator
45 clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
46 addr ........<#### A1 ##################><#### A2 ####>.........................
47 read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_______________________________________
48 wait _____________/~~~~~~~~~~~~\________________________________________________
49 readdata _________________________________________<#### D1 ####><#### D2 ####>______
51 module fasttarget
// PIPECONNECT, no wait
57 always @(posedge clk
) begin
59 res
`RD <= ~rst && req`R ? req`A : 0;
64 PIPECONNECT - 1 wait state
65 Request noticed by target
66 | Response captured by initiator
68 clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
69 addr ........<#### A1 ##################><#### A2 ##################>...........
70 read ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\/~~~~~~~~~~~~~~~~~~~~~~~~~~\___________
71 wait _____________/~~~~~~~~~~~~\______________/~~~~~~~~~~~~\____________________
72 readdata _________________________________________<#### D1 ####>______________<#### D2 ####>______
82 module slowtarget
// PIPECONNECT, 1 wait
86 output wire `RES res);
91 assign res
`RD = readData;
92 assign res
`WAIT = req`R & ~ready;
98 //$display("target in reset");
100 readData
<= ready ? req
`A : 0;
101 ready
<= req
`R & ~ready;
102 //$display("target %d %d", ready, res`WAIT);
107 Simple master waits for a result before issuing new request
109 PIPECONNECT - no wait states
110 Request noticed by target
111 | Response captured by initiator
113 clock /~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
114 addr ...<#####req 1###>...........................<#####req 2
115 read ___/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
116 wait ________________________________________________________
117 readdata ______________________<#############>___________________
121 Streaming master keeps one outstanding command
123 PIPECONNECT - no wait states
124 Request noticed by target
125 | Response captured by initiator
127 clock _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
128 addr ........<#####req 1###>.............<#####req 2
129 read ________/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
130 wait _____________________________________________________________
131 readdata ___________________________<#############>___________________
139 input wire `RES res);
142 reg [31:0] dataExpect
;
147 always @(posedge clk
)
154 dataValid
<= req
`R & ~res`WAIT;
156 if (dataExpect
!= res
`RD)
157 $display("%6d init%d got %x !!! BAD!", $time, name
, res
`RD);
159 $display("%6d init%d got %x as expected", $time, name
, res
`RD);
166 counter
<= counter
+ 1;
168 $display("%6d init%d requests %x", $time, name
, counter
);
177 wire [31:0] addr
= req
`A;
180 wire [31:0] data
= res
`RD;
182 initiator
initiator1(clk
, rst
, req1
, res1
);
183 initiator
initiator2(clk
, rst
, req2
, res2
);
184 mux2
mux_init(clk
, req1
, res1
, req2
, res2
, req
, res
);
185 slowtarget
target(clk
, rst
, req
, res
);
187 always #
5 clk
= ~clk
;
189 $monitor("%d%d %4d %x %d %d %x", rst
, clk
, $time, addr
, read
, wai
, data
);