| blob | 36cd8ee5bec9190392cc15a77a7dbb9b836d5885 |
1 # -------------------------------------------------------------------------- #\r
2 #\r
3 # Copyright (C) 1991-2010 Altera Corporation\r
4 # Your use of Altera Corporation's design tools, logic functions\r
5 # and other software and tools, and its AMPP partner logic\r
6 # functions, and any output files from any of the foregoing\r
7 # (including device programming or simulation files), and any\r
8 # associated documentation or information are expressly subject\r
9 # to the terms and conditions of the Altera Program License\r
10 # Subscription Agreement, Altera MegaCore Function License\r
11 # Agreement, or other applicable license agreement, including,\r
12 # without limitation, that your use is for the sole purpose of\r
13 # programming logic devices manufactured by Altera and sold by\r
14 # Altera or its authorized distributors. Please refer to the\r
15 # applicable agreement for further details.\r
16 #\r
17 # -------------------------------------------------------------------------- #\r
18 #\r
19 # Quartus II\r
20 # Version 10.0 Build 218 06/27/2010 SJ Web Edition\r
21 # Date created = 10:35:46 August 29, 2010\r
22 #\r
23 # -------------------------------------------------------------------------- #\r
24 #\r
25 # Notes:\r
26 #\r
27 # 1) The default values for assignments are stored in the file:\r
28 # echoserial_assignment_defaults.qdf\r
29 # If this file doesn't exist, see file:\r
30 # assignment_defaults.qdf\r
31 #\r
32 # 2) Altera recommends that you do not modify this file. This\r
33 # file is updated automatically by the Quartus II software\r
34 # and any changes you make may be lost or overwritten.\r
35 #\r
36 # -------------------------------------------------------------------------- #\r
37 \r
38 \r
39 set_global_assignment -name FAMILY "Cyclone III"\r
40 set_global_assignment -name DEVICE EP3C16F256C8\r
41 set_global_assignment -name TOP_LEVEL_ENTITY toplevel\r
42 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.0\r
43 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:35:46 AUGUST 29, 2010"\r
44 set_global_assignment -name LAST_QUARTUS_VERSION 10.0\r
45 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0\r
46 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85\r
47 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA\r
48 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256\r
49 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8\r
50 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1\r
51 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V\r
52 set_global_assignment -name SMART_RECOMPILE ON\r
53 \r
54 set_location_assignment PIN_E2 -to clk\r
55 set_location_assignment PIN_B4 -to led[0]\r
56 set_location_assignment PIN_C2 -to led[1]\r
57 set_location_assignment PIN_C3 -to led[2]\r
58 set_location_assignment PIN_D6 -to led[3]\r
59 set_location_assignment PIN_E6 -to led[4]\r
60 set_location_assignment PIN_B3 -to led[5]\r
61 set_location_assignment PIN_A7 -to led[6]\r
62 set_location_assignment PIN_B1 -to led[7]\r
63 set_location_assignment PIN_P6 -to ram_lb_n\r
64 set_location_assignment PIN_P3 -to ram_ub_n\r
65 set_location_assignment PIN_L2 -to ram_data[0]\r
66 set_location_assignment PIN_N3 -to ram_data[1]\r
67 set_location_assignment PIN_N1 -to ram_data[2]\r
68 set_location_assignment PIN_N2 -to ram_data[3]\r
69 set_location_assignment PIN_P1 -to ram_data[4]\r
70 set_location_assignment PIN_P2 -to ram_data[5]\r
71 set_location_assignment PIN_R1 -to ram_data[6]\r
72 set_location_assignment PIN_R3 -to ram_data[7]\r
73 set_location_assignment PIN_G1 -to ram_data[8]\r
74 set_location_assignment PIN_G2 -to ram_data[9]\r
75 set_location_assignment PIN_G5 -to ram_data[10]\r
76 set_location_assignment PIN_K5 -to ram_data[11]\r
77 set_location_assignment PIN_L4 -to ram_data[12]\r
78 set_location_assignment PIN_M6 -to ram_data[13]\r
79 set_location_assignment PIN_N6 -to ram_data[14]\r
80 set_location_assignment PIN_N5 -to ram_data[15]\r
81 set_location_assignment PIN_R6 -to ram_oe_n\r
82 set_location_assignment PIN_L1 -to ram_ce1_n\r
83 set_location_assignment PIN_T2 -to ram_we_n\r
84 set_location_assignment PIN_F2 -to ram_ce2\r
85 set_location_assignment PIN_L3 -to ram_addr[0]\r
86 set_location_assignment PIN_K1 -to ram_addr[1]\r
87 set_location_assignment PIN_K2 -to ram_addr[2]\r
88 set_location_assignment PIN_J1 -to ram_addr[3]\r
89 set_location_assignment PIN_J2 -to ram_addr[4]\r
90 set_location_assignment PIN_T7 -to ram_addr[5]\r
91 set_location_assignment PIN_T6 -to ram_addr[6]\r
92 set_location_assignment PIN_R7 -to ram_addr[7]\r
93 set_location_assignment PIN_F1 -to ram_addr[8]\r
94 set_location_assignment PIN_F3 -to ram_addr[9]\r
95 set_location_assignment PIN_D5 -to ram_addr[10]\r
96 set_location_assignment PIN_D1 -to ram_addr[11]\r
97 set_location_assignment PIN_D3 -to ram_addr[12]\r
98 set_location_assignment PIN_T5 -to ram_addr[13]\r
99 set_location_assignment PIN_R5 -to ram_addr[14]\r
100 set_location_assignment PIN_T4 -to ram_addr[15]\r
101 set_location_assignment PIN_R4 -to ram_addr[16]\r
102 set_location_assignment PIN_T3 -to ram_addr[17]\r
103 set_location_assignment PIN_A10 -to exp_pres\r
104 set_location_assignment PIN_T12 -to exp_rst_n\r
105 set_location_assignment PIN_C8 -to rxd\r
106 set_location_assignment PIN_D8 -to txd\r
107 \r
108 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top\r
109 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top\r
110 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top\r
111 set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"\r
112 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"\r
113 \r
114 \r
115 \r
116 \r
117 set_global_assignment -name SOURCE_FILE ../config.h\r
118 set_global_assignment -name VERILOG_FILE toplevel.v\r
119 set_global_assignment -name VERILOG_FILE mega/pll.v\r
120 set_global_assignment -name VERILOG_FILE sram16_ctrl.v\r
121 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/blockram.v\r
122 set_global_assignment -name SOURCE_FILE ../../shared/rtl/soclib/pipeconnect.h\r
123 set_global_assignment -name VERILOG_FILE "../../shared/rtl/yari-core/yari.v"\r
124 set_global_assignment -name VERILOG_FILE "../../shared/rtl/yari-core/asm.v"\r
125 set_global_assignment -name VERILOG_FILE "../../shared/rtl/yari-core/stage_I.v"\r
126 set_global_assignment -name VERILOG_FILE "../../shared/rtl/yari-core/stage_D.v"\r
127 set_global_assignment -name VERILOG_FILE "../../shared/rtl/yari-core/stage_X.v"\r
128 set_global_assignment -name VERILOG_FILE "../../shared/rtl/yari-core/stage_M.v"\r
129 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/dmem.v\r
130 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/peri_ctrl.v\r
131 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/pipeconnect.v\r
132 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/rs232.v\r
133 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/rs232in.v\r
134 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/rs232out.v\r
135 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/bus_ctrl.v\r
136 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/dc_ctrl.v\r
137 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/vga.v\r
138 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/hexled.v\r
139 set_global_assignment -name VERILOG_FILE ../../shared/rtl/altera/cyclone/logshiftright.v\r
140 set_global_assignment -name VERILOG_FILE ../../shared/rtl/altera/cyclone/arithshiftbidir.v\r
141 set_global_assignment -name VERILOG_FILE ../../shared/rtl/altera/cyclone/simpledpram.v\r
142 set_global_assignment -name VERILOG_FILE ../../shared/rtl/altera/cyclone/dpram.v\r
143 set_global_assignment -name MIF_FILE ../initmem.mif\r
144 set_global_assignment -name MIF_FILE ../tags0.mif\r
145 set_global_assignment -name MIF_FILE ../tags1.mif\r
146 set_global_assignment -name MIF_FILE ../tags2.mif\r
147 set_global_assignment -name MIF_FILE ../tags3.mif\r
148 set_global_assignment -name SDC_FILE yari.sdc\r
149 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top