rtl/target/Cycore-ep1c12/main.v

   1 // -----------------------------------------------------------------------
   2 //
   3 //   Copyright 2004,2007 Tommy Thorn - All Rights Reserved
   4 //
   5 //   This program is free software; you can redistribute it and/or modify
   6 //   it under the terms of the GNU General Public License as published by
   7 //   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
   8 //   Bostom MA 02111-1307, USA; either version 2 of the License, or
   9 //   (at your option) any later version; incorporated herein by reference.
  10 //
  11 // -----------------------------------------------------------------------
  12 //
  13 // Main module
  14
  15
  16 /*
  17   4000_0000 - 400F_FFFF Extern SRAM (1 MiB)
  18   BFC0_0000 - BFC0_3FFF Boot ROM (16 KiB) (Preloaded I$ cache)
  19   FF00_0000 - FF00_1FFF Peripherals
  20                         Read             Write
  21                       0 rs232out busy    rs232out data
  22                       1 rs232in  data
  23                       2 rs232in  count
  24                       3 TSC
  25  */
  26
  27 `timescale 1ns/10ps
  28 `include "../../soclib/pipeconnect.h"
  29 module main(
  30
  31         input wire clk,
  32 //
  33 //      serial interface
  34 //
  35         output wire ser_txd,
  36         input wire ser_rxd,
  37         input wire ser_ncts,
  38         output wire ser_nrts,
  39
  40 //
  41 //      watchdog
  42 //
  43         output wire wd,
  44
  45 //
  46 //      two ram banks
  47 //
  48         output wire [17:0] rama_a,
  49         inout wire [15:0] rama_d,
  50         output wire rama_ncs,
  51         output wire rama_noe,
  52         output wire rama_nlb,
  53         output wire rama_nub,
  54         output wire rama_nwe,
  55         output wire [17:0] ramb_a,
  56         inout wire [15:0] ramb_d,
  57         output wire ramb_ncs,
  58         output wire ramb_noe,
  59         output wire ramb_nlb,
  60         output wire ramb_nub,
  61         output wire ramb_nwe);
  62
  63    wire clock;
  64
  65    pll pll(.inclk0(clk),    // 20 MHz on Cycore
  66            .c0(clock),      // xx MHz output
  67           );
  68
  69    assign wd = rst_counter[22];
  70
  71    reg [26:0] rst_counter = 0;
  72    always @(posedge clock)
  73 //      if (~USER_PB[0])
  74 //         rst_counter <= 'd48_000_000;
  75 //      else if (~rst_counter[26])
  76       if (~rst_counter[26])
  77          rst_counter <= rst_counter - 1;
  78
  79    wire rst = ~rst_counter[26];
  80
  81    assign       ramb_a = rama_a;
  82    assign       ramb_ncs = rama_ncs;
  83    assign       ramb_noe = rama_noe;
  84    assign       ramb_nwe = rama_nwe;
  85
  86
  87
  88
  89    parameter FREQ = 40_000_000; // match clock frequency
  90    parameter BPS  =    115_200; // Serial speed
  91
  92    wire [ 7:0]   rs232out_d;
  93    wire          rs232out_w;
  94    wire          rs232out_busy;
  95
  96    wire [ 7:0]   rs232in_data;
  97    wire          rs232in_attention;
  98
  99    wire          mem_waitrequest;
 100    wire    [1:0] mem_id;
 101    wire   [29:0] mem_address;
 102    wire          mem_read;
 103    wire          mem_write;
 104    wire   [31:0] mem_writedata;
 105    wire    [3:0] mem_writedatamask;
 106    wire   [31:0] mem_readdata;
 107    wire    [1:0] mem_readdataid;
 108
 109    wire `REQ     rs232_req;
 110    wire `RES     rs232_res;
 111
 112    yari yari_inst(
 113          .clock(clock)
 114         ,.rst(rst)
 115
 116         ,.mem_waitrequest(mem_waitrequest)
 117         ,.mem_id(mem_id)
 118         ,.mem_address(mem_address)
 119         ,.mem_read(mem_read)
 120         ,.mem_write(mem_write)
 121         ,.mem_writedata(mem_writedata)
 122         ,.mem_writedatamask(mem_writedatamask)
 123         ,.mem_readdata(mem_readdata)
 124         ,.mem_readdataid(mem_readdataid)
 125
 126         ,.peripherals_req(rs232_req)
 127         ,.peripherals_res(rs232_res)
 128         );
 129
 130    sram_ctrl sram_ctrl
 131       (.clock(clk)
 132       ,.rst(rst)
 133       ,.mem_waitrequest(mem_waitrequest)
 134       ,.mem_id(mem_id)
 135       ,.mem_address(mem_address)
 136       ,.mem_read(mem_read)
 137       ,.mem_write(mem_write)
 138       ,.mem_writedata(mem_writedata)
 139       ,.mem_writedatamask(mem_writedatamask)
 140       ,.mem_readdata(mem_readdata)
 141       ,.mem_readdataid(mem_readdataid)
 142
 143       ,.sram_a(rama_a)
 144       ,.sram_d({rama_d,ramb_d})
 145       ,.sram_cs_n(rama_ncs)
 146       ,.sram_be_n({rama_nub,rama_nlb,ramb_nub,ramb_nlb})
 147       ,.sram_oe_n(rama_noe)
 148       ,.sram_we_n(rama_nwe)
 149       );
 150
 151    rs232out #(BPS,FREQ)
 152       rs232out_inst(.clk25MHz(clock),
 153                .reset(0),
 154
 155                .serial_out(ser_txd),
 156                .transmit_data(rs232out_d),
 157                .we(rs232out_w),
 158                .busy(rs232out_busy));
 159
 160    rs232in #(BPS,FREQ)
 161       rs232in_inst(.clk25MHz(clock),
 162                    .reset(0),
 163
 164                    .serial_in(ser_rxd),
 165                    .received_data(rs232in_data),
 166                    .attention(rs232in_attention));
 167
 168    rs232 rs232_inst(.clk(clock),
 169                .rst(rst),
 170
 171                .rs232_req(rs232_req),
 172                .rs232_res(rs232_res),
 173
 174                .rs232in_attention(rs232in_attention),
 175                .rs232in_data(rs232in_data),
 176
 177                .rs232out_busy(rs232out_busy),
 178                .rs232out_w(rs232out_w),
 179                .rs232out_d(rs232out_d));
 180 endmodule