2 OOOOOO AAAAA AAAAA AAAAA AAAAA AAAAAA (only J and JAL)
5 OOOOOO SSSSS TTTTT IIIII IIIII IIIIII (dest is rT)
8 OOOOOO SSSSS TTTTT DDDDD MMMMM FFFFFF (dest is rD)
11 Root map (nearly all I-type )
16 000010 iiiii iiiii iiiii iiiii iiiiii J -- Jump
17 000011 iiiii iiiii iiiii iiiii iiiiii JAL -- Jump and link
19 000100 sssss ttttt iiiii iiiii iiiiii BEQ -- Branch on equal
20 000101 sssss ttttt iiiii iiiii iiiiii BNE -- Branch on not equal
21 000110 sssss 00000 iiiii iiiii iiiiii BLEZ -- Branch on less than or equal to zero
22 000111 sssss 00000 iiiii iiiii iiiiii BGTZ -- Branch on greater than zero
23 001000 sssss ttttt iiiii iiiii iiiiii ADDI -- Add immediate
24 001001 sssss ttttt iiiii iiiii iiiiii ADDIU -- Add immediate unsigned
25 001010 sssss ttttt iiiii iiiii iiiiii SLTI -- Set on less than immediate (signed)
26 001011 sssss ttttt iiiii iiiii iiiiii SLTIU -- Set on less than immediate unsigned
27 001100 sssss ttttt iiiii iiiii iiiiii ANDI -- Bitwise and immediate
28 001101 sssss ttttt iiiii iiiii iiiiii ORI -- Bitwise or immediate
29 001110 sssss ttttt iiiii iiiii iiiiii XORI -- Bitwise exclusive or immediate
30 001111 ----- ttttt iiiii iiiii iiiiii LUI -- Load upper immediate
31 010000 ----- ttttt iiiii iiiii iiiiii LLO --
32 010001 ----- ttttt iiiii iiiii iiiiii TRAP --
34 100000 sssss ttttt iiiii iiiii iiiiii LB -- Load byte
35 100001 sssss ttttt iiiii iiiii iiiiii LH -- Load half
36 100011 sssss ttttt iiiii iiiii iiiiii LW -- Load word
37 100100 sssss ttttt iiiii iiiii iiiiii LBU -- Load byte unsigned
38 100101 sssss ttttt iiiii iiiii iiiiii LHU -- Load half unsigned
39 101000 sssss ttttt iiiii iiiii iiiiii SB -- Store byte
40 101001 sssss ttttt iiiii iiiii iiiiii SH -- Store half
41 101011 sssss ttttt iiiii iiiii iiiiii SW -- Store word
44 000000 00000 00000 00000 00000 000000 NOP -- no operation
45 000000 sssss ttttt ddddd hhhhh 000000 SLL -- Shift left logical
46 000000 ----- ttttt ddddd hhhhh 000010 SRL -- Shift right logical
47 000000 ----- ttttt ddddd hhhhh 000011 SRA -- Shift right arithmetic
48 000000 sssss ttttt ddddd 00000 000100 SLLV -- Shift left logical variable
49 000000 sssss ttttt ddddd 00000 000110 SRLV -- Shift right logical variable
50 000000 sssss ttttt ddddd 00000 000111 SRAV -- Shift right logical variable
51 000000 sssss 00000 00000 00000 001000 JR -- Jump register
52 000000 sssss 00000 ddddd 00000 001001 JALR -- Jump and link register
53 000000 ----- ----- ----- ----- 001100 SYSCALL -- System call
55 000000 00000 00000 ddddd 00000 010000 MFHI -- Move from HI
56 000000 sssss 00000 00000 00000 010001 MTHI -- Move to HI
57 000000 00000 00000 ddddd 00000 010010 MFLO -- Move from LO
58 000000 sssss 00000 00000 00000 010011 MTLO -- Move to LO
59 000000 sssss ttttt 00000 00000 011000 MULT -- Multiply
60 000000 sssss ttttt 00000 00000 011001 MULTU -- Multiply unsigned
61 000000 sssss ttttt 00000 00000 011010 DIV -- Divide
62 000000 sssss ttttt 00000 00000 011011 DIVU -- Divide unsigned
64 000000 sssss ttttt ddddd 00000 100000 ADD -- Add
65 000000 sssss ttttt ddddd 00000 100001 ADDU -- Add unsigned
66 000000 sssss ttttt ddddd 00000 100010 SUB -- Subtract
67 000000 sssss ttttt ddddd 00000 100011 SUBU -- Subtract unsigned
68 000000 sssss ttttt ddddd 00000 100100 AND -- Bitwise and
69 000000 sssss ttttt ddddd 00000 100101 OR -- Bitwise or
70 000000 sssss ttttt ddddd ----- 100110 XOR -- Bitwise exclusive or
71 000000 sssss ttttt ddddd ----- 100111 NOR -- Bitwise not or
72 000000 sssss ttttt ddddd 00000 101010 SLT -- Set on less than (signed)
73 000000 sssss ttttt ddddd 00000 101011 SLTU -- Set on less than unsigned
75 regimm_map // All I-type
76 000001 sssss 00000 iiiii iiiii iiiiii BLTZ -- Branch on less than zero
77 000001 sssss 00001 iiiii iiiii iiiiii BGEZ -- Branch on greater than or equal to zero
78 000001 sssss 10000 iiiii iiiii iiiiii BLTZAL -- Branch on less than zero and link
79 000001 sssss 10001 iiiii iiiii iiiiii BGEZAL -- Branch on greater than or equal to zero and link
83 Partial toplevel matrix:
86 0 REG REGIMM J JAL BEQ BNE BLEZ BGTZ
87 1 ADDI ADDIU SLTI SLTIU ANDI* ORI* XORI* LUI*
88 2 CP0 CP1 CP2 BBQL BGTZL
90 4 LB LH LWL LW LBU LHU LWR
95 The four marked instructions (*) does not sign extend their operand
96 (instead of producing the sign extended and non-sign extended
97 immediate operand as I do today, I could just make those instructions
98 pretend the upper 16-bit are zero...).