shared/rtl/soclib/rs232in.v

   1 // -----------------------------------------------------------------------
   2 //
   3 //   Copyright 2004,2007-2008 Tommy Thorn - All Rights Reserved
   4 //
   5 //   This program is free software; you can redistribute it and/or modify
   6 //   it under the terms of the GNU General Public License as published by
   7 //   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
   8 //   Bostom MA 02111-1307, USA; either version 2 of the License, or
   9 //   (at your option) any later version; incorporated herein by reference.
  10 //
  11 // -----------------------------------------------------------------------
  12
  13 `timescale 1ns/10ps
  14
  15 module rs232in
  16    (// Control
  17     input  wire        clock,
  18
  19     // Serial line
  20     input  wire        serial_in,
  21     output reg         attention = 0,
  22     output reg   [7:0] received_data = 0);
  23
  24    parameter           bps        =     57_600;
  25    parameter           frequency  = 25_000_000;
  26    parameter           period     = (frequency + bps/2) / bps;
  27
  28    reg  [16:0] ttyclk       = 0;
  29    wire [31:0] ttyclk_bit   = period - 2;
  30    wire [31:0] ttyclk_start = (3 * period) / 2 - 2;
  31    reg  [ 7:0] shift_in     = 0;
  32    reg  [ 4:0] count        = 0;
  33
  34    reg         rxd          = 0;
  35    reg         rxd2         = 0;
  36
  37    /*
  38     * The theory: look for a negedge, then wait 1.5 bit period to skip
  39     * start bit and center in first bit.  Keep shifting bits until a full
  40     * byte is collected.
  41     *
  42     *        Start                        Stop
  43     * data   ~\__ B0 B1 B2 B3 B4 B5 B6 B7 ~~
  44     * count        8  7  6  5  4  3  2  1
  45     */
  46    always @(posedge clock) begin
  47       attention <= 0;
  48
  49       // Get rid of meta stability.
  50       {rxd2,rxd} <= {rxd,serial_in};
  51
  52       if (~ttyclk[16]) begin
  53          ttyclk <= ttyclk - 1'd1;
  54       end else if (count) begin
  55          if (count == 1) begin
  56             received_data <= {rxd2, shift_in[7:1]};
  57             attention     <= 1;
  58          end
  59
  60          count       <= count - 1'd1;
  61          shift_in    <= {rxd2, shift_in[7:1]}; // Shift in from the left
  62          ttyclk      <= ttyclk_bit[16:0];
  63       end else if (~rxd2) begin
  64          // Just saw the negedge of the start bit
  65          ttyclk      <= ttyclk_start[16:0];
  66          count       <= 8;
  67       end
  68    end
  69 endmodule