1 # -------------------------------------------------------------------------- #
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3 # Copyright (C) 1991-2010 Altera Corporation
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4 # Your use of Altera Corporation's design tools, logic functions
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5 # and other software and tools, and its AMPP partner logic
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6 # functions, and any output files from any of the foregoing
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7 # (including device programming or simulation files), and any
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8 # associated documentation or information are expressly subject
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9 # to the terms and conditions of the Altera Program License
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10 # Subscription Agreement, Altera MegaCore Function License
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11 # Agreement, or other applicable license agreement, including,
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12 # without limitation, that your use is for the sole purpose of
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13 # programming logic devices manufactured by Altera and sold by
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14 # Altera or its authorized distributors. Please refer to the
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15 # applicable agreement for further details.
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17 # -------------------------------------------------------------------------- #
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20 # Version 10.0 Build 218 06/27/2010 SJ Web Edition
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21 # Date created = 10:35:46 August 29, 2010
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23 # -------------------------------------------------------------------------- #
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27 # 1) The default values for assignments are stored in the file:
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28 # echoserial_assignment_defaults.qdf
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29 # If this file doesn't exist, see file:
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30 # assignment_defaults.qdf
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32 # 2) Altera recommends that you do not modify this file. This
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33 # file is updated automatically by the Quartus II software
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34 # and any changes you make may be lost or overwritten.
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36 # -------------------------------------------------------------------------- #
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39 set_global_assignment -name FAMILY "Cyclone III"
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40 set_global_assignment -name DEVICE EP3C16F256C8
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41 set_global_assignment -name TOP_LEVEL_ENTITY toplevel
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42 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 10.0
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43 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:35:46 AUGUST 29, 2010"
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44 set_global_assignment -name LAST_QUARTUS_VERSION 10.0
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45 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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46 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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47 set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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48 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256
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49 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
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50 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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51 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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52 set_global_assignment -name SMART_RECOMPILE ON
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54 set_location_assignment PIN_E2 -to clk
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55 set_location_assignment PIN_B4 -to led[0]
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56 set_location_assignment PIN_C2 -to led[1]
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57 set_location_assignment PIN_C3 -to led[2]
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58 set_location_assignment PIN_D6 -to led[3]
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59 set_location_assignment PIN_E6 -to led[4]
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60 set_location_assignment PIN_B3 -to led[5]
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61 set_location_assignment PIN_A7 -to led[6]
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62 set_location_assignment PIN_B1 -to led[7]
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63 set_location_assignment PIN_P6 -to ram_lb_n
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64 set_location_assignment PIN_P3 -to ram_ub_n
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65 set_location_assignment PIN_L2 -to ram_data[0]
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66 set_location_assignment PIN_N3 -to ram_data[1]
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67 set_location_assignment PIN_N1 -to ram_data[2]
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68 set_location_assignment PIN_N2 -to ram_data[3]
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69 set_location_assignment PIN_P1 -to ram_data[4]
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70 set_location_assignment PIN_P2 -to ram_data[5]
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71 set_location_assignment PIN_R1 -to ram_data[6]
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72 set_location_assignment PIN_R3 -to ram_data[7]
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73 set_location_assignment PIN_G1 -to ram_data[8]
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74 set_location_assignment PIN_G2 -to ram_data[9]
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75 set_location_assignment PIN_G5 -to ram_data[10]
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76 set_location_assignment PIN_K5 -to ram_data[11]
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77 set_location_assignment PIN_L4 -to ram_data[12]
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78 set_location_assignment PIN_M6 -to ram_data[13]
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79 set_location_assignment PIN_N6 -to ram_data[14]
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80 set_location_assignment PIN_N5 -to ram_data[15]
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81 set_location_assignment PIN_R6 -to ram_oe_n
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82 set_location_assignment PIN_L1 -to ram_ce1_n
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83 set_location_assignment PIN_T2 -to ram_we_n
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84 set_location_assignment PIN_F2 -to ram_ce2
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85 set_location_assignment PIN_L3 -to ram_addr[0]
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86 set_location_assignment PIN_K1 -to ram_addr[1]
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87 set_location_assignment PIN_K2 -to ram_addr[2]
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88 set_location_assignment PIN_J1 -to ram_addr[3]
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89 set_location_assignment PIN_J2 -to ram_addr[4]
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90 set_location_assignment PIN_T7 -to ram_addr[5]
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91 set_location_assignment PIN_T6 -to ram_addr[6]
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92 set_location_assignment PIN_R7 -to ram_addr[7]
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93 set_location_assignment PIN_F1 -to ram_addr[8]
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94 set_location_assignment PIN_F3 -to ram_addr[9]
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95 set_location_assignment PIN_D5 -to ram_addr[10]
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96 set_location_assignment PIN_D1 -to ram_addr[11]
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97 set_location_assignment PIN_D3 -to ram_addr[12]
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98 set_location_assignment PIN_T5 -to ram_addr[13]
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99 set_location_assignment PIN_R5 -to ram_addr[14]
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100 set_location_assignment PIN_T4 -to ram_addr[15]
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101 set_location_assignment PIN_R4 -to ram_addr[16]
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102 set_location_assignment PIN_T3 -to ram_addr[17]
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103 set_location_assignment PIN_A10 -to exp_pres
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104 set_location_assignment PIN_T12 -to exp_rst_n
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105 set_location_assignment PIN_C8 -to rxd
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106 set_location_assignment PIN_D8 -to txd
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108 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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109 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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110 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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111 set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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112 set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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117 set_global_assignment -name SOURCE_FILE ../config.h
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118 set_global_assignment -name VERILOG_FILE toplevel.v
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119 set_global_assignment -name VERILOG_FILE mega/pll.v
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120 set_global_assignment -name VERILOG_FILE sram16_ctrl.v
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121 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/blockram.v
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122 set_global_assignment -name SOURCE_FILE ../../shared/rtl/soclib/pipeconnect.h
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123 set_global_assignment -name VERILOG_FILE "../../shared/rtl/yari-core/yari.v"
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124 set_global_assignment -name VERILOG_FILE "../../shared/rtl/yari-core/asm.v"
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125 set_global_assignment -name VERILOG_FILE "../../shared/rtl/yari-core/stage_I.v"
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126 set_global_assignment -name VERILOG_FILE "../../shared/rtl/yari-core/stage_D.v"
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127 set_global_assignment -name VERILOG_FILE "../../shared/rtl/yari-core/stage_X.v"
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128 set_global_assignment -name VERILOG_FILE "../../shared/rtl/yari-core/stage_M.v"
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129 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/dmem.v
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130 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/peri_ctrl.v
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131 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/pipeconnect.v
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132 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/rs232.v
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133 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/rs232in.v
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134 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/rs232out.v
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135 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/bus_ctrl.v
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136 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/dc_ctrl.v
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137 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/vga.v
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138 set_global_assignment -name VERILOG_FILE ../../shared/rtl/soclib/hexled.v
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139 set_global_assignment -name VERILOG_FILE ../../shared/rtl/altera/cyclone/logshiftright.v
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140 set_global_assignment -name VERILOG_FILE ../../shared/rtl/altera/cyclone/arithshiftbidir.v
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141 set_global_assignment -name VERILOG_FILE ../../shared/rtl/altera/CycloneIII/simpledpram.v
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142 set_global_assignment -name VERILOG_FILE ../../shared/rtl/altera/CycloneIII/dpram.v
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143 set_global_assignment -name MIF_FILE ../initmem.mif
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144 set_global_assignment -name MIF_FILE ../tags0.mif
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145 set_global_assignment -name MIF_FILE ../tags1.mif
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146 set_global_assignment -name MIF_FILE ../tags2.mif
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147 set_global_assignment -name MIF_FILE ../tags3.mif
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148 set_global_assignment -name SDC_FILE yari.sdc
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149 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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