Icarus/testpipe2.v

   1 `timescale 1ns/10ps
   2 `include "pipeconnect.h"
   3
   4 /*
   5  Notation:
   6  _  low, 0
   7  ~  high, 1
   8  /  posedge
   9  \  negedge
  10  .  unknown,undetermined,unimportant
  11  #  valid data (held stable)
  12  <  changing
  13  >  --
  14  */
  15
  16
  17 /*
  18  Fasttarget presents the request address as the result data after one
  19  cycle.  Wait is never asserted.
  20
  21  WISHBONE - no wait states
  22
  23  clock      _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
  24  addr       ........<#### A1 ####><#### A2 ####>.........................
  25  read       ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
  26  wait       _____________________________________________________________
  27  readdata   _____________<#### D1 ####><#### D2 ####>____________________
  28
  29
  30  PIPECONNECT - no wait states
  31                                Request noticed by target
  32                                |             Response captured by initiator
  33                                v             v
  34  clock      _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
  35  addr       ........<#### A1 ####><#### A2 ####>.........................
  36  read       ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_________________________
  37  wait       _____________________________________________________________
  38  readdata   ___________________________<#### D1 ####><#### D2 ####>______
  39
  40
  41  PIPECONNECT - some wait states
  42                                Request noticed by target
  43                                |             Response captured by initiator
  44                                v             v
  45  clock      _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
  46  addr       ........<#### A1 ##################><#### A2 ####>.........................
  47  read       ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\_______________________________________
  48  wait       _____________/~~~~~~~~~~~~\________________________________________________
  49  readdata   _________________________________________<#### D1 ####><#### D2 ####>______
  50  */
  51 module fasttarget // PIPECONNECT, no wait
  52   (input  wire        clk,
  53    input  wire        rst,
  54    input  wire `REQ   req,
  55    output reg  `RES   res);
  56
  57    always @(posedge clk) begin
  58       res`WAIT <= 0;
  59       res`RD <= ~rst && req`R ? req`A : 0;
  60    end
  61 endmodule
  62
  63 /*
  64  PIPECONNECT - 1 wait state
  65                                Request noticed by target
  66                                |             Response captured by initiator
  67                                v             v
  68  clock      _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
  69  addr       ........<#### A1 ##################><#### A2 ##################>...........
  70  read       ________/~~~~~~~~~~~~~~~~~~~~~~~~~~\/~~~~~~~~~~~~~~~~~~~~~~~~~~\___________
  71  wait       _____________/~~~~~~~~~~~~\______________/~~~~~~~~~~~~\____________________
  72  readdata   _________________________________________<#### D1 ####>______________<#### D2 ####>______
  73
  74  _~_~_~_~_~_
  75
  76  .AAAABBBB..
  77  _~~~~~~~~__
  78  _~~__~~____
  79  _____aa__bb
  80
  81 */
  82 module slowtarget // PIPECONNECT, 1 wait
  83   (input  wire        clk,
  84    input  wire        rst,
  85    input  wire `REQ   req,
  86    output wire `RES   res);
  87
  88    reg [31:0] readData;
  89    reg        ready;
  90
  91    assign     res`RD = readData;
  92    assign     res`WAIT = req`R & ~ready;
  93
  94    always @(posedge clk)
  95      if (rst) begin
  96         readData <= 0;
  97         ready    <= 0;
  98         //$display("target in reset");
  99      end else begin
 100         readData <= ready ? req`A : 0;
 101         ready    <= req`R & ~ready;
 102         //$display("target %d %d", ready, res`WAIT);
 103      end
 104 endmodule
 105
 106 /*
 107  Simple master waits for a result before issuing new request
 108
 109  PIPECONNECT - no wait states
 110                                Request noticed by target
 111                                |             Response captured by initiator
 112                                v             v
 113  clock      /~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
 114  addr       ...<#####req 1###>...........................<#####req 2
 115  read       ___/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
 116  wait       ________________________________________________________
 117  readdata   ______________________<#############>___________________
 118  */
 119
 120 /*
 121  Streaming master keeps one outstanding command
 122
 123  PIPECONNECT - no wait states
 124                                Request noticed by target
 125                                |             Response captured by initiator
 126                                v             v
 127  clock      _____/~~~~~~\______/~~~~~~\______/~~~~~~\______/~~~~~~\______
 128  addr       ........<#####req 1###>.............<#####req 2
 129  read       ________/~~~~~~~~~~~~~\___________________________/~~~~~~~~~~
 130  wait       _____________________________________________________________
 131  readdata   ___________________________<#############>___________________
 132
 133 */
 134
 135 module initiator
 136   (input  wire        clk,
 137    input  wire        rst,
 138    output reg  `REQ   req,
 139    input  wire `RES   res);
 140
 141    parameter  name = 1;
 142
 143    reg [31:0] counter, data;
 144    reg [31:0] dataExpect;
 145    reg        dataValid;
 146    wire       pause = ^counter[1:0];
 147
 148    always @(posedge clk)
 149      if (rst) begin
 150         counter <= name << 16;
 151         req     <= 0;
 152         dataValid <= 0;
 153         dataExpect <= 0;
 154      end else begin
 155         dataExpect <= data;
 156         dataValid <= req`R & ~res`WAIT;
 157         if (dataValid) begin
 158            if (dataExpect != res`RD)
 159              $display("%6d init%d got %x, expected %x !!! BAD!",
 160                       $time, name, res`RD, dataExpect);
 161            else
 162              $display("%6d init%d got %x as expected", $time, name, res`RD);
 163         end
 164
 165         if (~res`WAIT) begin
 166            counter <= counter + 1;
 167            if (pause) begin
 168               req`R   <= 0;
 169            end else begin
 170               req`R   <= 1;
 171               req`A   <= counter;
 172               data    <= counter;
 173               $display("%6d init%d requests %x", $time, name, counter);
 174            end
 175         end
 176      end
 177 endmodule
 178
 179 module main();
 180    reg rst, clk;
 181    wire `REQ req, req1, req2;
 182    wire `RES res, res1, res2;
 183    wire [31:0] addr = req`A;
 184    wire        read = req`R;
 185    wire        wai  = res`WAIT;
 186    wire [31:0] data = res`RD;
 187
 188    initiator  #(1) initiator1(clk, rst, req1, res1);
 189    initiator  #(2) initiator2(clk, rst, req2, res2);
 190    mux2       mux_init(clk, req1, res1, req2, res2, req, res);
 191    slowtarget target(clk, rst, req, res);
 192
 193    always # 5 clk = ~clk;
 194    initial begin
 195       $monitor("%d%d %4d %x %d %d %x", rst, clk, $time, addr, read, wai, data);
 196       clk = 1;
 197       rst = 1;
 198       #15 rst = 0;
 199       #200 $finish;
 200    end
 201 endmodule