theora-fpga/theora_hardware/theora_hardware.vhd

   1 -------------------------------------------------------------------------------
   2 -- Title      : Theora Hardware
   3 -- Project    : theora-fpga
   4 -------------------------------------------------------------------------------
   5 -- File       : theora_hardware.vhd
   6 -- Author     : Leonardo de Paula Rosa Piga
   7 -- Company    : LSC - IC - UNICAMP
   8 -- Last update: 2007/08/23
   9 -- Platform   :
  10 -------------------------------------------------------------------------------
  11 -- Description: Wrapper to receive data from NIOS processor
  12 -------------------------------------------------------------------------------
  13
  14 library std;
  15 library ieee;
  16 use ieee.std_logic_1164.all;
  17 use ieee.numeric_std.all;
  18
  19 entity theora_hardware is
  20
  21   port (
  22     clk : in std_logic;
  23     clk_25Mhz : in std_logic;
  24     reset_n      : in  std_logic;                     -- reset
  25
  26     ---------------------------------------------------------------------------
  27     -- Ports of Handshake
  28     ---------------------------------------------------------------------------
  29     in_request    : out std_logic;
  30     in_valid      : in  std_logic;      -- in_data
  31     in_data       : in  signed(31 downto 0);
  32
  33     -- Remover depois
  34     out_valid     : out std_logic;
  35     ---------------------------------------------------------------------------
  36     -- Ports of video controller
  37     ---------------------------------------------------------------------------
  38     red          : out std_logic_vector(7 downto 0);  -- red component
  39     green        : out std_logic_vector(7 downto 0);  -- green component
  40     blue         : out std_logic_vector(7 downto 0);  -- blue component
  41     line_pixel   : out std_logic_vector(9 downto 0);  -- compute line
  42     column_pixel : out std_logic_vector(9 downto 0);  -- compute column
  43     m1, m2       : out std_logic;                     -- select dac mode
  44     blank_n      : out std_logic;                     -- dac command
  45     sync_n       : out std_logic;                     -- dac command
  46     sync_t       : out std_logic;                     -- dac command
  47     video_clk    : out std_logic;                     -- dac command
  48     vga_vs       : out std_logic;                     -- vertical sync
  49     vga_hs       : out std_logic                      -- horizontal sync
  50     );
  51
  52 end theora_hardware;
  53
  54 architecture a_theora_hardware of theora_hardware is
  55   constant DEPTH      : natural := 8192;       -- RGB MEMORY DEPTH
  56   constant ADDR_WIDTH : natural := 13;         -- RGB MEMORY ADDRESS WIDTH
  57   constant DATA_WIDTH : natural := 24;         -- RGB MEMORY DATA WIDTH
  58
  59   component interface_vga
  60     generic (
  61       DEPTH      : natural := 8192;              -- RGB MEMORY DEPTH
  62       ADDR_WIDTH : natural := 13;                -- RGB MEMORY ADDRESS WIDTH
  63       DATA_WIDTH : natural := 24;                -- RGB MEMORY DATA WIDTH
  64       ZOOM       : natural range 0 to 7 := 4     -- Image will be scaled to ZOOM
  65       );
  66
  67   port(
  68     video_clock  : in  std_logic;
  69     reset_n      : in  std_logic;                     -- reset
  70
  71
  72     ---------------------------------------------------------------------------
  73     -- Ports of RGB frame memory
  74     ---------------------------------------------------------------------------
  75     rgb_rd_addr   : out unsigned(ADDR_WIDTH-1 downto 0);
  76     rgb_rd_data   : in  signed(DATA_WIDTH-1 downto 0);
  77
  78     ---------------------------------------------------------------------------
  79     -- Port of RGB frame memory control access
  80     ---------------------------------------------------------------------------
  81     can_read_mem  : in  std_logic;
  82
  83     video_width   : in  unsigned(11 downto 0);
  84     video_height  : in  unsigned(11 downto 0);
  85
  86     red          : out std_logic_vector(7 downto 0);  -- red component
  87     green        : out std_logic_vector(7 downto 0);  -- green component
  88     blue         : out std_logic_vector(7 downto 0);  -- blue component
  89     line_pixel   : out std_logic_vector(9 downto 0);  -- compute line
  90     column_pixel : out std_logic_vector(9 downto 0);  -- compute column
  91     m1, m2       : out std_logic;                     -- select dac mode
  92     blank_n      : out std_logic;                     -- dac command
  93     sync_n       : out std_logic;                     -- dac command
  94     sync_t       : out std_logic;                     -- dac command
  95     video_clk    : out std_logic;                     -- dac command
  96     vga_vs       : out std_logic;                     -- vertical sync
  97     vga_hs       : out std_logic                      -- horizontal sync
  98     );
  99
 100   end component;
 101
 102   component YCbCr2RGB
 103     generic (
 104       DEPTH      : natural := 8192;       -- RGB MEMORY DEPTH
 105       ADDR_WIDTH : natural := 13;         -- RGB MEMORY ADDRESS WIDTH
 106       DATA_WIDTH : natural := 24;         -- RGB MEMORY DATA WIDTH
 107       ZOOM       : natural range 0 to 7 := 4     -- Image will be scaled to ZOOM
 108       );
 109
 110     port (
 111       Clk           : in std_logic;
 112       reset_n       : in std_logic;
 113
 114       ---------------------------------------------------------------------------
 115       -- Ports of Handshake
 116       ---------------------------------------------------------------------------
 117       in_request    : out std_logic;
 118       in_valid      : in  std_logic;
 119       in_data       : in  signed(31 downto 0);
 120
 121       ---------------------------------------------------------------------------
 122       -- Ports of RGB frame memory
 123       ---------------------------------------------------------------------------
 124       rgb_rd_addr   : in unsigned(ADDR_WIDTH-1 downto 0);
 125       rgb_rd_data   : out signed(DATA_WIDTH-1 downto 0);
 126
 127       ---------------------------------------------------------------------------
 128       -- Port of RGB frame memory control access
 129       ---------------------------------------------------------------------------
 130       can_read_mem  : out std_logic
 131       );
 132   end component;
 133
 134   component ReconRefFrames
 135     port (Clk,
 136           Reset_n       : in  std_logic;
 137
 138           in_request    : out std_logic;
 139           in_valid      : in  std_logic;
 140           in_data       : in  signed(31 downto 0);
 141
 142           out_requested : in  std_logic;
 143           out_valid     : out std_logic;
 144           out_data      : out signed(31 downto 0)
 145           );
 146
 147   end component;
 148
 149   constant ZOOM : natural := 2;
 150
 151   signal s_line_pixel   : std_logic_vector(9 downto 0);  -- compute line
 152   signal s_column_pixel : std_logic_vector(9 downto 0);  -- compute column
 153
 154   signal out_conv_requested : std_logic;
 155   signal out_conv_valid     : std_logic;
 156   signal out_conv_data      : signed(31 downto 0);
 157
 158   signal in_rr_request    : std_logic;
 159   signal in_rr_valid      : std_logic;
 160   signal in_rr_data       : signed(31 downto 0);
 161
 162   signal out_rr_requested : std_logic;
 163   signal out_rr_valid     : std_logic;
 164   signal out_rr_data      : signed(31 downto 0);
 165
 166   type switch_state_t is (stt_switch1, stt_switch2, stt_switch3,
 167                           stt_switch4, stt_switch5);
 168   signal switch_state : switch_state_t;
 169   signal s_in_request : std_logic;
 170
 171   signal rgb_rd_addr   : unsigned(ADDR_WIDTH-1 downto 0);
 172   signal rgb_rd_data   : signed(DATA_WIDTH-1 downto 0);
 173
 174   signal video_width   : unsigned(11 downto 0);
 175   signal video_height  : unsigned(11 downto 0);
 176
 177   signal can_read_mem : std_logic;
 178
 179 begin  -- a_theora_hardware
 180
 181   interface_vga0: interface_vga
 182     generic map (
 183       DEPTH      => DEPTH,
 184       ADDR_WIDTH => ADDR_WIDTH,
 185       DATA_WIDTH => DATA_WIDTH,
 186       ZOOM       => ZOOM)
 187
 188     port map (
 189       video_clock  => clk_25Mhz,
 190       reset_n      => reset_n,
 191
 192       ---------------------------------------------------------------------------
 193       -- Ports of RGB frame memory
 194       ---------------------------------------------------------------------------
 195       rgb_rd_addr   => rgb_rd_addr,
 196       rgb_rd_data   => rgb_rd_data,
 197
 198       ---------------------------------------------------------------------------
 199       -- Port of RGB frame memory control access
 200       ---------------------------------------------------------------------------
 201       can_read_mem  => can_read_mem,
 202
 203       video_width   => video_width,
 204       video_height  => video_height,
 205
 206       ---------------------------------------------------------------------------
 207       -- Ports of video controller
 208       ---------------------------------------------------------------------------
 209       red          => red,
 210       green        => green,
 211       blue         => blue,
 212       line_pixel   => s_line_pixel,
 213       column_pixel => s_column_pixel,
 214       m1           => m1,
 215       m2           => m2,
 216       blank_n      => blank_n,
 217       sync_n       => sync_n,
 218       sync_t       => sync_t,
 219       video_clk    => video_clk,
 220       vga_vs       => vga_vs,
 221       vga_hs       => vga_hs
 222       );
 223
 224   YCbCr2RGB_0: YCbCr2RGB
 225     generic map (
 226       DEPTH      => DEPTH,
 227       ADDR_WIDTH => ADDR_WIDTH,
 228       DATA_WIDTH => DATA_WIDTH,
 229       ZOOM       => ZOOM)
 230     port map (
 231       Clk           => Clk,
 232       reset_n       => reset_n,
 233
 234       ---------------------------------------------------------------------------
 235       -- Ports of Handshake
 236       ---------------------------------------------------------------------------
 237       in_request    => out_conv_requested,
 238       in_valid      => out_conv_valid,
 239       in_data       => out_conv_data,
 240
 241       ---------------------------------------------------------------------------
 242       -- Ports of RGB frame memory
 243       ---------------------------------------------------------------------------
 244       rgb_rd_addr   => rgb_rd_addr,
 245       rgb_rd_data   => rgb_rd_data,
 246
 247       ---------------------------------------------------------------------------
 248       -- Port of RGB frame memory control access
 249       ---------------------------------------------------------------------------
 250       can_read_mem  => can_read_mem
 251       );
 252
 253   reconrefframes0: ReconRefFrames
 254     port map (
 255       Clk => clk,
 256       Reset_n       => reset_n,
 257
 258       in_request    => out_rr_requested,
 259       in_valid      => out_rr_valid,
 260       in_data       => out_rr_data,
 261
 262       out_requested => in_rr_request,
 263       out_valid     => in_rr_valid,
 264       out_data      => in_rr_data
 265       );
 266
 267   in_request <= s_in_request;
 268
 269   out_rr_valid <= in_valid;
 270
 271   out_rr_data <= in_data;
 272
 273   Mux_out_conv_valid: with switch_state select
 274     out_conv_valid <= in_valid when stt_switch3 | stt_switch4,
 275                       in_rr_valid when stt_switch5,
 276                       '0'      when others;
 277
 278
 279   Mux_out_conv_data: with switch_state select
 280     out_conv_data <= in_data when stt_switch3 | stt_switch4,
 281                      in_rr_data when stt_switch5,
 282                      (others => '0') when others;
 283
 284   out_valid <= clk_25Mhz when (unsigned(s_line_pixel) < video_height * ZOOM and
 285                                unsigned(s_column_pixel) < video_width * ZOOM) else
 286                '0';
 287
 288   line_pixel <= s_line_pixel;
 289   column_pixel <= s_column_pixel;
 290
 291
 292   SwitchSignalsIn: process (reset_n,
 293                             out_conv_requested, out_rr_requested,
 294                             switch_state)
 295   begin  -- process SwitchSignals
 296
 297     s_in_request <= '0';
 298     in_rr_request <= '0';
 299
 300     if (switch_state = stt_switch3 or  switch_state = stt_switch4) then
 301       in_rr_request <= '0';
 302       s_in_request <= out_rr_requested and out_conv_requested;
 303
 304     else
 305       in_rr_request <= out_conv_requested;
 306       s_in_request <= out_rr_requested;
 307
 308     end if;
 309
 310   end process SwitchSignalsIn;
 311
 312
 313
 314   -- purpose: Control the switch the interface_vga and ReconRefFrames ports' signals
 315   -- type   : sequential
 316   -- inputs : clk, reset_n
 317   SwitchSignalsControl: process (clk, reset_n)
 318   begin  -- process SwitchEntries
 319     if reset_n = '0' then               -- asynchronous reset (active low)
 320       switch_state <= stt_switch1;
 321
 322     elsif clk'event and clk = '1' then  -- rising clock edge
 323       if (s_in_request = '1' and in_valid = '1') then
 324         case switch_state is
 325           -- Ignore first data
 326           when stt_switch1 =>
 327             switch_state <= stt_switch2;
 328
 329           -- FrameSize
 330           when stt_switch2 =>
 331             switch_state <= stt_switch3;
 332
 333           -- Video Height
 334           when stt_switch3 =>
 335             switch_state <= stt_switch4;
 336             video_height <= unsigned(in_data(11 downto 0));
 337
 338           -- Video Width
 339           when stt_switch4 =>
 340             switch_state <= stt_switch5;
 341             video_width <= unsigned(in_data(11 downto 0));
 342
 343           -- Reconrefframes parameters
 344           when stt_switch5 =>
 345             switch_state <= stt_switch5;
 346         end case;
 347       end if;
 348     end if;
 349   end process SwitchSignalsControl;
 350
 351 end a_theora_hardware;