theora-fpga/theora_hardware/lflimits.vhd

   1 -------------------------------------------------------------------------------
   2 --  Description: This file implements a component that calculate
   3 --               the filtbounding on-the-fly.
   4 -------------------------------------------------------------------------------
   5
   6 library std;
   7 library ieee;
   8 use ieee.std_logic_1164.all;
   9 use ieee.numeric_std.all;
  10
  11 entity LFLimits is
  12
  13   port (
  14     parameter : in  unsigned(8 downto 0);
  15     FLimit    : in  signed(8 downto 0);
  16
  17     fbv_value : out signed(9 downto 0));
  18
  19 end LFLimits;
  20
  21 architecture a_LFLimits of LFLimits is
  22
  23 begin  -- a_LFLimits
  24
  25   fbv_value <=
  26     "0000000000"
  27          when ((parameter <= 256 - unsigned(2*('0' & FLimit))) or
  28                (parameter >= 256 + unsigned(2*('0' & FLimit)))) else
  29     ('0' & signed(parameter)) - "0100000000"
  30          when ((parameter > 256 - unsigned(FLimit)) and
  31                (parameter < 256 + unsigned(FLimit))) else
  32     resize(256 - 2*('0' & FLimit) - ('0' & signed(parameter)), 10)
  33          when ((parameter > 256 - unsigned(2*('0' & FLimit))) and
  34                (parameter <= 256 - unsigned(FLimit))) else
  35     resize(256 + 2*('0' & FLimit) -('0' & signed(parameter)), 10);
  36 end a_LFLimits;