theora-fpga/testbenchs/reconrefframes/dual_syncram.vhd

   1 -------------------------------------------------------------------------------
   2 --  Description: This file implements a dual-SRAM
   3 -------------------------------------------------------------------------------
   4
   5 library IEEE;
   6 use IEEE.std_logic_1164.all;
   7 use IEEE.numeric_std.all;
   8
   9
  10 -- This entity will infferr two identical block rams
  11 -- to permit two reads in the same clock cicle.
  12
  13 entity dual_syncram is
  14   generic (
  15     DEPTH : positive := 64;             -- How many slots
  16     DATA_WIDTH : positive := 16;        -- How many bits per slot
  17     ADDR_WIDTH : positive := 6          -- = ceil(log2(DEPTH))
  18     );
  19   port (
  20     clk : in std_logic;
  21     wr_e  : in std_logic;
  22     wr_addr : in unsigned(ADDR_WIDTH-1 downto 0);
  23     wr_data : in signed(DATA_WIDTH-1 downto 0);
  24     rd1_addr : in unsigned(ADDR_WIDTH-1 downto 0);
  25     rd1_data : out signed(DATA_WIDTH-1 downto 0);
  26     rd2_addr : in unsigned(ADDR_WIDTH-1 downto 0);
  27     rd2_data : out signed(DATA_WIDTH-1 downto 0)
  28     );
  29 end entity dual_syncram;
  30
  31 architecture rtl of dual_syncram is
  32
  33   type MEM_TYPE is array(0 to DEPTH-1) of
  34     signed(DATA_WIDTH-1 downto 0);
  35   signal memory : MEM_TYPE;
  36 begin
  37
  38   process( clk )
  39   begin
  40     if ( rising_edge(clk) ) then
  41       if ( wr_e = '1' ) then
  42         memory( to_integer(wr_addr) ) <= wr_data;
  43       end if;
  44       rd1_data <= memory( to_integer(rd1_addr) );
  45       rd2_data <= memory( to_integer(rd2_addr) );
  46     end if;
  47   end process;
  48
  49 end rtl;