include/asm-xtensa/system.h

   1 /*
   2  * include/asm-xtensa/system.h
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2001 - 2005 Tensilica Inc.
   9  */
  10
  11 #ifndef _XTENSA_SYSTEM_H
  12 #define _XTENSA_SYSTEM_H
  13
  14 #include <linux/stringify.h>
  15
  16 #include <asm/processor.h>
  17
  18 /* interrupt control */
  19
  20 #define local_save_flags(x)                                             \
  21         __asm__ __volatile__ ("rsr %0,"__stringify(PS) : "=a" (x));
  22 #define local_irq_restore(x)    do {                                    \
  23         __asm__ __volatile__ ("wsr %0, "__stringify(PS)" ; rsync"       \
  24                               :: "a" (x) : "memory"); } while(0);
  25 #define local_irq_save(x)       do {                                    \
  26         __asm__ __volatile__ ("rsil %0, "__stringify(LOCKLEVEL)         \
  27                               : "=a" (x) :: "memory");} while(0);
  28
  29 static inline void local_irq_disable(void)
  30 {
  31         unsigned long flags;
  32         __asm__ __volatile__ ("rsil %0, "__stringify(LOCKLEVEL)
  33                               : "=a" (flags) :: "memory");
  34 }
  35 static inline void local_irq_enable(void)
  36 {
  37         unsigned long flags;
  38         __asm__ __volatile__ ("rsil %0, 0" : "=a" (flags) :: "memory");
  39
  40 }
  41
  42 static inline int irqs_disabled(void)
  43 {
  44         unsigned long flags;
  45         local_save_flags(flags);
  46         return flags & 0xf;
  47 }
  48
  49 <<<<<<< HEAD:include/asm-xtensa/system.h
  50 #define RSR_CPENABLE(x) do {                                              \
  51         __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \
  52         } while(0);
  53 #define WSR_CPENABLE(x) do {                                              \
  54         __asm__ __volatile__("wsr %0," __stringify(CPENABLE)";rsync"      \
  55                              :: "a" (x));} while(0);
  56
  57 #define clear_cpenable() __clear_cpenable()
  58
  59 static inline void __clear_cpenable(void)
  60 {
  61 #if XCHAL_HAVE_CP
  62         unsigned long i = 0;
  63         WSR_CPENABLE(i);
  64 #endif
  65 }
  66
  67 static inline void enable_coprocessor(int i)
  68 {
  69 #if XCHAL_HAVE_CP
  70         int cp;
  71         RSR_CPENABLE(cp);
  72         cp |= 1 << i;
  73         WSR_CPENABLE(cp);
  74 #endif
  75 }
  76
  77 static inline void disable_coprocessor(int i)
  78 {
  79 #if XCHAL_HAVE_CP
  80         int cp;
  81         RSR_CPENABLE(cp);
  82         cp &= ~(1 << i);
  83         WSR_CPENABLE(cp);
  84 #endif
  85 }
  86 =======
  87 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/system.h
  88
  89 #define smp_read_barrier_depends() do { } while(0)
  90 #define read_barrier_depends() do { } while(0)
  91
  92 #define mb()  barrier()
  93 #define rmb() mb()
  94 #define wmb() mb()
  95
  96 #ifdef CONFIG_SMP
  97 #error smp_* not defined
  98 #else
  99 #define smp_mb()        barrier()
 100 #define smp_rmb()       barrier()
 101 #define smp_wmb()       barrier()
 102 #endif
 103
 104 #define set_mb(var, value)      do { var = value; mb(); } while (0)
 105
 106 #if !defined (__ASSEMBLY__)
 107
 108 /* * switch_to(n) should switch tasks to task nr n, first
 109  * checking that n isn't the current task, in which case it does nothing.
 110  */
 111 extern void *_switch_to(void *last, void *next);
 112
 113 #endif  /* __ASSEMBLY__ */
 114
 115 #define switch_to(prev,next,last)               \
 116 do {                                            \
 117 <<<<<<< HEAD:include/asm-xtensa/system.h
 118         clear_cpenable();                       \
 119 =======
 120 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/system.h
 121         (last) = _switch_to(prev, next);        \
 122 } while(0)
 123
 124 /*
 125  * cmpxchg
 126  */
 127
 128 static inline unsigned long
 129 __cmpxchg_u32(volatile int *p, int old, int new)
 130 {
 131   __asm__ __volatile__("rsil    a15, "__stringify(LOCKLEVEL)"\n\t"
 132                        "l32i    %0, %1, 0              \n\t"
 133                        "bne     %0, %2, 1f             \n\t"
 134                        "s32i    %3, %1, 0              \n\t"
 135                        "1:                             \n\t"
 136                        "wsr     a15, "__stringify(PS)" \n\t"
 137                        "rsync                          \n\t"
 138                        : "=&a" (old)
 139                        : "a" (p), "a" (old), "r" (new)
 140                        : "a15", "memory");
 141   return old;
 142 }
 143 /* This function doesn't exist, so you'll get a linker error
 144  * if something tries to do an invalid cmpxchg(). */
 145
 146 extern void __cmpxchg_called_with_bad_pointer(void);
 147
 148 static __inline__ unsigned long
 149 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 150 {
 151         switch (size) {
 152         case 4:  return __cmpxchg_u32(ptr, old, new);
 153         default: __cmpxchg_called_with_bad_pointer();
 154                  return old;
 155         }
 156 }
 157
 158 #define cmpxchg(ptr,o,n)                                                      \
 159         ({ __typeof__(*(ptr)) _o_ = (o);                                      \
 160            __typeof__(*(ptr)) _n_ = (n);                                      \
 161            (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,          \
 162                                         (unsigned long)_n_, sizeof (*(ptr))); \
 163         })
 164
 165 #include <asm-generic/cmpxchg-local.h>
 166
 167 static inline unsigned long __cmpxchg_local(volatile void *ptr,
 168                                       unsigned long old,
 169                                       unsigned long new, int size)
 170 {
 171         switch (size) {
 172         case 4:
 173                 return __cmpxchg_u32(ptr, old, new);
 174         default:
 175                 return __cmpxchg_local_generic(ptr, old, new, size);
 176         }
 177
 178         return old;
 179 }
 180
 181 /*
 182  * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
 183  * them available.
 184  */
 185 #define cmpxchg_local(ptr, o, n)                                               \
 186         ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
 187                         (unsigned long)(n), sizeof(*(ptr))))
 188 #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
 189
 190 /*
 191  * xchg_u32
 192  *
 193  * Note that a15 is used here because the register allocation
 194  * done by the compiler is not guaranteed and a window overflow
 195  * may not occur between the rsil and wsr instructions. By using
 196  * a15 in the rsil, the machine is guaranteed to be in a state
 197  * where no register reference will cause an overflow.
 198  */
 199
 200 static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
 201 {
 202   unsigned long tmp;
 203   __asm__ __volatile__("rsil    a15, "__stringify(LOCKLEVEL)"\n\t"
 204                        "l32i    %0, %1, 0              \n\t"
 205                        "s32i    %2, %1, 0              \n\t"
 206                        "wsr     a15, "__stringify(PS)" \n\t"
 207                        "rsync                          \n\t"
 208                        : "=&a" (tmp)
 209                        : "a" (m), "a" (val)
 210                        : "a15", "memory");
 211   return tmp;
 212 }
 213
 214 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 215
 216 /*
 217  * This only works if the compiler isn't horribly bad at optimizing.
 218  * gcc-2.5.8 reportedly can't handle this, but I define that one to
 219  * be dead anyway.
 220  */
 221
 222 extern void __xchg_called_with_bad_pointer(void);
 223
 224 static __inline__ unsigned long
 225 __xchg(unsigned long x, volatile void * ptr, int size)
 226 {
 227         switch (size) {
 228                 case 4:
 229                         return xchg_u32(ptr, x);
 230         }
 231         __xchg_called_with_bad_pointer();
 232         return x;
 233 }
 234
 235 extern void set_except_vector(int n, void *addr);
 236
 237 static inline void spill_registers(void)
 238 {
 239         unsigned int a0, ps;
 240
 241         __asm__ __volatile__ (
 242                 "movi   a14," __stringify (PS_EXCM_BIT) " | 1\n\t"
 243                 "mov    a12, a0\n\t"
 244                 "rsr    a13," __stringify(SAR) "\n\t"
 245                 "xsr    a14," __stringify(PS) "\n\t"
 246                 "movi   a0, _spill_registers\n\t"
 247                 "rsync\n\t"
 248                 "callx0 a0\n\t"
 249                 "mov    a0, a12\n\t"
 250                 "wsr    a13," __stringify(SAR) "\n\t"
 251                 "wsr    a14," __stringify(PS) "\n\t"
 252                 :: "a" (&a0), "a" (&ps)
 253 <<<<<<< HEAD:include/asm-xtensa/system.h
 254                 : "a2", "a3", "a12", "a13", "a14", "a15", "memory");
 255 =======
 256                 : "a2", "a3", "a4", "a7", "a11", "a12", "a13", "a14", "a15", "memory");
 257 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/system.h
 258 }
 259
 260 #define arch_align_stack(x) (x)
 261
 262 #endif  /* _XTENSA_SYSTEM_H */