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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / ssb / driver_chipcommon.c
blobedfd2e6ec56d83d85a1112c07e8f904372cb0f85
1 /*
2 * Sonics Silicon Backplane
3 * Broadcom ChipCommon core driver
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11 #include <linux/ssb/ssb.h>
12 #include <linux/ssb/ssb_regs.h>
13 #include <linux/pci.h>
14
15 #include "ssb_private.h"
16
17
18 /* Clock sources */
19 enum ssb_clksrc {
20 /* PCI clock */
21 SSB_CHIPCO_CLKSRC_PCI,
22 /* Crystal slow clock oscillator */
23 SSB_CHIPCO_CLKSRC_XTALOS,
24 /* Low power oscillator */
25 SSB_CHIPCO_CLKSRC_LOPWROS,
26 };
27
28
29 static inline u32 chipco_read32(struct ssb_chipcommon *cc,
30 u16 offset)
31 {
32 return ssb_read32(cc->dev, offset);
33 }
34
35 static inline void chipco_write32(struct ssb_chipcommon *cc,
36 u16 offset,
37 u32 value)
38 {
39 ssb_write32(cc->dev, offset, value);
40 }
41
42 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
43 static inline void chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
44 u32 mask, u32 value)
45 =======
46 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
47 u32 mask, u32 value)
48 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
49 {
50 value &= mask;
51 value |= chipco_read32(cc, offset) & ~mask;
52 chipco_write32(cc, offset, value);
53 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
54 =======
55
56 return value;
57 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
58 }
59
60 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
61 enum ssb_clkmode mode)
62 {
63 struct ssb_device *ccdev = cc->dev;
64 struct ssb_bus *bus;
65 u32 tmp;
66
67 if (!ccdev)
68 return;
69 bus = ccdev->bus;
70 /* chipcommon cores prior to rev6 don't support dynamic clock control */
71 if (ccdev->id.revision < 6)
72 return;
73 /* chipcommon cores rev10 are a whole new ball game */
74 if (ccdev->id.revision >= 10)
75 return;
76 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
77 return;
78
79 switch (mode) {
80 case SSB_CLKMODE_SLOW:
81 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
82 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
83 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
84 break;
85 case SSB_CLKMODE_FAST:
86 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
87 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
88 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
89 tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
90 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
91 break;
92 case SSB_CLKMODE_DYNAMIC:
93 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
94 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
95 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
96 tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
97 if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
98 tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
99 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
100
101 /* for dynamic control, we have to release our xtal_pu "force on" */
102 if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
103 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
104 break;
105 default:
106 SSB_WARN_ON(1);
107 }
108 }
109
110 /* Get the Slow Clock Source */
111 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
112 {
113 struct ssb_bus *bus = cc->dev->bus;
114 u32 uninitialized_var(tmp);
115
116 if (cc->dev->id.revision < 6) {
117 if (bus->bustype == SSB_BUSTYPE_SSB ||
118 bus->bustype == SSB_BUSTYPE_PCMCIA)
119 return SSB_CHIPCO_CLKSRC_XTALOS;
120 if (bus->bustype == SSB_BUSTYPE_PCI) {
121 pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
122 if (tmp & 0x10)
123 return SSB_CHIPCO_CLKSRC_PCI;
124 return SSB_CHIPCO_CLKSRC_XTALOS;
125 }
126 }
127 if (cc->dev->id.revision < 10) {
128 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
129 tmp &= 0x7;
130 if (tmp == 0)
131 return SSB_CHIPCO_CLKSRC_LOPWROS;
132 if (tmp == 1)
133 return SSB_CHIPCO_CLKSRC_XTALOS;
134 if (tmp == 2)
135 return SSB_CHIPCO_CLKSRC_PCI;
136 }
137
138 return SSB_CHIPCO_CLKSRC_XTALOS;
139 }
140
141 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
142 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
143 {
144 int uninitialized_var(limit);
145 enum ssb_clksrc clocksrc;
146 int divisor = 1;
147 u32 tmp;
148
149 clocksrc = chipco_pctl_get_slowclksrc(cc);
150 if (cc->dev->id.revision < 6) {
151 switch (clocksrc) {
152 case SSB_CHIPCO_CLKSRC_PCI:
153 divisor = 64;
154 break;
155 case SSB_CHIPCO_CLKSRC_XTALOS:
156 divisor = 32;
157 break;
158 default:
159 SSB_WARN_ON(1);
160 }
161 } else if (cc->dev->id.revision < 10) {
162 switch (clocksrc) {
163 case SSB_CHIPCO_CLKSRC_LOPWROS:
164 break;
165 case SSB_CHIPCO_CLKSRC_XTALOS:
166 case SSB_CHIPCO_CLKSRC_PCI:
167 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
168 divisor = (tmp >> 16) + 1;
169 divisor *= 4;
170 break;
171 }
172 } else {
173 tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
174 divisor = (tmp >> 16) + 1;
175 divisor *= 4;
176 }
177
178 switch (clocksrc) {
179 case SSB_CHIPCO_CLKSRC_LOPWROS:
180 if (get_max)
181 limit = 43000;
182 else
183 limit = 25000;
184 break;
185 case SSB_CHIPCO_CLKSRC_XTALOS:
186 if (get_max)
187 limit = 20200000;
188 else
189 limit = 19800000;
190 break;
191 case SSB_CHIPCO_CLKSRC_PCI:
192 if (get_max)
193 limit = 34000000;
194 else
195 limit = 25000000;
196 break;
197 }
198 limit /= divisor;
199
200 return limit;
201 }
202
203 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
204 {
205 struct ssb_bus *bus = cc->dev->bus;
206
207 if (bus->chip_id == 0x4321) {
208 if (bus->chip_rev == 0)
209 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
210 else if (bus->chip_rev == 1)
211 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
212 }
213
214 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
215 return;
216
217 if (cc->dev->id.revision >= 10) {
218 /* Set Idle Power clock rate to 1Mhz */
219 chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
220 (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
221 0x0000FFFF) | 0x00040000);
222 } else {
223 int maxfreq;
224
225 maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
226 chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
227 (maxfreq * 150 + 999999) / 1000000);
228 chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
229 (maxfreq * 15 + 999999) / 1000000);
230 }
231 }
232
233 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
234 {
235 struct ssb_bus *bus = cc->dev->bus;
236 int minfreq;
237 unsigned int tmp;
238 u32 pll_on_delay;
239
240 if (bus->bustype != SSB_BUSTYPE_PCI)
241 return;
242 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
243 return;
244
245 minfreq = chipco_pctl_clockfreqlimit(cc, 0);
246 pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
247 tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
248 SSB_WARN_ON(tmp & ~0xFFFF);
249
250 cc->fast_pwrup_delay = tmp;
251 }
252
253 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
254 {
255 if (!cc->dev)
256 return; /* We don't have a ChipCommon */
257 chipco_powercontrol_init(cc);
258 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
259 calc_fast_powerup_delay(cc);
260 }
261
262 void ssb_chipco_suspend(struct ssb_chipcommon *cc, pm_message_t state)
263 {
264 if (!cc->dev)
265 return;
266 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
267 }
268
269 void ssb_chipco_resume(struct ssb_chipcommon *cc)
270 {
271 if (!cc->dev)
272 return;
273 chipco_powercontrol_init(cc);
274 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
275 }
276
277 /* Get the processor clock */
278 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
279 u32 *plltype, u32 *n, u32 *m)
280 {
281 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
282 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
283 switch (*plltype) {
284 case SSB_PLLTYPE_2:
285 case SSB_PLLTYPE_4:
286 case SSB_PLLTYPE_6:
287 case SSB_PLLTYPE_7:
288 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
289 break;
290 case SSB_PLLTYPE_3:
291 /* 5350 uses m2 to control mips */
292 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
293 break;
294 default:
295 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
296 break;
297 }
298 }
299
300 /* Get the bus clock */
301 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
302 u32 *plltype, u32 *n, u32 *m)
303 {
304 *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
305 *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
306 switch (*plltype) {
307 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
308 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
309 break;
310 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
311 if (cc->dev->bus->chip_id != 0x5365) {
312 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
313 break;
314 }
315 /* Fallthough */
316 default:
317 *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
318 }
319 }
320
321 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
322 unsigned long ns)
323 {
324 struct ssb_device *dev = cc->dev;
325 struct ssb_bus *bus = dev->bus;
326 u32 tmp;
327
328 /* set register for external IO to control LED. */
329 chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
330 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
331 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */
332 tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */
333 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
334
335 /* Set timing for the flash */
336 tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */
337 tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */
338 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */
339 if ((bus->chip_id == 0x5365) ||
340 (dev->id.revision < 9))
341 chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
342 if ((bus->chip_id == 0x5365) ||
343 (dev->id.revision < 9) ||
344 ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
345 chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
346
347 if (bus->chip_id == 0x5350) {
348 /* Enable EXTIF */
349 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
350 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */
351 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
352 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */
353 chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
354 }
355 }
356
357 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
358 void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
359 {
360 /* instant NMI */
361 chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
362 }
363
364 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
365 {
366 return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
367 }
368
369 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
370 void ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
371 =======
372 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
373 {
374 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
375 }
376
377 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
378 {
379 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
380 }
381
382 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
383 {
384 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
385 }
386
387 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
388 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
389 {
390 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
391 chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
392 =======
393 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
394 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
395 }
396
397 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
398 void ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
399 =======
400 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
401 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
402 {
403 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
404 chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
405 =======
406 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
407 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
408 }
409
410 #ifdef CONFIG_SSB_SERIAL
411 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
412 struct ssb_serial_port *ports)
413 {
414 struct ssb_bus *bus = cc->dev->bus;
415 int nr_ports = 0;
416 u32 plltype;
417 unsigned int irq;
418 u32 baud_base, div;
419 u32 i, n;
420 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
421 =======
422 unsigned int ccrev = cc->dev->id.revision;
423 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
424
425 plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
426 irq = ssb_mips_irq(cc->dev);
427
428 if (plltype == SSB_PLLTYPE_1) {
429 /* PLL clock */
430 baud_base = ssb_calc_clock_rate(plltype,
431 chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
432 chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
433 div = 1;
434 } else {
435 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
436 if (cc->dev->id.revision >= 11) {
437 =======
438 if (ccrev == 20) {
439 /* BCM5354 uses constant 25MHz clock */
440 baud_base = 25000000;
441 div = 48;
442 /* Set the override bit so we don't divide it */
443 chipco_write32(cc, SSB_CHIPCO_CORECTL,
444 chipco_read32(cc, SSB_CHIPCO_CORECTL)
445 | SSB_CHIPCO_CORECTL_UARTCLK0);
446 } else if ((ccrev >= 11) && (ccrev != 15)) {
447 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
448 /* Fixed ALP clock */
449 baud_base = 20000000;
450 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
451 =======
452 if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
453 /* FIXME: baud_base is different for devices with a PMU */
454 SSB_WARN_ON(1);
455 }
456 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
457 div = 1;
458 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
459 =======
460 if (ccrev >= 21) {
461 /* Turn off UART clock before switching clocksource. */
462 chipco_write32(cc, SSB_CHIPCO_CORECTL,
463 chipco_read32(cc, SSB_CHIPCO_CORECTL)
464 & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
465 }
466 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
467 /* Set the override bit so we don't divide it */
468 chipco_write32(cc, SSB_CHIPCO_CORECTL,
469 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
470 SSB_CHIPCO_CORECTL_UARTCLK0);
471 } else if (cc->dev->id.revision >= 3) {
472 =======
473 chipco_read32(cc, SSB_CHIPCO_CORECTL)
474 | SSB_CHIPCO_CORECTL_UARTCLK0);
475 if (ccrev >= 21) {
476 /* Re-enable the UART clock. */
477 chipco_write32(cc, SSB_CHIPCO_CORECTL,
478 chipco_read32(cc, SSB_CHIPCO_CORECTL)
479 | SSB_CHIPCO_CORECTL_UARTCLKEN);
480 }
481 } else if (ccrev >= 3) {
482 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
483 /* Internal backplane clock */
484 baud_base = ssb_clockspeed(bus);
485 div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
486 & SSB_CHIPCO_CLKDIV_UART;
487 } else {
488 /* Fixed internal backplane clock */
489 baud_base = 88000000;
490 div = 48;
491 }
492
493 /* Clock source depends on strapping if UartClkOverride is unset */
494 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
495 if ((cc->dev->id.revision > 0) &&
496 =======
497 if ((ccrev > 0) &&
498 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
499 !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
500 if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
501 SSB_CHIPCO_CAP_UARTCLK_INT) {
502 /* Internal divided backplane clock */
503 baud_base /= div;
504 } else {
505 /* Assume external clock of 1.8432 MHz */
506 baud_base = 1843200;
507 }
508 }
509 }
510
511 /* Determine the registers of the UARTs */
512 n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
513 for (i = 0; i < n; i++) {
514 void __iomem *cc_mmio;
515 void __iomem *uart_regs;
516
517 cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
518 uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
519 /* Offset changed at after rev 0 */
520 <<<<<<< HEAD:drivers/ssb/driver_chipcommon.c
521 if (cc->dev->id.revision == 0)
522 =======
523 if (ccrev == 0)
524 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ssb/driver_chipcommon.c
525 uart_regs += (i * 8);
526 else
527 uart_regs += (i * 256);
528
529 nr_ports++;
530 ports[i].regs = uart_regs;
531 ports[i].irq = irq;
532 ports[i].baud_base = baud_base;
533 ports[i].reg_shift = 0;
534 }
535
536 return nr_ports;
537 }
538 #endif /* CONFIG_SSB_SERIAL */
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