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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / mfd / sm501.c
blob7f0f9b07deea282dcbc86573083ef9e9fcc689f9
1 /* linux/drivers/mfd/sm501.c
2 *
3 * Copyright (C) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * Vincent Sanders <vince@simtec.co.uk>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * SM501 MFD driver
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/list.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pci.h>
22
23 #include <linux/sm501.h>
24 #include <linux/sm501-regs.h>
25
26 #include <asm/io.h>
27
28 struct sm501_device {
29 struct list_head list;
30 struct platform_device pdev;
31 };
32
33 struct sm501_devdata {
34 spinlock_t reg_lock;
35 struct mutex clock_lock;
36 struct list_head devices;
37
38 struct device *dev;
39 struct resource *io_res;
40 struct resource *mem_res;
41 struct resource *regs_claim;
42 struct sm501_platdata *platdata;
43
44 unsigned int in_suspend;
45 unsigned long pm_misc;
46
47 int unit_power[20];
48 unsigned int pdev_id;
49 unsigned int irq;
50 void __iomem *regs;
51 <<<<<<< HEAD:drivers/mfd/sm501.c
52 =======
53 unsigned int rev;
54 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
55 };
56
57 #define MHZ (1000 * 1000)
58
59 #ifdef DEBUG
60 <<<<<<< HEAD:drivers/mfd/sm501.c
61 static const unsigned int misc_div[] = {
62 [0] = 1,
63 [1] = 2,
64 [2] = 4,
65 [3] = 8,
66 [4] = 16,
67 [5] = 32,
68 [6] = 64,
69 [7] = 128,
70 [8] = 3,
71 [9] = 6,
72 [10] = 12,
73 [11] = 24,
74 [12] = 48,
75 [13] = 96,
76 [14] = 192,
77 [15] = 384,
78 };
79
80 static const unsigned int px_div[] = {
81 =======
82 static const unsigned int div_tab[] = {
83 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
84 [0] = 1,
85 [1] = 2,
86 [2] = 4,
87 [3] = 8,
88 [4] = 16,
89 [5] = 32,
90 [6] = 64,
91 [7] = 128,
92 [8] = 3,
93 [9] = 6,
94 [10] = 12,
95 [11] = 24,
96 [12] = 48,
97 [13] = 96,
98 [14] = 192,
99 [15] = 384,
100 [16] = 5,
101 [17] = 10,
102 [18] = 20,
103 [19] = 40,
104 [20] = 80,
105 [21] = 160,
106 [22] = 320,
107 [23] = 604,
108 };
109
110 static unsigned long decode_div(unsigned long pll2, unsigned long val,
111 unsigned int lshft, unsigned int selbit,
112 <<<<<<< HEAD:drivers/mfd/sm501.c
113 unsigned long mask, const unsigned int *dtab)
114 =======
115 unsigned long mask)
116 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
117 {
118 if (val & selbit)
119 pll2 = 288 * MHZ;
120
121 <<<<<<< HEAD:drivers/mfd/sm501.c
122 return pll2 / dtab[(val >> lshft) & mask];
123 =======
124 return pll2 / div_tab[(val >> lshft) & mask];
125 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
126 }
127
128 #define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
129
130 /* sm501_dump_clk
131 *
132 * Print out the current clock configuration for the device
133 */
134
135 static void sm501_dump_clk(struct sm501_devdata *sm)
136 {
137 unsigned long misct = readl(sm->regs + SM501_MISC_TIMING);
138 unsigned long pm0 = readl(sm->regs + SM501_POWER_MODE_0_CLOCK);
139 unsigned long pm1 = readl(sm->regs + SM501_POWER_MODE_1_CLOCK);
140 unsigned long pmc = readl(sm->regs + SM501_POWER_MODE_CONTROL);
141 unsigned long sdclk0, sdclk1;
142 unsigned long pll2 = 0;
143
144 switch (misct & 0x30) {
145 case 0x00:
146 pll2 = 336 * MHZ;
147 break;
148 case 0x10:
149 pll2 = 288 * MHZ;
150 break;
151 case 0x20:
152 pll2 = 240 * MHZ;
153 break;
154 case 0x30:
155 pll2 = 192 * MHZ;
156 break;
157 }
158
159 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
160 <<<<<<< HEAD:drivers/mfd/sm501.c
161 sdclk0 /= misc_div[((misct >> 8) & 0xf)];
162 =======
163 sdclk0 /= div_tab[((misct >> 8) & 0xf)];
164 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
165
166 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
167 <<<<<<< HEAD:drivers/mfd/sm501.c
168 sdclk1 /= misc_div[((misct >> 16) & 0xf)];
169 =======
170 sdclk1 /= div_tab[((misct >> 16) & 0xf)];
171 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
172
173 dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
174 misct, pm0, pm1);
175
176 dev_dbg(sm->dev, "PLL2 = %ld.%ld MHz (%ld), SDCLK0=%08lx, SDCLK1=%08lx\n",
177 fmt_freq(pll2), sdclk0, sdclk1);
178
179 dev_dbg(sm->dev, "SDRAM: PM0=%ld, PM1=%ld\n", sdclk0, sdclk1);
180
181 dev_dbg(sm->dev, "PM0[%c]: "
182 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
183 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
184 (pmc & 3 ) == 0 ? '*' : '-',
185 <<<<<<< HEAD:drivers/mfd/sm501.c
186 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31, px_div)),
187 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15, misc_div)),
188 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15, misc_div)),
189 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15, misc_div)));
190 =======
191 fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
192 fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
193 fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),
194 fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));
195 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
196
197 dev_dbg(sm->dev, "PM1[%c]: "
198 "P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
199 "M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
200 (pmc & 3 ) == 1 ? '*' : '-',
201 <<<<<<< HEAD:drivers/mfd/sm501.c
202 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31, px_div)),
203 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15, misc_div)),
204 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15, misc_div)),
205 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15, misc_div)));
206 =======
207 fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
208 fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
209 fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),
210 fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));
211 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
212 }
213
214 static void sm501_dump_regs(struct sm501_devdata *sm)
215 {
216 void __iomem *regs = sm->regs;
217
218 dev_info(sm->dev, "System Control %08x\n",
219 readl(regs + SM501_SYSTEM_CONTROL));
220 dev_info(sm->dev, "Misc Control %08x\n",
221 readl(regs + SM501_MISC_CONTROL));
222 dev_info(sm->dev, "GPIO Control Low %08x\n",
223 readl(regs + SM501_GPIO31_0_CONTROL));
224 dev_info(sm->dev, "GPIO Control Hi %08x\n",
225 readl(regs + SM501_GPIO63_32_CONTROL));
226 dev_info(sm->dev, "DRAM Control %08x\n",
227 readl(regs + SM501_DRAM_CONTROL));
228 dev_info(sm->dev, "Arbitration Ctrl %08x\n",
229 readl(regs + SM501_ARBTRTN_CONTROL));
230 dev_info(sm->dev, "Misc Timing %08x\n",
231 readl(regs + SM501_MISC_TIMING));
232 }
233
234 static void sm501_dump_gate(struct sm501_devdata *sm)
235 {
236 dev_info(sm->dev, "CurrentGate %08x\n",
237 readl(sm->regs + SM501_CURRENT_GATE));
238 dev_info(sm->dev, "CurrentClock %08x\n",
239 readl(sm->regs + SM501_CURRENT_CLOCK));
240 dev_info(sm->dev, "PowerModeControl %08x\n",
241 readl(sm->regs + SM501_POWER_MODE_CONTROL));
242 }
243
244 #else
245 static inline void sm501_dump_gate(struct sm501_devdata *sm) { }
246 static inline void sm501_dump_regs(struct sm501_devdata *sm) { }
247 static inline void sm501_dump_clk(struct sm501_devdata *sm) { }
248 #endif
249
250 /* sm501_sync_regs
251 *
252 * ensure the
253 */
254
255 static void sm501_sync_regs(struct sm501_devdata *sm)
256 {
257 readl(sm->regs);
258 }
259
260 static inline void sm501_mdelay(struct sm501_devdata *sm, unsigned int delay)
261 {
262 /* during suspend/resume, we are currently not allowed to sleep,
263 * so change to using mdelay() instead of msleep() if we
264 * are in one of these paths */
265
266 if (sm->in_suspend)
267 mdelay(delay);
268 else
269 msleep(delay);
270 }
271
272 /* sm501_misc_control
273 *
274 * alters the miscellaneous control parameters
275 */
276
277 int sm501_misc_control(struct device *dev,
278 unsigned long set, unsigned long clear)
279 {
280 struct sm501_devdata *sm = dev_get_drvdata(dev);
281 unsigned long misc;
282 unsigned long save;
283 unsigned long to;
284
285 spin_lock_irqsave(&sm->reg_lock, save);
286
287 misc = readl(sm->regs + SM501_MISC_CONTROL);
288 to = (misc & ~clear) | set;
289
290 if (to != misc) {
291 writel(to, sm->regs + SM501_MISC_CONTROL);
292 sm501_sync_regs(sm);
293
294 dev_dbg(sm->dev, "MISC_CONTROL %08lx\n", misc);
295 }
296
297 spin_unlock_irqrestore(&sm->reg_lock, save);
298 return to;
299 }
300
301 EXPORT_SYMBOL_GPL(sm501_misc_control);
302
303 /* sm501_modify_reg
304 *
305 * Modify a register in the SM501 which may be shared with other
306 * drivers.
307 */
308
309 unsigned long sm501_modify_reg(struct device *dev,
310 unsigned long reg,
311 unsigned long set,
312 unsigned long clear)
313 {
314 struct sm501_devdata *sm = dev_get_drvdata(dev);
315 unsigned long data;
316 unsigned long save;
317
318 spin_lock_irqsave(&sm->reg_lock, save);
319
320 data = readl(sm->regs + reg);
321 data |= set;
322 data &= ~clear;
323
324 writel(data, sm->regs + reg);
325 sm501_sync_regs(sm);
326
327 spin_unlock_irqrestore(&sm->reg_lock, save);
328
329 return data;
330 }
331
332 EXPORT_SYMBOL_GPL(sm501_modify_reg);
333
334 unsigned long sm501_gpio_get(struct device *dev,
335 unsigned long gpio)
336 {
337 struct sm501_devdata *sm = dev_get_drvdata(dev);
338 unsigned long result;
339 unsigned long reg;
340
341 reg = (gpio > 32) ? SM501_GPIO_DATA_HIGH : SM501_GPIO_DATA_LOW;
342 result = readl(sm->regs + reg);
343
344 result >>= (gpio & 31);
345 return result & 1UL;
346 }
347
348 EXPORT_SYMBOL_GPL(sm501_gpio_get);
349
350 void sm501_gpio_set(struct device *dev,
351 unsigned long gpio,
352 unsigned int to,
353 unsigned int dir)
354 {
355 struct sm501_devdata *sm = dev_get_drvdata(dev);
356
357 unsigned long bit = 1 << (gpio & 31);
358 unsigned long base;
359 unsigned long save;
360 unsigned long val;
361
362 base = (gpio > 32) ? SM501_GPIO_DATA_HIGH : SM501_GPIO_DATA_LOW;
363 base += SM501_GPIO;
364
365 spin_lock_irqsave(&sm->reg_lock, save);
366
367 val = readl(sm->regs + base) & ~bit;
368 if (to)
369 val |= bit;
370 writel(val, sm->regs + base);
371
372 val = readl(sm->regs + SM501_GPIO_DDR_LOW) & ~bit;
373 if (dir)
374 val |= bit;
375
376 writel(val, sm->regs + SM501_GPIO_DDR_LOW);
377 sm501_sync_regs(sm);
378
379 spin_unlock_irqrestore(&sm->reg_lock, save);
380
381 }
382
383 EXPORT_SYMBOL_GPL(sm501_gpio_set);
384
385
386 /* sm501_unit_power
387 *
388 * alters the power active gate to set specific units on or off
389 */
390
391 int sm501_unit_power(struct device *dev, unsigned int unit, unsigned int to)
392 {
393 struct sm501_devdata *sm = dev_get_drvdata(dev);
394 unsigned long mode;
395 unsigned long gate;
396 unsigned long clock;
397
398 mutex_lock(&sm->clock_lock);
399
400 mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
401 gate = readl(sm->regs + SM501_CURRENT_GATE);
402 clock = readl(sm->regs + SM501_CURRENT_CLOCK);
403
404 mode &= 3; /* get current power mode */
405
406 if (unit >= ARRAY_SIZE(sm->unit_power)) {
407 dev_err(dev, "%s: bad unit %d\n", __FUNCTION__, unit);
408 goto already;
409 }
410
411 dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __FUNCTION__, unit,
412 sm->unit_power[unit], to);
413
414 if (to == 0 && sm->unit_power[unit] == 0) {
415 dev_err(sm->dev, "unit %d is already shutdown\n", unit);
416 goto already;
417 }
418
419 sm->unit_power[unit] += to ? 1 : -1;
420 to = sm->unit_power[unit] ? 1 : 0;
421
422 if (to) {
423 if (gate & (1 << unit))
424 goto already;
425 gate |= (1 << unit);
426 } else {
427 if (!(gate & (1 << unit)))
428 goto already;
429 gate &= ~(1 << unit);
430 }
431
432 switch (mode) {
433 case 1:
434 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
435 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
436 mode = 0;
437 break;
438 case 2:
439 case 0:
440 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
441 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
442 mode = 1;
443 break;
444
445 default:
446 return -1;
447 }
448
449 writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
450 sm501_sync_regs(sm);
451
452 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
453 gate, clock, mode);
454
455 sm501_mdelay(sm, 16);
456
457 already:
458 mutex_unlock(&sm->clock_lock);
459 return gate;
460 }
461
462 EXPORT_SYMBOL_GPL(sm501_unit_power);
463
464
465 /* Perform a rounded division. */
466 static long sm501fb_round_div(long num, long denom)
467 {
468 /* n / d + 1 / 2 = (2n + d) / 2d */
469 return (2 * num + denom) / (2 * denom);
470 }
471
472 /* clock value structure. */
473 struct sm501_clock {
474 unsigned long mclk;
475 int divider;
476 int shift;
477 <<<<<<< HEAD:drivers/mfd/sm501.c
478 =======
479 unsigned int m, n, k;
480 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
481 };
482
483 <<<<<<< HEAD:drivers/mfd/sm501.c
484 =======
485 /* sm501_calc_clock
486 *
487 * Calculates the nearest discrete clock frequency that
488 * can be achieved with the specified input clock.
489 * the maximum divisor is 3 or 5
490 */
491
492 static int sm501_calc_clock(unsigned long freq,
493 struct sm501_clock *clock,
494 int max_div,
495 unsigned long mclk,
496 long *best_diff)
497 {
498 int ret = 0;
499 int divider;
500 int shift;
501 long diff;
502
503 /* try dividers 1 and 3 for CRT and for panel,
504 try divider 5 for panel only.*/
505
506 for (divider = 1; divider <= max_div; divider += 2) {
507 /* try all 8 shift values.*/
508 for (shift = 0; shift < 8; shift++) {
509 /* Calculate difference to requested clock */
510 diff = sm501fb_round_div(mclk, divider << shift) - freq;
511 if (diff < 0)
512 diff = -diff;
513
514 /* If it is less than the current, use it */
515 if (diff < *best_diff) {
516 *best_diff = diff;
517
518 clock->mclk = mclk;
519 clock->divider = divider;
520 clock->shift = shift;
521 ret = 1;
522 }
523 }
524 }
525
526 return ret;
527 }
528
529 /* sm501_calc_pll
530 *
531 * Calculates the nearest discrete clock frequency that can be
532 * achieved using the programmable PLL.
533 * the maximum divisor is 3 or 5
534 */
535
536 static unsigned long sm501_calc_pll(unsigned long freq,
537 struct sm501_clock *clock,
538 int max_div)
539 {
540 unsigned long mclk;
541 unsigned int m, n, k;
542 long best_diff = 999999999;
543
544 /*
545 * The SM502 datasheet doesn't specify the min/max values for M and N.
546 * N = 1 at least doesn't work in practice.
547 */
548 for (m = 2; m <= 255; m++) {
549 for (n = 2; n <= 127; n++) {
550 for (k = 0; k <= 1; k++) {
551 mclk = (24000000UL * m / n) >> k;
552
553 if (sm501_calc_clock(freq, clock, max_div,
554 mclk, &best_diff)) {
555 clock->m = m;
556 clock->n = n;
557 clock->k = k;
558 }
559 }
560 }
561 }
562
563 /* Return best clock. */
564 return clock->mclk / (clock->divider << clock->shift);
565 }
566
567 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
568 /* sm501_select_clock
569 *
570 <<<<<<< HEAD:drivers/mfd/sm501.c
571 * selects nearest discrete clock frequency the SM501 can achive
572 =======
573 * Calculates the nearest discrete clock frequency that can be
574 * achieved using the 288MHz and 336MHz PLLs.
575 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
576 * the maximum divisor is 3 or 5
577 */
578 <<<<<<< HEAD:drivers/mfd/sm501.c
579 =======
580
581 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
582 static unsigned long sm501_select_clock(unsigned long freq,
583 struct sm501_clock *clock,
584 int max_div)
585 {
586 unsigned long mclk;
587 <<<<<<< HEAD:drivers/mfd/sm501.c
588 int divider;
589 int shift;
590 long diff;
591 =======
592 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
593 long best_diff = 999999999;
594
595 /* Try 288MHz and 336MHz clocks. */
596 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
597 <<<<<<< HEAD:drivers/mfd/sm501.c
598 /* try dividers 1 and 3 for CRT and for panel,
599 try divider 5 for panel only.*/
600
601 for (divider = 1; divider <= max_div; divider += 2) {
602 /* try all 8 shift values.*/
603 for (shift = 0; shift < 8; shift++) {
604 /* Calculate difference to requested clock */
605 diff = sm501fb_round_div(mclk, divider << shift) - freq;
606 if (diff < 0)
607 diff = -diff;
608
609 /* If it is less than the current, use it */
610 if (diff < best_diff) {
611 best_diff = diff;
612
613 clock->mclk = mclk;
614 clock->divider = divider;
615 clock->shift = shift;
616 }
617 }
618 }
619 =======
620 sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
621 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
622 }
623
624 /* Return best clock. */
625 return clock->mclk / (clock->divider << clock->shift);
626 }
627
628 /* sm501_set_clock
629 *
630 * set one of the four clock sources to the closest available frequency to
631 * the one specified
632 */
633
634 unsigned long sm501_set_clock(struct device *dev,
635 int clksrc,
636 unsigned long req_freq)
637 {
638 struct sm501_devdata *sm = dev_get_drvdata(dev);
639 unsigned long mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
640 unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE);
641 unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK);
642 unsigned char reg;
643 <<<<<<< HEAD:drivers/mfd/sm501.c
644 =======
645 unsigned int pll_reg = 0;
646 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
647 unsigned long sm501_freq; /* the actual frequency acheived */
648
649 struct sm501_clock to;
650
651 /* find achivable discrete frequency and setup register value
652 * accordingly, V2XCLK, MCLK and M1XCLK are the same P2XCLK
653 * has an extra bit for the divider */
654
655 switch (clksrc) {
656 case SM501_CLOCK_P2XCLK:
657 /* This clock is divided in half so to achive the
658 * requested frequency the value must be multiplied by
659 * 2. This clock also has an additional pre divisor */
660
661 <<<<<<< HEAD:drivers/mfd/sm501.c
662 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 5) / 2);
663 reg=to.shift & 0x07;/* bottom 3 bits are shift */
664 if (to.divider == 3)
665 reg |= 0x08; /* /3 divider required */
666 else if (to.divider == 5)
667 reg |= 0x10; /* /5 divider required */
668 if (to.mclk != 288000000)
669 reg |= 0x20; /* which mclk pll is source */
670 =======
671 if (sm->rev >= 0xC0) {
672 /* SM502 -> use the programmable PLL */
673 sm501_freq = (sm501_calc_pll(2 * req_freq,
674 &to, 5) / 2);
675 reg = to.shift & 0x07;/* bottom 3 bits are shift */
676 if (to.divider == 3)
677 reg |= 0x08; /* /3 divider required */
678 else if (to.divider == 5)
679 reg |= 0x10; /* /5 divider required */
680 reg |= 0x40; /* select the programmable PLL */
681 pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
682 } else {
683 sm501_freq = (sm501_select_clock(2 * req_freq,
684 &to, 5) / 2);
685 reg = to.shift & 0x07;/* bottom 3 bits are shift */
686 if (to.divider == 3)
687 reg |= 0x08; /* /3 divider required */
688 else if (to.divider == 5)
689 reg |= 0x10; /* /5 divider required */
690 if (to.mclk != 288000000)
691 reg |= 0x20; /* which mclk pll is source */
692 }
693 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
694 break;
695
696 case SM501_CLOCK_V2XCLK:
697 /* This clock is divided in half so to achive the
698 * requested frequency the value must be multiplied by 2. */
699
700 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
701 reg=to.shift & 0x07; /* bottom 3 bits are shift */
702 if (to.divider == 3)
703 reg |= 0x08; /* /3 divider required */
704 if (to.mclk != 288000000)
705 reg |= 0x10; /* which mclk pll is source */
706 break;
707
708 case SM501_CLOCK_MCLK:
709 case SM501_CLOCK_M1XCLK:
710 /* These clocks are the same and not further divided */
711
712 sm501_freq = sm501_select_clock( req_freq, &to, 3);
713 reg=to.shift & 0x07; /* bottom 3 bits are shift */
714 if (to.divider == 3)
715 reg |= 0x08; /* /3 divider required */
716 if (to.mclk != 288000000)
717 reg |= 0x10; /* which mclk pll is source */
718 break;
719
720 default:
721 return 0; /* this is bad */
722 }
723
724 mutex_lock(&sm->clock_lock);
725
726 mode = readl(sm->regs + SM501_POWER_MODE_CONTROL);
727 gate = readl(sm->regs + SM501_CURRENT_GATE);
728 clock = readl(sm->regs + SM501_CURRENT_CLOCK);
729
730 clock = clock & ~(0xFF << clksrc);
731 clock |= reg<<clksrc;
732
733 mode &= 3; /* find current mode */
734
735 switch (mode) {
736 case 1:
737 writel(gate, sm->regs + SM501_POWER_MODE_0_GATE);
738 writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
739 mode = 0;
740 break;
741 case 2:
742 case 0:
743 writel(gate, sm->regs + SM501_POWER_MODE_1_GATE);
744 writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
745 mode = 1;
746 break;
747
748 default:
749 mutex_unlock(&sm->clock_lock);
750 return -1;
751 }
752
753 writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
754 <<<<<<< HEAD:drivers/mfd/sm501.c
755 =======
756
757 if (pll_reg)
758 writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
759
760 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
761 sm501_sync_regs(sm);
762
763 dev_info(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
764 gate, clock, mode);
765
766 sm501_mdelay(sm, 16);
767 mutex_unlock(&sm->clock_lock);
768
769 sm501_dump_clk(sm);
770
771 return sm501_freq;
772 }
773
774 EXPORT_SYMBOL_GPL(sm501_set_clock);
775
776 /* sm501_find_clock
777 *
778 * finds the closest available frequency for a given clock
779 */
780
781 <<<<<<< HEAD:drivers/mfd/sm501.c
782 unsigned long sm501_find_clock(int clksrc,
783 =======
784 unsigned long sm501_find_clock(struct device *dev,
785 int clksrc,
786 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
787 unsigned long req_freq)
788 {
789 <<<<<<< HEAD:drivers/mfd/sm501.c
790 =======
791 struct sm501_devdata *sm = dev_get_drvdata(dev);
792 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
793 unsigned long sm501_freq; /* the frequency achiveable by the 501 */
794 struct sm501_clock to;
795
796 switch (clksrc) {
797 case SM501_CLOCK_P2XCLK:
798 <<<<<<< HEAD:drivers/mfd/sm501.c
799 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 5) / 2);
800 =======
801 if (sm->rev >= 0xC0) {
802 /* SM502 -> use the programmable PLL */
803 sm501_freq = (sm501_calc_pll(2 * req_freq,
804 &to, 5) / 2);
805 } else {
806 sm501_freq = (sm501_select_clock(2 * req_freq,
807 &to, 5) / 2);
808 }
809 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
810 break;
811
812 case SM501_CLOCK_V2XCLK:
813 sm501_freq = (sm501_select_clock(2 * req_freq, &to, 3) / 2);
814 break;
815
816 case SM501_CLOCK_MCLK:
817 case SM501_CLOCK_M1XCLK:
818 sm501_freq = sm501_select_clock(req_freq, &to, 3);
819 break;
820
821 default:
822 sm501_freq = 0; /* error */
823 }
824
825 return sm501_freq;
826 }
827
828 EXPORT_SYMBOL_GPL(sm501_find_clock);
829
830 static struct sm501_device *to_sm_device(struct platform_device *pdev)
831 {
832 return container_of(pdev, struct sm501_device, pdev);
833 }
834
835 /* sm501_device_release
836 *
837 * A release function for the platform devices we create to allow us to
838 * free any items we allocated
839 */
840
841 static void sm501_device_release(struct device *dev)
842 {
843 kfree(to_sm_device(to_platform_device(dev)));
844 }
845
846 /* sm501_create_subdev
847 *
848 * Create a skeleton platform device with resources for passing to a
849 * sub-driver
850 */
851
852 static struct platform_device *
853 sm501_create_subdev(struct sm501_devdata *sm,
854 char *name, unsigned int res_count)
855 {
856 struct sm501_device *smdev;
857
858 smdev = kzalloc(sizeof(struct sm501_device) +
859 sizeof(struct resource) * res_count, GFP_KERNEL);
860 if (!smdev)
861 return NULL;
862
863 smdev->pdev.dev.release = sm501_device_release;
864
865 smdev->pdev.name = name;
866 smdev->pdev.id = sm->pdev_id;
867 smdev->pdev.resource = (struct resource *)(smdev+1);
868 smdev->pdev.num_resources = res_count;
869
870 smdev->pdev.dev.parent = sm->dev;
871
872 return &smdev->pdev;
873 }
874
875 /* sm501_register_device
876 *
877 * Register a platform device created with sm501_create_subdev()
878 */
879
880 static int sm501_register_device(struct sm501_devdata *sm,
881 struct platform_device *pdev)
882 {
883 struct sm501_device *smdev = to_sm_device(pdev);
884 int ptr;
885 int ret;
886
887 for (ptr = 0; ptr < pdev->num_resources; ptr++) {
888 printk("%s[%d] flags %08lx: %08llx..%08llx\n",
889 pdev->name, ptr,
890 pdev->resource[ptr].flags,
891 (unsigned long long)pdev->resource[ptr].start,
892 (unsigned long long)pdev->resource[ptr].end);
893 }
894
895 ret = platform_device_register(pdev);
896
897 if (ret >= 0) {
898 dev_dbg(sm->dev, "registered %s\n", pdev->name);
899 list_add_tail(&smdev->list, &sm->devices);
900 } else
901 dev_err(sm->dev, "error registering %s (%d)\n",
902 pdev->name, ret);
903
904 return ret;
905 }
906
907 /* sm501_create_subio
908 *
909 * Fill in an IO resource for a sub device
910 */
911
912 static void sm501_create_subio(struct sm501_devdata *sm,
913 struct resource *res,
914 resource_size_t offs,
915 resource_size_t size)
916 {
917 res->flags = IORESOURCE_MEM;
918 res->parent = sm->io_res;
919 res->start = sm->io_res->start + offs;
920 res->end = res->start + size - 1;
921 }
922
923 /* sm501_create_mem
924 *
925 * Fill in an MEM resource for a sub device
926 */
927
928 static void sm501_create_mem(struct sm501_devdata *sm,
929 struct resource *res,
930 resource_size_t *offs,
931 resource_size_t size)
932 {
933 *offs -= size; /* adjust memory size */
934
935 res->flags = IORESOURCE_MEM;
936 res->parent = sm->mem_res;
937 res->start = sm->mem_res->start + *offs;
938 res->end = res->start + size - 1;
939 }
940
941 /* sm501_create_irq
942 *
943 * Fill in an IRQ resource for a sub device
944 */
945
946 static void sm501_create_irq(struct sm501_devdata *sm,
947 struct resource *res)
948 {
949 res->flags = IORESOURCE_IRQ;
950 res->parent = NULL;
951 res->start = res->end = sm->irq;
952 }
953
954 static int sm501_register_usbhost(struct sm501_devdata *sm,
955 resource_size_t *mem_avail)
956 {
957 struct platform_device *pdev;
958
959 pdev = sm501_create_subdev(sm, "sm501-usb", 3);
960 if (!pdev)
961 return -ENOMEM;
962
963 sm501_create_subio(sm, &pdev->resource[0], 0x40000, 0x20000);
964 sm501_create_mem(sm, &pdev->resource[1], mem_avail, 256*1024);
965 sm501_create_irq(sm, &pdev->resource[2]);
966
967 return sm501_register_device(sm, pdev);
968 }
969
970 static int sm501_register_display(struct sm501_devdata *sm,
971 resource_size_t *mem_avail)
972 {
973 struct platform_device *pdev;
974
975 pdev = sm501_create_subdev(sm, "sm501-fb", 4);
976 if (!pdev)
977 return -ENOMEM;
978
979 sm501_create_subio(sm, &pdev->resource[0], 0x80000, 0x10000);
980 sm501_create_subio(sm, &pdev->resource[1], 0x100000, 0x50000);
981 sm501_create_mem(sm, &pdev->resource[2], mem_avail, *mem_avail);
982 sm501_create_irq(sm, &pdev->resource[3]);
983
984 return sm501_register_device(sm, pdev);
985 }
986
987 /* sm501_dbg_regs
988 *
989 * Debug attribute to attach to parent device to show core registers
990 */
991
992 static ssize_t sm501_dbg_regs(struct device *dev,
993 struct device_attribute *attr, char *buff)
994 {
995 struct sm501_devdata *sm = dev_get_drvdata(dev) ;
996 unsigned int reg;
997 char *ptr = buff;
998 int ret;
999
1000 for (reg = 0x00; reg < 0x70; reg += 4) {
1001 ret = sprintf(ptr, "%08x = %08x\n",
1002 reg, readl(sm->regs + reg));
1003 ptr += ret;
1004 }
1005
1006 return ptr - buff;
1007 }
1008
1009
1010 static DEVICE_ATTR(dbg_regs, 0666, sm501_dbg_regs, NULL);
1011
1012 /* sm501_init_reg
1013 *
1014 * Helper function for the init code to setup a register
1015 *
1016 * clear the bits which are set in r->mask, and then set
1017 * the bits set in r->set.
1018 */
1019
1020 static inline void sm501_init_reg(struct sm501_devdata *sm,
1021 unsigned long reg,
1022 struct sm501_reg_init *r)
1023 {
1024 unsigned long tmp;
1025
1026 tmp = readl(sm->regs + reg);
1027 tmp &= ~r->mask;
1028 tmp |= r->set;
1029 writel(tmp, sm->regs + reg);
1030 }
1031
1032 /* sm501_init_regs
1033 *
1034 * Setup core register values
1035 */
1036
1037 static void sm501_init_regs(struct sm501_devdata *sm,
1038 struct sm501_initdata *init)
1039 {
1040 sm501_misc_control(sm->dev,
1041 init->misc_control.set,
1042 init->misc_control.mask);
1043
1044 sm501_init_reg(sm, SM501_MISC_TIMING, &init->misc_timing);
1045 sm501_init_reg(sm, SM501_GPIO31_0_CONTROL, &init->gpio_low);
1046 sm501_init_reg(sm, SM501_GPIO63_32_CONTROL, &init->gpio_high);
1047
1048 if (init->m1xclk) {
1049 dev_info(sm->dev, "setting M1XCLK to %ld\n", init->m1xclk);
1050 sm501_set_clock(sm->dev, SM501_CLOCK_M1XCLK, init->m1xclk);
1051 }
1052
1053 if (init->mclk) {
1054 dev_info(sm->dev, "setting MCLK to %ld\n", init->mclk);
1055 sm501_set_clock(sm->dev, SM501_CLOCK_MCLK, init->mclk);
1056 }
1057
1058 }
1059
1060 /* Check the PLL sources for the M1CLK and M1XCLK
1061 *
1062 * If the M1CLK and M1XCLKs are not sourced from the same PLL, then
1063 * there is a risk (see errata AB-5) that the SM501 will cease proper
1064 * function. If this happens, then it is likely the SM501 will
1065 * hang the system.
1066 */
1067
1068 static int sm501_check_clocks(struct sm501_devdata *sm)
1069 {
1070 unsigned long pwrmode = readl(sm->regs + SM501_CURRENT_CLOCK);
1071 unsigned long msrc = (pwrmode & SM501_POWERMODE_M_SRC);
1072 unsigned long m1src = (pwrmode & SM501_POWERMODE_M1_SRC);
1073
1074 return ((msrc == 0 && m1src != 0) || (msrc != 0 && m1src == 0));
1075 }
1076
1077 static unsigned int sm501_mem_local[] = {
1078 [0] = 4*1024*1024,
1079 [1] = 8*1024*1024,
1080 [2] = 16*1024*1024,
1081 [3] = 32*1024*1024,
1082 [4] = 64*1024*1024,
1083 [5] = 2*1024*1024,
1084 };
1085
1086 /* sm501_init_dev
1087 *
1088 * Common init code for an SM501
1089 */
1090
1091 static int sm501_init_dev(struct sm501_devdata *sm)
1092 {
1093 resource_size_t mem_avail;
1094 unsigned long dramctrl;
1095 unsigned long devid;
1096 int ret;
1097
1098 mutex_init(&sm->clock_lock);
1099 spin_lock_init(&sm->reg_lock);
1100
1101 INIT_LIST_HEAD(&sm->devices);
1102
1103 devid = readl(sm->regs + SM501_DEVICEID);
1104
1105 if ((devid & SM501_DEVICEID_IDMASK) != SM501_DEVICEID_SM501) {
1106 dev_err(sm->dev, "incorrect device id %08lx\n", devid);
1107 return -EINVAL;
1108 }
1109
1110 dramctrl = readl(sm->regs + SM501_DRAM_CONTROL);
1111 mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
1112
1113 dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
1114 sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
1115
1116 <<<<<<< HEAD:drivers/mfd/sm501.c
1117 =======
1118 sm->rev = devid & SM501_DEVICEID_REVMASK;
1119
1120 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/mfd/sm501.c
1121 sm501_dump_gate(sm);
1122
1123 ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
1124 if (ret)
1125 dev_err(sm->dev, "failed to create debug regs file\n");
1126
1127 sm501_dump_clk(sm);
1128
1129 /* check to see if we have some device initialisation */
1130
1131 if (sm->platdata) {
1132 struct sm501_platdata *pdata = sm->platdata;
1133
1134 if (pdata->init) {
1135 sm501_init_regs(sm, sm->platdata->init);
1136
1137 if (pdata->init->devices & SM501_USE_USB_HOST)
1138 sm501_register_usbhost(sm, &mem_avail);
1139 }
1140 }
1141
1142 ret = sm501_check_clocks(sm);
1143 if (ret) {
1144 dev_err(sm->dev, "M1X and M clocks sourced from different "
1145 "PLLs\n");
1146 return -EINVAL;
1147 }
1148
1149 /* always create a framebuffer */
1150 sm501_register_display(sm, &mem_avail);
1151
1152 return 0;
1153 }
1154
1155 static int sm501_plat_probe(struct platform_device *dev)
1156 {
1157 struct sm501_devdata *sm;
1158 int err;
1159
1160 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1161 if (sm == NULL) {
1162 dev_err(&dev->dev, "no memory for device data\n");
1163 err = -ENOMEM;
1164 goto err1;
1165 }
1166
1167 sm->dev = &dev->dev;
1168 sm->pdev_id = dev->id;
1169 sm->irq = platform_get_irq(dev, 0);
1170 sm->io_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
1171 sm->mem_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1172 sm->platdata = dev->dev.platform_data;
1173
1174 if (sm->irq < 0) {
1175 dev_err(&dev->dev, "failed to get irq resource\n");
1176 err = sm->irq;
1177 goto err_res;
1178 }
1179
1180 if (sm->io_res == NULL || sm->mem_res == NULL) {
1181 dev_err(&dev->dev, "failed to get IO resource\n");
1182 err = -ENOENT;
1183 goto err_res;
1184 }
1185
1186 sm->regs_claim = request_mem_region(sm->io_res->start,
1187 0x100, "sm501");
1188
1189 if (sm->regs_claim == NULL) {
1190 dev_err(&dev->dev, "cannot claim registers\n");
1191 err= -EBUSY;
1192 goto err_res;
1193 }
1194
1195 platform_set_drvdata(dev, sm);
1196
1197 sm->regs = ioremap(sm->io_res->start,
1198 (sm->io_res->end - sm->io_res->start) - 1);
1199
1200 if (sm->regs == NULL) {
1201 dev_err(&dev->dev, "cannot remap registers\n");
1202 err = -EIO;
1203 goto err_claim;
1204 }
1205
1206 return sm501_init_dev(sm);
1207
1208 err_claim:
1209 release_resource(sm->regs_claim);
1210 kfree(sm->regs_claim);
1211 err_res:
1212 kfree(sm);
1213 err1:
1214 return err;
1215
1216 }
1217
1218 #ifdef CONFIG_PM
1219 /* power management support */
1220
1221 static int sm501_plat_suspend(struct platform_device *pdev, pm_message_t state)
1222 {
1223 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1224
1225 sm->in_suspend = 1;
1226 sm->pm_misc = readl(sm->regs + SM501_MISC_CONTROL);
1227
1228 sm501_dump_regs(sm);
1229 return 0;
1230 }
1231
1232 static int sm501_plat_resume(struct platform_device *pdev)
1233 {
1234 struct sm501_devdata *sm = platform_get_drvdata(pdev);
1235
1236 sm501_dump_regs(sm);
1237 sm501_dump_gate(sm);
1238 sm501_dump_clk(sm);
1239
1240 /* check to see if we are in the same state as when suspended */
1241
1242 if (readl(sm->regs + SM501_MISC_CONTROL) != sm->pm_misc) {
1243 dev_info(sm->dev, "SM501_MISC_CONTROL changed over sleep\n");
1244 writel(sm->pm_misc, sm->regs + SM501_MISC_CONTROL);
1245
1246 /* our suspend causes the controller state to change,
1247 * either by something attempting setup, power loss,
1248 * or an external reset event on power change */
1249
1250 if (sm->platdata && sm->platdata->init) {
1251 sm501_init_regs(sm, sm->platdata->init);
1252 }
1253 }
1254
1255 /* dump our state from resume */
1256
1257 sm501_dump_regs(sm);
1258 sm501_dump_clk(sm);
1259
1260 sm->in_suspend = 0;
1261
1262 return 0;
1263 }
1264 #else
1265 #define sm501_plat_suspend NULL
1266 #define sm501_plat_resume NULL
1267 #endif
1268
1269 /* Initialisation data for PCI devices */
1270
1271 static struct sm501_initdata sm501_pci_initdata = {
1272 .gpio_high = {
1273 .set = 0x3F000000, /* 24bit panel */
1274 .mask = 0x0,
1275 },
1276 .misc_timing = {
1277 .set = 0x010100, /* SDRAM timing */
1278 .mask = 0x1F1F00,
1279 },
1280 .misc_control = {
1281 .set = SM501_MISC_PNL_24BIT,
1282 .mask = 0,
1283 },
1284
1285 .devices = SM501_USE_ALL,
1286
1287 /* Errata AB-3 says that 72MHz is the fastest available
1288 * for 33MHZ PCI with proper bus-mastering operation */
1289
1290 .mclk = 72 * MHZ,
1291 .m1xclk = 144 * MHZ,
1292 };
1293
1294 static struct sm501_platdata_fbsub sm501_pdata_fbsub = {
1295 .flags = (SM501FB_FLAG_USE_INIT_MODE |
1296 SM501FB_FLAG_USE_HWCURSOR |
1297 SM501FB_FLAG_USE_HWACCEL |
1298 SM501FB_FLAG_DISABLE_AT_EXIT),
1299 };
1300
1301 static struct sm501_platdata_fb sm501_fb_pdata = {
1302 .fb_route = SM501_FB_OWN,
1303 .fb_crt = &sm501_pdata_fbsub,
1304 .fb_pnl = &sm501_pdata_fbsub,
1305 };
1306
1307 static struct sm501_platdata sm501_pci_platdata = {
1308 .init = &sm501_pci_initdata,
1309 .fb = &sm501_fb_pdata,
1310 };
1311
1312 static int sm501_pci_probe(struct pci_dev *dev,
1313 const struct pci_device_id *id)
1314 {
1315 struct sm501_devdata *sm;
1316 int err;
1317
1318 sm = kzalloc(sizeof(struct sm501_devdata), GFP_KERNEL);
1319 if (sm == NULL) {
1320 dev_err(&dev->dev, "no memory for device data\n");
1321 err = -ENOMEM;
1322 goto err1;
1323 }
1324
1325 /* set a default set of platform data */
1326 dev->dev.platform_data = sm->platdata = &sm501_pci_platdata;
1327
1328 /* set a hopefully unique id for our child platform devices */
1329 sm->pdev_id = 32 + dev->devfn;
1330
1331 pci_set_drvdata(dev, sm);
1332
1333 err = pci_enable_device(dev);
1334 if (err) {
1335 dev_err(&dev->dev, "cannot enable device\n");
1336 goto err2;
1337 }
1338
1339 sm->dev = &dev->dev;
1340 sm->irq = dev->irq;
1341
1342 #ifdef __BIG_ENDIAN
1343 /* if the system is big-endian, we most probably have a
1344 * translation in the IO layer making the PCI bus little endian
1345 * so make the framebuffer swapped pixels */
1346
1347 sm501_fb_pdata.flags |= SM501_FBPD_SWAP_FB_ENDIAN;
1348 #endif
1349
1350 /* check our resources */
1351
1352 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) {
1353 dev_err(&dev->dev, "region #0 is not memory?\n");
1354 err = -EINVAL;
1355 goto err3;
1356 }
1357
1358 if (!(pci_resource_flags(dev, 1) & IORESOURCE_MEM)) {
1359 dev_err(&dev->dev, "region #1 is not memory?\n");
1360 err = -EINVAL;
1361 goto err3;
1362 }
1363
1364 /* make our resources ready for sharing */
1365
1366 sm->io_res = &dev->resource[1];
1367 sm->mem_res = &dev->resource[0];
1368
1369 sm->regs_claim = request_mem_region(sm->io_res->start,
1370 0x100, "sm501");
1371 if (sm->regs_claim == NULL) {
1372 dev_err(&dev->dev, "cannot claim registers\n");
1373 err= -EBUSY;
1374 goto err3;
1375 }
1376
1377 sm->regs = ioremap(pci_resource_start(dev, 1),
1378 pci_resource_len(dev, 1));
1379
1380 if (sm->regs == NULL) {
1381 dev_err(&dev->dev, "cannot remap registers\n");
1382 err = -EIO;
1383 goto err4;
1384 }
1385
1386 sm501_init_dev(sm);
1387 return 0;
1388
1389 err4:
1390 release_resource(sm->regs_claim);
1391 kfree(sm->regs_claim);
1392 err3:
1393 pci_disable_device(dev);
1394 err2:
1395 pci_set_drvdata(dev, NULL);
1396 kfree(sm);
1397 err1:
1398 return err;
1399 }
1400
1401 static void sm501_remove_sub(struct sm501_devdata *sm,
1402 struct sm501_device *smdev)
1403 {
1404 list_del(&smdev->list);
1405 platform_device_unregister(&smdev->pdev);
1406 }
1407
1408 static void sm501_dev_remove(struct sm501_devdata *sm)
1409 {
1410 struct sm501_device *smdev, *tmp;
1411
1412 list_for_each_entry_safe(smdev, tmp, &sm->devices, list)
1413 sm501_remove_sub(sm, smdev);
1414
1415 device_remove_file(sm->dev, &dev_attr_dbg_regs);
1416 }
1417
1418 static void sm501_pci_remove(struct pci_dev *dev)
1419 {
1420 struct sm501_devdata *sm = pci_get_drvdata(dev);
1421
1422 sm501_dev_remove(sm);
1423 iounmap(sm->regs);
1424
1425 release_resource(sm->regs_claim);
1426 kfree(sm->regs_claim);
1427
1428 pci_set_drvdata(dev, NULL);
1429 pci_disable_device(dev);
1430 }
1431
1432 static int sm501_plat_remove(struct platform_device *dev)
1433 {
1434 struct sm501_devdata *sm = platform_get_drvdata(dev);
1435
1436 sm501_dev_remove(sm);
1437 iounmap(sm->regs);
1438
1439 release_resource(sm->regs_claim);
1440 kfree(sm->regs_claim);
1441
1442 return 0;
1443 }
1444
1445 static struct pci_device_id sm501_pci_tbl[] = {
1446 { 0x126f, 0x0501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
1447 { 0, },
1448 };
1449
1450 MODULE_DEVICE_TABLE(pci, sm501_pci_tbl);
1451
1452 static struct pci_driver sm501_pci_drv = {
1453 .name = "sm501",
1454 .id_table = sm501_pci_tbl,
1455 .probe = sm501_pci_probe,
1456 .remove = sm501_pci_remove,
1457 };
1458
1459 static struct platform_driver sm501_plat_drv = {
1460 .driver = {
1461 .name = "sm501",
1462 .owner = THIS_MODULE,
1463 },
1464 .probe = sm501_plat_probe,
1465 .remove = sm501_plat_remove,
1466 .suspend = sm501_plat_suspend,
1467 .resume = sm501_plat_resume,
1468 };
1469
1470 static int __init sm501_base_init(void)
1471 {
1472 platform_driver_register(&sm501_plat_drv);
1473 return pci_register_driver(&sm501_pci_drv);
1474 }
1475
1476 static void __exit sm501_base_exit(void)
1477 {
1478 platform_driver_unregister(&sm501_plat_drv);
1479 pci_unregister_driver(&sm501_pci_drv);
1480 }
1481
1482 module_init(sm501_base_init);
1483 module_exit(sm501_base_exit);
1484
1485 MODULE_DESCRIPTION("SM501 Core Driver");
1486 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Vincent Sanders");
1487 MODULE_LICENSE("GPL v2");
WRT350N Kernel Patches