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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / dma / iop-adma.c
blobc920e1ce8d4d9596dd107afdc1d807783e94e602
1 /*
2 * offload engine driver for the Intel Xscale series of i/o processors
3 * Copyright © 2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20 /*
21 * This driver supports the asynchrounous DMA copy and RAID engines available
22 * on the Intel Xscale(R) family of I/O Processors (IOP 32x, 33x, 134x)
23 */
24
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/async_tx.h>
28 #include <linux/delay.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/spinlock.h>
31 #include <linux/interrupt.h>
32 #include <linux/platform_device.h>
33 #include <linux/memory.h>
34 #include <linux/ioport.h>
35
36 #include <asm/arch/adma.h>
37
38 #define to_iop_adma_chan(chan) container_of(chan, struct iop_adma_chan, common)
39 #define to_iop_adma_device(dev) \
40 container_of(dev, struct iop_adma_device, common)
41 #define tx_to_iop_adma_slot(tx) \
42 container_of(tx, struct iop_adma_desc_slot, async_tx)
43
44 /**
45 * iop_adma_free_slots - flags descriptor slots for reuse
46 * @slot: Slot to free
47 * Caller must hold &iop_chan->lock while calling this function
48 */
49 static void iop_adma_free_slots(struct iop_adma_desc_slot *slot)
50 {
51 int stride = slot->slots_per_op;
52
53 while (stride--) {
54 slot->slots_per_op = 0;
55 slot = list_entry(slot->slot_node.next,
56 struct iop_adma_desc_slot,
57 slot_node);
58 }
59 }
60
61 static dma_cookie_t
62 iop_adma_run_tx_complete_actions(struct iop_adma_desc_slot *desc,
63 struct iop_adma_chan *iop_chan, dma_cookie_t cookie)
64 {
65 BUG_ON(desc->async_tx.cookie < 0);
66 spin_lock_bh(&desc->async_tx.lock);
67 if (desc->async_tx.cookie > 0) {
68 cookie = desc->async_tx.cookie;
69 desc->async_tx.cookie = 0;
70
71 /* call the callback (must not sleep or submit new
72 * operations to this channel)
73 */
74 if (desc->async_tx.callback)
75 desc->async_tx.callback(
76 desc->async_tx.callback_param);
77
78 /* unmap dma addresses
79 * (unmap_single vs unmap_page?)
80 */
81 if (desc->group_head && desc->unmap_len) {
82 struct iop_adma_desc_slot *unmap = desc->group_head;
83 struct device *dev =
84 &iop_chan->device->pdev->dev;
85 u32 len = unmap->unmap_len;
86 u32 src_cnt = unmap->unmap_src_cnt;
87 dma_addr_t addr = iop_desc_get_dest_addr(unmap,
88 iop_chan);
89
90 dma_unmap_page(dev, addr, len, DMA_FROM_DEVICE);
91 while (src_cnt--) {
92 addr = iop_desc_get_src_addr(unmap,
93 iop_chan,
94 src_cnt);
95 dma_unmap_page(dev, addr, len,
96 DMA_TO_DEVICE);
97 }
98 desc->group_head = NULL;
99 }
100 }
101
102 /* run dependent operations */
103 async_tx_run_dependencies(&desc->async_tx);
104 spin_unlock_bh(&desc->async_tx.lock);
105
106 return cookie;
107 }
108
109 static int
110 iop_adma_clean_slot(struct iop_adma_desc_slot *desc,
111 struct iop_adma_chan *iop_chan)
112 {
113 /* the client is allowed to attach dependent operations
114 * until 'ack' is set
115 */
116 if (!desc->async_tx.ack)
117 return 0;
118
119 /* leave the last descriptor in the chain
120 * so we can append to it
121 */
122 if (desc->chain_node.next == &iop_chan->chain)
123 return 1;
124
125 dev_dbg(iop_chan->device->common.dev,
126 "\tfree slot: %d slots_per_op: %d\n",
127 desc->idx, desc->slots_per_op);
128
129 list_del(&desc->chain_node);
130 iop_adma_free_slots(desc);
131
132 return 0;
133 }
134
135 static void __iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
136 {
137 struct iop_adma_desc_slot *iter, *_iter, *grp_start = NULL;
138 dma_cookie_t cookie = 0;
139 u32 current_desc = iop_chan_get_current_descriptor(iop_chan);
140 int busy = iop_chan_is_busy(iop_chan);
141 int seen_current = 0, slot_cnt = 0, slots_per_op = 0;
142
143 <<<<<<< HEAD:drivers/dma/iop-adma.c
144 dev_dbg(iop_chan->device->common.dev, "%s\n", __FUNCTION__);
145 =======
146 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
147 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
148 /* free completed slots from the chain starting with
149 * the oldest descriptor
150 */
151 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
152 chain_node) {
153 pr_debug("\tcookie: %d slot: %d busy: %d "
154 "this_desc: %#x next_desc: %#x ack: %d\n",
155 iter->async_tx.cookie, iter->idx, busy,
156 iter->async_tx.phys, iop_desc_get_next_desc(iter),
157 iter->async_tx.ack);
158 prefetch(_iter);
159 prefetch(&_iter->async_tx);
160
161 /* do not advance past the current descriptor loaded into the
162 * hardware channel, subsequent descriptors are either in
163 * process or have not been submitted
164 */
165 if (seen_current)
166 break;
167
168 /* stop the search if we reach the current descriptor and the
169 * channel is busy, or if it appears that the current descriptor
170 * needs to be re-read (i.e. has been appended to)
171 */
172 if (iter->async_tx.phys == current_desc) {
173 BUG_ON(seen_current++);
174 if (busy || iop_desc_get_next_desc(iter))
175 break;
176 }
177
178 /* detect the start of a group transaction */
179 if (!slot_cnt && !slots_per_op) {
180 slot_cnt = iter->slot_cnt;
181 slots_per_op = iter->slots_per_op;
182 if (slot_cnt <= slots_per_op) {
183 slot_cnt = 0;
184 slots_per_op = 0;
185 }
186 }
187
188 if (slot_cnt) {
189 pr_debug("\tgroup++\n");
190 if (!grp_start)
191 grp_start = iter;
192 slot_cnt -= slots_per_op;
193 }
194
195 /* all the members of a group are complete */
196 if (slots_per_op != 0 && slot_cnt == 0) {
197 struct iop_adma_desc_slot *grp_iter, *_grp_iter;
198 int end_of_chain = 0;
199 pr_debug("\tgroup end\n");
200
201 /* collect the total results */
202 if (grp_start->xor_check_result) {
203 u32 zero_sum_result = 0;
204 slot_cnt = grp_start->slot_cnt;
205 grp_iter = grp_start;
206
207 list_for_each_entry_from(grp_iter,
208 &iop_chan->chain, chain_node) {
209 zero_sum_result |=
210 iop_desc_get_zero_result(grp_iter);
211 pr_debug("\titer%d result: %d\n",
212 grp_iter->idx, zero_sum_result);
213 slot_cnt -= slots_per_op;
214 if (slot_cnt == 0)
215 break;
216 }
217 pr_debug("\tgrp_start->xor_check_result: %p\n",
218 grp_start->xor_check_result);
219 *grp_start->xor_check_result = zero_sum_result;
220 }
221
222 /* clean up the group */
223 slot_cnt = grp_start->slot_cnt;
224 grp_iter = grp_start;
225 list_for_each_entry_safe_from(grp_iter, _grp_iter,
226 &iop_chan->chain, chain_node) {
227 cookie = iop_adma_run_tx_complete_actions(
228 grp_iter, iop_chan, cookie);
229
230 slot_cnt -= slots_per_op;
231 end_of_chain = iop_adma_clean_slot(grp_iter,
232 iop_chan);
233
234 if (slot_cnt == 0 || end_of_chain)
235 break;
236 }
237
238 /* the group should be complete at this point */
239 BUG_ON(slot_cnt);
240
241 slots_per_op = 0;
242 grp_start = NULL;
243 if (end_of_chain)
244 break;
245 else
246 continue;
247 } else if (slots_per_op) /* wait for group completion */
248 continue;
249
250 /* write back zero sum results (single descriptor case) */
251 if (iter->xor_check_result && iter->async_tx.cookie)
252 *iter->xor_check_result =
253 iop_desc_get_zero_result(iter);
254
255 cookie = iop_adma_run_tx_complete_actions(
256 iter, iop_chan, cookie);
257
258 if (iop_adma_clean_slot(iter, iop_chan))
259 break;
260 }
261
262 BUG_ON(!seen_current);
263
264 iop_chan_idle(busy, iop_chan);
265
266 if (cookie > 0) {
267 iop_chan->completed_cookie = cookie;
268 pr_debug("\tcompleted cookie %d\n", cookie);
269 }
270 }
271
272 static void
273 iop_adma_slot_cleanup(struct iop_adma_chan *iop_chan)
274 {
275 spin_lock_bh(&iop_chan->lock);
276 __iop_adma_slot_cleanup(iop_chan);
277 spin_unlock_bh(&iop_chan->lock);
278 }
279
280 static void iop_adma_tasklet(unsigned long data)
281 {
282 struct iop_adma_chan *chan = (struct iop_adma_chan *) data;
283 __iop_adma_slot_cleanup(chan);
284 }
285
286 static struct iop_adma_desc_slot *
287 iop_adma_alloc_slots(struct iop_adma_chan *iop_chan, int num_slots,
288 int slots_per_op)
289 {
290 struct iop_adma_desc_slot *iter, *_iter, *alloc_start = NULL;
291 LIST_HEAD(chain);
292 int slots_found, retry = 0;
293
294 /* start search from the last allocated descrtiptor
295 * if a contiguous allocation can not be found start searching
296 * from the beginning of the list
297 */
298 retry:
299 slots_found = 0;
300 if (retry == 0)
301 iter = iop_chan->last_used;
302 else
303 iter = list_entry(&iop_chan->all_slots,
304 struct iop_adma_desc_slot,
305 slot_node);
306
307 list_for_each_entry_safe_continue(
308 iter, _iter, &iop_chan->all_slots, slot_node) {
309 prefetch(_iter);
310 prefetch(&_iter->async_tx);
311 if (iter->slots_per_op) {
312 /* give up after finding the first busy slot
313 * on the second pass through the list
314 */
315 if (retry)
316 break;
317
318 slots_found = 0;
319 continue;
320 }
321
322 /* start the allocation if the slot is correctly aligned */
323 if (!slots_found++) {
324 if (iop_desc_is_aligned(iter, slots_per_op))
325 alloc_start = iter;
326 else {
327 slots_found = 0;
328 continue;
329 }
330 }
331
332 if (slots_found == num_slots) {
333 struct iop_adma_desc_slot *alloc_tail = NULL;
334 struct iop_adma_desc_slot *last_used = NULL;
335 iter = alloc_start;
336 while (num_slots) {
337 int i;
338 dev_dbg(iop_chan->device->common.dev,
339 "allocated slot: %d "
340 "(desc %p phys: %#x) slots_per_op %d\n",
341 iter->idx, iter->hw_desc,
342 iter->async_tx.phys, slots_per_op);
343
344 /* pre-ack all but the last descriptor */
345 if (num_slots != slots_per_op)
346 iter->async_tx.ack = 1;
347 else
348 iter->async_tx.ack = 0;
349
350 list_add_tail(&iter->chain_node, &chain);
351 alloc_tail = iter;
352 iter->async_tx.cookie = 0;
353 iter->slot_cnt = num_slots;
354 iter->xor_check_result = NULL;
355 for (i = 0; i < slots_per_op; i++) {
356 iter->slots_per_op = slots_per_op - i;
357 last_used = iter;
358 iter = list_entry(iter->slot_node.next,
359 struct iop_adma_desc_slot,
360 slot_node);
361 }
362 num_slots -= slots_per_op;
363 }
364 alloc_tail->group_head = alloc_start;
365 alloc_tail->async_tx.cookie = -EBUSY;
366 list_splice(&chain, &alloc_tail->async_tx.tx_list);
367 iop_chan->last_used = last_used;
368 iop_desc_clear_next_desc(alloc_start);
369 iop_desc_clear_next_desc(alloc_tail);
370 return alloc_tail;
371 }
372 }
373 if (!retry++)
374 goto retry;
375
376 /* try to free some slots if the allocation fails */
377 tasklet_schedule(&iop_chan->irq_tasklet);
378
379 return NULL;
380 }
381
382 static dma_cookie_t
383 iop_desc_assign_cookie(struct iop_adma_chan *iop_chan,
384 struct iop_adma_desc_slot *desc)
385 {
386 dma_cookie_t cookie = iop_chan->common.cookie;
387 cookie++;
388 if (cookie < 0)
389 cookie = 1;
390 iop_chan->common.cookie = desc->async_tx.cookie = cookie;
391 return cookie;
392 }
393
394 static void iop_adma_check_threshold(struct iop_adma_chan *iop_chan)
395 {
396 dev_dbg(iop_chan->device->common.dev, "pending: %d\n",
397 iop_chan->pending);
398
399 if (iop_chan->pending >= IOP_ADMA_THRESHOLD) {
400 iop_chan->pending = 0;
401 iop_chan_append(iop_chan);
402 }
403 }
404
405 static dma_cookie_t
406 iop_adma_tx_submit(struct dma_async_tx_descriptor *tx)
407 {
408 struct iop_adma_desc_slot *sw_desc = tx_to_iop_adma_slot(tx);
409 struct iop_adma_chan *iop_chan = to_iop_adma_chan(tx->chan);
410 struct iop_adma_desc_slot *grp_start, *old_chain_tail;
411 int slot_cnt;
412 int slots_per_op;
413 dma_cookie_t cookie;
414
415 grp_start = sw_desc->group_head;
416 slot_cnt = grp_start->slot_cnt;
417 slots_per_op = grp_start->slots_per_op;
418
419 spin_lock_bh(&iop_chan->lock);
420 cookie = iop_desc_assign_cookie(iop_chan, sw_desc);
421
422 old_chain_tail = list_entry(iop_chan->chain.prev,
423 struct iop_adma_desc_slot, chain_node);
424 list_splice_init(&sw_desc->async_tx.tx_list,
425 &old_chain_tail->chain_node);
426
427 /* fix up the hardware chain */
428 iop_desc_set_next_desc(old_chain_tail, grp_start->async_tx.phys);
429
430 /* 1/ don't add pre-chained descriptors
431 * 2/ dummy read to flush next_desc write
432 */
433 BUG_ON(iop_desc_get_next_desc(sw_desc));
434
435 /* increment the pending count by the number of slots
436 * memcpy operations have a 1:1 (slot:operation) relation
437 * other operations are heavier and will pop the threshold
438 * more often.
439 */
440 iop_chan->pending += slot_cnt;
441 iop_adma_check_threshold(iop_chan);
442 spin_unlock_bh(&iop_chan->lock);
443
444 dev_dbg(iop_chan->device->common.dev, "%s cookie: %d slot: %d\n",
445 <<<<<<< HEAD:drivers/dma/iop-adma.c
446 __FUNCTION__, sw_desc->async_tx.cookie, sw_desc->idx);
447 =======
448 __func__, sw_desc->async_tx.cookie, sw_desc->idx);
449 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
450
451 return cookie;
452 }
453
454 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan);
455 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan);
456
457 /* returns the number of allocated descriptors */
458 static int iop_adma_alloc_chan_resources(struct dma_chan *chan)
459 {
460 char *hw_desc;
461 int idx;
462 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
463 struct iop_adma_desc_slot *slot = NULL;
464 int init = iop_chan->slots_allocated ? 0 : 1;
465 struct iop_adma_platform_data *plat_data =
466 iop_chan->device->pdev->dev.platform_data;
467 int num_descs_in_pool = plat_data->pool_size/IOP_ADMA_SLOT_SIZE;
468
469 /* Allocate descriptor slots */
470 do {
471 idx = iop_chan->slots_allocated;
472 if (idx == num_descs_in_pool)
473 break;
474
475 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
476 if (!slot) {
477 printk(KERN_INFO "IOP ADMA Channel only initialized"
478 " %d descriptor slots", idx);
479 break;
480 }
481 hw_desc = (char *) iop_chan->device->dma_desc_pool_virt;
482 slot->hw_desc = (void *) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
483
484 dma_async_tx_descriptor_init(&slot->async_tx, chan);
485 slot->async_tx.tx_submit = iop_adma_tx_submit;
486 INIT_LIST_HEAD(&slot->chain_node);
487 INIT_LIST_HEAD(&slot->slot_node);
488 INIT_LIST_HEAD(&slot->async_tx.tx_list);
489 hw_desc = (char *) iop_chan->device->dma_desc_pool;
490 slot->async_tx.phys =
491 (dma_addr_t) &hw_desc[idx * IOP_ADMA_SLOT_SIZE];
492 slot->idx = idx;
493
494 spin_lock_bh(&iop_chan->lock);
495 iop_chan->slots_allocated++;
496 list_add_tail(&slot->slot_node, &iop_chan->all_slots);
497 spin_unlock_bh(&iop_chan->lock);
498 } while (iop_chan->slots_allocated < num_descs_in_pool);
499
500 if (idx && !iop_chan->last_used)
501 iop_chan->last_used = list_entry(iop_chan->all_slots.next,
502 struct iop_adma_desc_slot,
503 slot_node);
504
505 dev_dbg(iop_chan->device->common.dev,
506 "allocated %d descriptor slots last_used: %p\n",
507 iop_chan->slots_allocated, iop_chan->last_used);
508
509 /* initialize the channel and the chain with a null operation */
510 if (init) {
511 if (dma_has_cap(DMA_MEMCPY,
512 iop_chan->device->common.cap_mask))
513 iop_chan_start_null_memcpy(iop_chan);
514 else if (dma_has_cap(DMA_XOR,
515 iop_chan->device->common.cap_mask))
516 iop_chan_start_null_xor(iop_chan);
517 else
518 BUG();
519 }
520
521 return (idx > 0) ? idx : -ENOMEM;
522 }
523
524 static struct dma_async_tx_descriptor *
525 iop_adma_prep_dma_interrupt(struct dma_chan *chan)
526 {
527 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
528 struct iop_adma_desc_slot *sw_desc, *grp_start;
529 int slot_cnt, slots_per_op;
530
531 <<<<<<< HEAD:drivers/dma/iop-adma.c
532 dev_dbg(iop_chan->device->common.dev, "%s\n", __FUNCTION__);
533 =======
534 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
535 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
536
537 spin_lock_bh(&iop_chan->lock);
538 slot_cnt = iop_chan_interrupt_slot_count(&slots_per_op, iop_chan);
539 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
540 if (sw_desc) {
541 grp_start = sw_desc->group_head;
542 iop_desc_init_interrupt(grp_start, iop_chan);
543 grp_start->unmap_len = 0;
544 }
545 spin_unlock_bh(&iop_chan->lock);
546
547 return sw_desc ? &sw_desc->async_tx : NULL;
548 }
549
550 static struct dma_async_tx_descriptor *
551 iop_adma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dma_dest,
552 dma_addr_t dma_src, size_t len, unsigned long flags)
553 {
554 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
555 struct iop_adma_desc_slot *sw_desc, *grp_start;
556 int slot_cnt, slots_per_op;
557
558 if (unlikely(!len))
559 return NULL;
560 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
561
562 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
563 <<<<<<< HEAD:drivers/dma/iop-adma.c
564 __FUNCTION__, len);
565 =======
566 __func__, len);
567 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
568
569 spin_lock_bh(&iop_chan->lock);
570 slot_cnt = iop_chan_memcpy_slot_count(len, &slots_per_op);
571 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
572 if (sw_desc) {
573 grp_start = sw_desc->group_head;
574 iop_desc_init_memcpy(grp_start, flags);
575 iop_desc_set_byte_count(grp_start, iop_chan, len);
576 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
577 iop_desc_set_memcpy_src_addr(grp_start, dma_src);
578 sw_desc->unmap_src_cnt = 1;
579 sw_desc->unmap_len = len;
580 }
581 spin_unlock_bh(&iop_chan->lock);
582
583 return sw_desc ? &sw_desc->async_tx : NULL;
584 }
585
586 static struct dma_async_tx_descriptor *
587 iop_adma_prep_dma_memset(struct dma_chan *chan, dma_addr_t dma_dest,
588 int value, size_t len, unsigned long flags)
589 {
590 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
591 struct iop_adma_desc_slot *sw_desc, *grp_start;
592 int slot_cnt, slots_per_op;
593
594 if (unlikely(!len))
595 return NULL;
596 BUG_ON(unlikely(len > IOP_ADMA_MAX_BYTE_COUNT));
597
598 dev_dbg(iop_chan->device->common.dev, "%s len: %u\n",
599 <<<<<<< HEAD:drivers/dma/iop-adma.c
600 __FUNCTION__, len);
601 =======
602 __func__, len);
603 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
604
605 spin_lock_bh(&iop_chan->lock);
606 slot_cnt = iop_chan_memset_slot_count(len, &slots_per_op);
607 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
608 if (sw_desc) {
609 grp_start = sw_desc->group_head;
610 iop_desc_init_memset(grp_start, flags);
611 iop_desc_set_byte_count(grp_start, iop_chan, len);
612 iop_desc_set_block_fill_val(grp_start, value);
613 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
614 sw_desc->unmap_src_cnt = 1;
615 sw_desc->unmap_len = len;
616 }
617 spin_unlock_bh(&iop_chan->lock);
618
619 return sw_desc ? &sw_desc->async_tx : NULL;
620 }
621
622 static struct dma_async_tx_descriptor *
623 iop_adma_prep_dma_xor(struct dma_chan *chan, dma_addr_t dma_dest,
624 dma_addr_t *dma_src, unsigned int src_cnt, size_t len,
625 unsigned long flags)
626 {
627 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
628 struct iop_adma_desc_slot *sw_desc, *grp_start;
629 int slot_cnt, slots_per_op;
630
631 if (unlikely(!len))
632 return NULL;
633 BUG_ON(unlikely(len > IOP_ADMA_XOR_MAX_BYTE_COUNT));
634
635 dev_dbg(iop_chan->device->common.dev,
636 "%s src_cnt: %d len: %u flags: %lx\n",
637 <<<<<<< HEAD:drivers/dma/iop-adma.c
638 __FUNCTION__, src_cnt, len, flags);
639 =======
640 __func__, src_cnt, len, flags);
641 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
642
643 spin_lock_bh(&iop_chan->lock);
644 slot_cnt = iop_chan_xor_slot_count(len, src_cnt, &slots_per_op);
645 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
646 if (sw_desc) {
647 grp_start = sw_desc->group_head;
648 iop_desc_init_xor(grp_start, src_cnt, flags);
649 iop_desc_set_byte_count(grp_start, iop_chan, len);
650 iop_desc_set_dest_addr(grp_start, iop_chan, dma_dest);
651 sw_desc->unmap_src_cnt = src_cnt;
652 sw_desc->unmap_len = len;
653 while (src_cnt--)
654 iop_desc_set_xor_src_addr(grp_start, src_cnt,
655 dma_src[src_cnt]);
656 }
657 spin_unlock_bh(&iop_chan->lock);
658
659 return sw_desc ? &sw_desc->async_tx : NULL;
660 }
661
662 static struct dma_async_tx_descriptor *
663 iop_adma_prep_dma_zero_sum(struct dma_chan *chan, dma_addr_t *dma_src,
664 unsigned int src_cnt, size_t len, u32 *result,
665 unsigned long flags)
666 {
667 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
668 struct iop_adma_desc_slot *sw_desc, *grp_start;
669 int slot_cnt, slots_per_op;
670
671 if (unlikely(!len))
672 return NULL;
673
674 dev_dbg(iop_chan->device->common.dev, "%s src_cnt: %d len: %u\n",
675 <<<<<<< HEAD:drivers/dma/iop-adma.c
676 __FUNCTION__, src_cnt, len);
677 =======
678 __func__, src_cnt, len);
679 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
680
681 spin_lock_bh(&iop_chan->lock);
682 slot_cnt = iop_chan_zero_sum_slot_count(len, src_cnt, &slots_per_op);
683 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
684 if (sw_desc) {
685 grp_start = sw_desc->group_head;
686 iop_desc_init_zero_sum(grp_start, src_cnt, flags);
687 iop_desc_set_zero_sum_byte_count(grp_start, len);
688 grp_start->xor_check_result = result;
689 pr_debug("\t%s: grp_start->xor_check_result: %p\n",
690 <<<<<<< HEAD:drivers/dma/iop-adma.c
691 __FUNCTION__, grp_start->xor_check_result);
692 =======
693 __func__, grp_start->xor_check_result);
694 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
695 sw_desc->unmap_src_cnt = src_cnt;
696 sw_desc->unmap_len = len;
697 while (src_cnt--)
698 iop_desc_set_zero_sum_src_addr(grp_start, src_cnt,
699 dma_src[src_cnt]);
700 }
701 spin_unlock_bh(&iop_chan->lock);
702
703 return sw_desc ? &sw_desc->async_tx : NULL;
704 }
705
706 static void iop_adma_dependency_added(struct dma_chan *chan)
707 {
708 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
709 tasklet_schedule(&iop_chan->irq_tasklet);
710 }
711
712 static void iop_adma_free_chan_resources(struct dma_chan *chan)
713 {
714 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
715 struct iop_adma_desc_slot *iter, *_iter;
716 int in_use_descs = 0;
717
718 iop_adma_slot_cleanup(iop_chan);
719
720 spin_lock_bh(&iop_chan->lock);
721 list_for_each_entry_safe(iter, _iter, &iop_chan->chain,
722 chain_node) {
723 in_use_descs++;
724 list_del(&iter->chain_node);
725 }
726 list_for_each_entry_safe_reverse(
727 iter, _iter, &iop_chan->all_slots, slot_node) {
728 list_del(&iter->slot_node);
729 kfree(iter);
730 iop_chan->slots_allocated--;
731 }
732 iop_chan->last_used = NULL;
733
734 dev_dbg(iop_chan->device->common.dev, "%s slots_allocated %d\n",
735 <<<<<<< HEAD:drivers/dma/iop-adma.c
736 __FUNCTION__, iop_chan->slots_allocated);
737 =======
738 __func__, iop_chan->slots_allocated);
739 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
740 spin_unlock_bh(&iop_chan->lock);
741
742 /* one is ok since we left it on there on purpose */
743 if (in_use_descs > 1)
744 printk(KERN_ERR "IOP: Freeing %d in use descriptors!\n",
745 in_use_descs - 1);
746 }
747
748 /**
749 * iop_adma_is_complete - poll the status of an ADMA transaction
750 * @chan: ADMA channel handle
751 * @cookie: ADMA transaction identifier
752 */
753 static enum dma_status iop_adma_is_complete(struct dma_chan *chan,
754 dma_cookie_t cookie,
755 dma_cookie_t *done,
756 dma_cookie_t *used)
757 {
758 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
759 dma_cookie_t last_used;
760 dma_cookie_t last_complete;
761 enum dma_status ret;
762
763 last_used = chan->cookie;
764 last_complete = iop_chan->completed_cookie;
765
766 if (done)
767 *done = last_complete;
768 if (used)
769 *used = last_used;
770
771 ret = dma_async_is_complete(cookie, last_complete, last_used);
772 if (ret == DMA_SUCCESS)
773 return ret;
774
775 iop_adma_slot_cleanup(iop_chan);
776
777 last_used = chan->cookie;
778 last_complete = iop_chan->completed_cookie;
779
780 if (done)
781 *done = last_complete;
782 if (used)
783 *used = last_used;
784
785 return dma_async_is_complete(cookie, last_complete, last_used);
786 }
787
788 static irqreturn_t iop_adma_eot_handler(int irq, void *data)
789 {
790 struct iop_adma_chan *chan = data;
791
792 <<<<<<< HEAD:drivers/dma/iop-adma.c
793 dev_dbg(chan->device->common.dev, "%s\n", __FUNCTION__);
794 =======
795 dev_dbg(chan->device->common.dev, "%s\n", __func__);
796 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
797
798 tasklet_schedule(&chan->irq_tasklet);
799
800 iop_adma_device_clear_eot_status(chan);
801
802 return IRQ_HANDLED;
803 }
804
805 static irqreturn_t iop_adma_eoc_handler(int irq, void *data)
806 {
807 struct iop_adma_chan *chan = data;
808
809 <<<<<<< HEAD:drivers/dma/iop-adma.c
810 dev_dbg(chan->device->common.dev, "%s\n", __FUNCTION__);
811 =======
812 dev_dbg(chan->device->common.dev, "%s\n", __func__);
813 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
814
815 tasklet_schedule(&chan->irq_tasklet);
816
817 iop_adma_device_clear_eoc_status(chan);
818
819 return IRQ_HANDLED;
820 }
821
822 static irqreturn_t iop_adma_err_handler(int irq, void *data)
823 {
824 struct iop_adma_chan *chan = data;
825 unsigned long status = iop_chan_get_status(chan);
826
827 dev_printk(KERN_ERR, chan->device->common.dev,
828 "error ( %s%s%s%s%s%s%s)\n",
829 iop_is_err_int_parity(status, chan) ? "int_parity " : "",
830 iop_is_err_mcu_abort(status, chan) ? "mcu_abort " : "",
831 iop_is_err_int_tabort(status, chan) ? "int_tabort " : "",
832 iop_is_err_int_mabort(status, chan) ? "int_mabort " : "",
833 iop_is_err_pci_tabort(status, chan) ? "pci_tabort " : "",
834 iop_is_err_pci_mabort(status, chan) ? "pci_mabort " : "",
835 iop_is_err_split_tx(status, chan) ? "split_tx " : "");
836
837 iop_adma_device_clear_err_status(chan);
838
839 BUG();
840
841 return IRQ_HANDLED;
842 }
843
844 static void iop_adma_issue_pending(struct dma_chan *chan)
845 {
846 struct iop_adma_chan *iop_chan = to_iop_adma_chan(chan);
847
848 if (iop_chan->pending) {
849 iop_chan->pending = 0;
850 iop_chan_append(iop_chan);
851 }
852 }
853
854 /*
855 * Perform a transaction to verify the HW works.
856 */
857 #define IOP_ADMA_TEST_SIZE 2000
858
859 static int __devinit iop_adma_memcpy_self_test(struct iop_adma_device *device)
860 {
861 int i;
862 void *src, *dest;
863 dma_addr_t src_dma, dest_dma;
864 struct dma_chan *dma_chan;
865 dma_cookie_t cookie;
866 struct dma_async_tx_descriptor *tx;
867 int err = 0;
868 struct iop_adma_chan *iop_chan;
869
870 <<<<<<< HEAD:drivers/dma/iop-adma.c
871 dev_dbg(device->common.dev, "%s\n", __FUNCTION__);
872 =======
873 dev_dbg(device->common.dev, "%s\n", __func__);
874 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
875
876 src = kzalloc(sizeof(u8) * IOP_ADMA_TEST_SIZE, GFP_KERNEL);
877 if (!src)
878 return -ENOMEM;
879 dest = kzalloc(sizeof(u8) * IOP_ADMA_TEST_SIZE, GFP_KERNEL);
880 if (!dest) {
881 kfree(src);
882 return -ENOMEM;
883 }
884
885 /* Fill in src buffer */
886 for (i = 0; i < IOP_ADMA_TEST_SIZE; i++)
887 ((u8 *) src)[i] = (u8)i;
888
889 memset(dest, 0, IOP_ADMA_TEST_SIZE);
890
891 /* Start copy, using first DMA channel */
892 dma_chan = container_of(device->common.channels.next,
893 struct dma_chan,
894 device_node);
895 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
896 err = -ENODEV;
897 goto out;
898 }
899
900 dest_dma = dma_map_single(dma_chan->device->dev, dest,
901 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
902 src_dma = dma_map_single(dma_chan->device->dev, src,
903 IOP_ADMA_TEST_SIZE, DMA_TO_DEVICE);
904 tx = iop_adma_prep_dma_memcpy(dma_chan, dest_dma, src_dma,
905 IOP_ADMA_TEST_SIZE, 1);
906
907 cookie = iop_adma_tx_submit(tx);
908 iop_adma_issue_pending(dma_chan);
909 async_tx_ack(tx);
910 msleep(1);
911
912 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
913 DMA_SUCCESS) {
914 dev_printk(KERN_ERR, dma_chan->device->dev,
915 "Self-test copy timed out, disabling\n");
916 err = -ENODEV;
917 goto free_resources;
918 }
919
920 iop_chan = to_iop_adma_chan(dma_chan);
921 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
922 IOP_ADMA_TEST_SIZE, DMA_FROM_DEVICE);
923 if (memcmp(src, dest, IOP_ADMA_TEST_SIZE)) {
924 dev_printk(KERN_ERR, dma_chan->device->dev,
925 "Self-test copy failed compare, disabling\n");
926 err = -ENODEV;
927 goto free_resources;
928 }
929
930 free_resources:
931 iop_adma_free_chan_resources(dma_chan);
932 out:
933 kfree(src);
934 kfree(dest);
935 return err;
936 }
937
938 #define IOP_ADMA_NUM_SRC_TEST 4 /* must be <= 15 */
939 static int __devinit
940 iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device)
941 {
942 int i, src_idx;
943 struct page *dest;
944 struct page *xor_srcs[IOP_ADMA_NUM_SRC_TEST];
945 struct page *zero_sum_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
946 dma_addr_t dma_srcs[IOP_ADMA_NUM_SRC_TEST + 1];
947 dma_addr_t dma_addr, dest_dma;
948 struct dma_async_tx_descriptor *tx;
949 struct dma_chan *dma_chan;
950 dma_cookie_t cookie;
951 u8 cmp_byte = 0;
952 u32 cmp_word;
953 u32 zero_sum_result;
954 int err = 0;
955 struct iop_adma_chan *iop_chan;
956
957 <<<<<<< HEAD:drivers/dma/iop-adma.c
958 dev_dbg(device->common.dev, "%s\n", __FUNCTION__);
959 =======
960 dev_dbg(device->common.dev, "%s\n", __func__);
961 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
962
963 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
964 xor_srcs[src_idx] = alloc_page(GFP_KERNEL);
965 if (!xor_srcs[src_idx])
966 while (src_idx--) {
967 __free_page(xor_srcs[src_idx]);
968 return -ENOMEM;
969 }
970 }
971
972 dest = alloc_page(GFP_KERNEL);
973 if (!dest)
974 while (src_idx--) {
975 __free_page(xor_srcs[src_idx]);
976 return -ENOMEM;
977 }
978
979 /* Fill in src buffers */
980 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) {
981 u8 *ptr = page_address(xor_srcs[src_idx]);
982 for (i = 0; i < PAGE_SIZE; i++)
983 ptr[i] = (1 << src_idx);
984 }
985
986 for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++)
987 cmp_byte ^= (u8) (1 << src_idx);
988
989 cmp_word = (cmp_byte << 24) | (cmp_byte << 16) |
990 (cmp_byte << 8) | cmp_byte;
991
992 memset(page_address(dest), 0, PAGE_SIZE);
993
994 dma_chan = container_of(device->common.channels.next,
995 struct dma_chan,
996 device_node);
997 if (iop_adma_alloc_chan_resources(dma_chan) < 1) {
998 err = -ENODEV;
999 goto out;
1000 }
1001
1002 /* test xor */
1003 dest_dma = dma_map_page(dma_chan->device->dev, dest, 0,
1004 PAGE_SIZE, DMA_FROM_DEVICE);
1005 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1006 dma_srcs[i] = dma_map_page(dma_chan->device->dev, xor_srcs[i],
1007 0, PAGE_SIZE, DMA_TO_DEVICE);
1008 tx = iop_adma_prep_dma_xor(dma_chan, dest_dma, dma_srcs,
1009 IOP_ADMA_NUM_SRC_TEST, PAGE_SIZE, 1);
1010
1011 cookie = iop_adma_tx_submit(tx);
1012 iop_adma_issue_pending(dma_chan);
1013 async_tx_ack(tx);
1014 msleep(8);
1015
1016 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) !=
1017 DMA_SUCCESS) {
1018 dev_printk(KERN_ERR, dma_chan->device->dev,
1019 "Self-test xor timed out, disabling\n");
1020 err = -ENODEV;
1021 goto free_resources;
1022 }
1023
1024 iop_chan = to_iop_adma_chan(dma_chan);
1025 dma_sync_single_for_cpu(&iop_chan->device->pdev->dev, dest_dma,
1026 PAGE_SIZE, DMA_FROM_DEVICE);
1027 for (i = 0; i < (PAGE_SIZE / sizeof(u32)); i++) {
1028 u32 *ptr = page_address(dest);
1029 if (ptr[i] != cmp_word) {
1030 dev_printk(KERN_ERR, dma_chan->device->dev,
1031 "Self-test xor failed compare, disabling\n");
1032 err = -ENODEV;
1033 goto free_resources;
1034 }
1035 }
1036 dma_sync_single_for_device(&iop_chan->device->pdev->dev, dest_dma,
1037 PAGE_SIZE, DMA_TO_DEVICE);
1038
1039 /* skip zero sum if the capability is not present */
1040 if (!dma_has_cap(DMA_ZERO_SUM, dma_chan->device->cap_mask))
1041 goto free_resources;
1042
1043 /* zero sum the sources with the destintation page */
1044 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST; i++)
1045 zero_sum_srcs[i] = xor_srcs[i];
1046 zero_sum_srcs[i] = dest;
1047
1048 zero_sum_result = 1;
1049
1050 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1051 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1052 zero_sum_srcs[i], 0, PAGE_SIZE,
1053 DMA_TO_DEVICE);
1054 tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1055 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1056 &zero_sum_result, 1);
1057
1058 cookie = iop_adma_tx_submit(tx);
1059 iop_adma_issue_pending(dma_chan);
1060 async_tx_ack(tx);
1061 msleep(8);
1062
1063 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1064 dev_printk(KERN_ERR, dma_chan->device->dev,
1065 "Self-test zero sum timed out, disabling\n");
1066 err = -ENODEV;
1067 goto free_resources;
1068 }
1069
1070 if (zero_sum_result != 0) {
1071 dev_printk(KERN_ERR, dma_chan->device->dev,
1072 "Self-test zero sum failed compare, disabling\n");
1073 err = -ENODEV;
1074 goto free_resources;
1075 }
1076
1077 /* test memset */
1078 dma_addr = dma_map_page(dma_chan->device->dev, dest, 0,
1079 PAGE_SIZE, DMA_FROM_DEVICE);
1080 tx = iop_adma_prep_dma_memset(dma_chan, dma_addr, 0, PAGE_SIZE, 1);
1081
1082 cookie = iop_adma_tx_submit(tx);
1083 iop_adma_issue_pending(dma_chan);
1084 async_tx_ack(tx);
1085 msleep(8);
1086
1087 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1088 dev_printk(KERN_ERR, dma_chan->device->dev,
1089 "Self-test memset timed out, disabling\n");
1090 err = -ENODEV;
1091 goto free_resources;
1092 }
1093
1094 for (i = 0; i < PAGE_SIZE/sizeof(u32); i++) {
1095 u32 *ptr = page_address(dest);
1096 if (ptr[i]) {
1097 dev_printk(KERN_ERR, dma_chan->device->dev,
1098 "Self-test memset failed compare, disabling\n");
1099 err = -ENODEV;
1100 goto free_resources;
1101 }
1102 }
1103
1104 /* test for non-zero parity sum */
1105 zero_sum_result = 0;
1106 for (i = 0; i < IOP_ADMA_NUM_SRC_TEST + 1; i++)
1107 dma_srcs[i] = dma_map_page(dma_chan->device->dev,
1108 zero_sum_srcs[i], 0, PAGE_SIZE,
1109 DMA_TO_DEVICE);
1110 tx = iop_adma_prep_dma_zero_sum(dma_chan, dma_srcs,
1111 IOP_ADMA_NUM_SRC_TEST + 1, PAGE_SIZE,
1112 &zero_sum_result, 1);
1113
1114 cookie = iop_adma_tx_submit(tx);
1115 iop_adma_issue_pending(dma_chan);
1116 async_tx_ack(tx);
1117 msleep(8);
1118
1119 if (iop_adma_is_complete(dma_chan, cookie, NULL, NULL) != DMA_SUCCESS) {
1120 dev_printk(KERN_ERR, dma_chan->device->dev,
1121 "Self-test non-zero sum timed out, disabling\n");
1122 err = -ENODEV;
1123 goto free_resources;
1124 }
1125
1126 if (zero_sum_result != 1) {
1127 dev_printk(KERN_ERR, dma_chan->device->dev,
1128 "Self-test non-zero sum failed compare, disabling\n");
1129 err = -ENODEV;
1130 goto free_resources;
1131 }
1132
1133 free_resources:
1134 iop_adma_free_chan_resources(dma_chan);
1135 out:
1136 src_idx = IOP_ADMA_NUM_SRC_TEST;
1137 while (src_idx--)
1138 __free_page(xor_srcs[src_idx]);
1139 __free_page(dest);
1140 return err;
1141 }
1142
1143 static int __devexit iop_adma_remove(struct platform_device *dev)
1144 {
1145 struct iop_adma_device *device = platform_get_drvdata(dev);
1146 struct dma_chan *chan, *_chan;
1147 struct iop_adma_chan *iop_chan;
1148 int i;
1149 struct iop_adma_platform_data *plat_data = dev->dev.platform_data;
1150
1151 dma_async_device_unregister(&device->common);
1152
1153 for (i = 0; i < 3; i++) {
1154 unsigned int irq;
1155 irq = platform_get_irq(dev, i);
1156 free_irq(irq, device);
1157 }
1158
1159 dma_free_coherent(&dev->dev, plat_data->pool_size,
1160 device->dma_desc_pool_virt, device->dma_desc_pool);
1161
1162 do {
1163 struct resource *res;
1164 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1165 release_mem_region(res->start, res->end - res->start);
1166 } while (0);
1167
1168 list_for_each_entry_safe(chan, _chan, &device->common.channels,
1169 device_node) {
1170 iop_chan = to_iop_adma_chan(chan);
1171 list_del(&chan->device_node);
1172 kfree(iop_chan);
1173 }
1174 kfree(device);
1175
1176 return 0;
1177 }
1178
1179 static int __devinit iop_adma_probe(struct platform_device *pdev)
1180 {
1181 struct resource *res;
1182 int ret = 0, i;
1183 struct iop_adma_device *adev;
1184 struct iop_adma_chan *iop_chan;
1185 struct dma_device *dma_dev;
1186 struct iop_adma_platform_data *plat_data = pdev->dev.platform_data;
1187
1188 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1189 if (!res)
1190 return -ENODEV;
1191
1192 if (!devm_request_mem_region(&pdev->dev, res->start,
1193 res->end - res->start, pdev->name))
1194 return -EBUSY;
1195
1196 adev = kzalloc(sizeof(*adev), GFP_KERNEL);
1197 if (!adev)
1198 return -ENOMEM;
1199 dma_dev = &adev->common;
1200
1201 /* allocate coherent memory for hardware descriptors
1202 * note: writecombine gives slightly better performance, but
1203 * requires that we explicitly flush the writes
1204 */
1205 if ((adev->dma_desc_pool_virt = dma_alloc_writecombine(&pdev->dev,
1206 plat_data->pool_size,
1207 &adev->dma_desc_pool,
1208 GFP_KERNEL)) == NULL) {
1209 ret = -ENOMEM;
1210 goto err_free_adev;
1211 }
1212
1213 dev_dbg(&pdev->dev, "%s: allocted descriptor pool virt %p phys %p\n",
1214 <<<<<<< HEAD:drivers/dma/iop-adma.c
1215 __FUNCTION__, adev->dma_desc_pool_virt,
1216 =======
1217 __func__, adev->dma_desc_pool_virt,
1218 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
1219 (void *) adev->dma_desc_pool);
1220
1221 adev->id = plat_data->hw_id;
1222
1223 /* discover transaction capabilites from the platform data */
1224 dma_dev->cap_mask = plat_data->cap_mask;
1225
1226 adev->pdev = pdev;
1227 platform_set_drvdata(pdev, adev);
1228
1229 INIT_LIST_HEAD(&dma_dev->channels);
1230
1231 /* set base routines */
1232 dma_dev->device_alloc_chan_resources = iop_adma_alloc_chan_resources;
1233 dma_dev->device_free_chan_resources = iop_adma_free_chan_resources;
1234 dma_dev->device_is_tx_complete = iop_adma_is_complete;
1235 dma_dev->device_issue_pending = iop_adma_issue_pending;
1236 dma_dev->device_dependency_added = iop_adma_dependency_added;
1237 dma_dev->dev = &pdev->dev;
1238
1239 /* set prep routines based on capability */
1240 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask))
1241 dma_dev->device_prep_dma_memcpy = iop_adma_prep_dma_memcpy;
1242 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask))
1243 dma_dev->device_prep_dma_memset = iop_adma_prep_dma_memset;
1244 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1245 dma_dev->max_xor = iop_adma_get_max_xor();
1246 dma_dev->device_prep_dma_xor = iop_adma_prep_dma_xor;
1247 }
1248 if (dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask))
1249 dma_dev->device_prep_dma_zero_sum =
1250 iop_adma_prep_dma_zero_sum;
1251 if (dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask))
1252 dma_dev->device_prep_dma_interrupt =
1253 iop_adma_prep_dma_interrupt;
1254
1255 iop_chan = kzalloc(sizeof(*iop_chan), GFP_KERNEL);
1256 if (!iop_chan) {
1257 ret = -ENOMEM;
1258 goto err_free_dma;
1259 }
1260 iop_chan->device = adev;
1261
1262 iop_chan->mmr_base = devm_ioremap(&pdev->dev, res->start,
1263 res->end - res->start);
1264 if (!iop_chan->mmr_base) {
1265 ret = -ENOMEM;
1266 goto err_free_iop_chan;
1267 }
1268 tasklet_init(&iop_chan->irq_tasklet, iop_adma_tasklet, (unsigned long)
1269 iop_chan);
1270
1271 /* clear errors before enabling interrupts */
1272 iop_adma_device_clear_err_status(iop_chan);
1273
1274 for (i = 0; i < 3; i++) {
1275 irq_handler_t handler[] = { iop_adma_eot_handler,
1276 iop_adma_eoc_handler,
1277 iop_adma_err_handler };
1278 int irq = platform_get_irq(pdev, i);
1279 if (irq < 0) {
1280 ret = -ENXIO;
1281 goto err_free_iop_chan;
1282 } else {
1283 ret = devm_request_irq(&pdev->dev, irq,
1284 handler[i], 0, pdev->name, iop_chan);
1285 if (ret)
1286 goto err_free_iop_chan;
1287 }
1288 }
1289
1290 spin_lock_init(&iop_chan->lock);
1291 init_timer(&iop_chan->cleanup_watchdog);
1292 iop_chan->cleanup_watchdog.data = (unsigned long) iop_chan;
1293 iop_chan->cleanup_watchdog.function = iop_adma_tasklet;
1294 INIT_LIST_HEAD(&iop_chan->chain);
1295 INIT_LIST_HEAD(&iop_chan->all_slots);
1296 INIT_RCU_HEAD(&iop_chan->common.rcu);
1297 iop_chan->common.device = dma_dev;
1298 list_add_tail(&iop_chan->common.device_node, &dma_dev->channels);
1299
1300 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1301 ret = iop_adma_memcpy_self_test(adev);
1302 dev_dbg(&pdev->dev, "memcpy self test returned %d\n", ret);
1303 if (ret)
1304 goto err_free_iop_chan;
1305 }
1306
1307 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask) ||
1308 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1309 ret = iop_adma_xor_zero_sum_self_test(adev);
1310 dev_dbg(&pdev->dev, "xor self test returned %d\n", ret);
1311 if (ret)
1312 goto err_free_iop_chan;
1313 }
1314
1315 dev_printk(KERN_INFO, &pdev->dev, "Intel(R) IOP: "
1316 "( %s%s%s%s%s%s%s%s%s%s)\n",
1317 dma_has_cap(DMA_PQ_XOR, dma_dev->cap_mask) ? "pq_xor " : "",
1318 dma_has_cap(DMA_PQ_UPDATE, dma_dev->cap_mask) ? "pq_update " : "",
1319 dma_has_cap(DMA_PQ_ZERO_SUM, dma_dev->cap_mask) ? "pq_zero_sum " : "",
1320 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "xor " : "",
1321 dma_has_cap(DMA_DUAL_XOR, dma_dev->cap_mask) ? "dual_xor " : "",
1322 dma_has_cap(DMA_ZERO_SUM, dma_dev->cap_mask) ? "xor_zero_sum " : "",
1323 dma_has_cap(DMA_MEMSET, dma_dev->cap_mask) ? "fill " : "",
1324 dma_has_cap(DMA_MEMCPY_CRC32C, dma_dev->cap_mask) ? "cpy+crc " : "",
1325 dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask) ? "cpy " : "",
1326 dma_has_cap(DMA_INTERRUPT, dma_dev->cap_mask) ? "intr " : "");
1327
1328 dma_async_device_register(dma_dev);
1329 goto out;
1330
1331 err_free_iop_chan:
1332 kfree(iop_chan);
1333 err_free_dma:
1334 dma_free_coherent(&adev->pdev->dev, plat_data->pool_size,
1335 adev->dma_desc_pool_virt, adev->dma_desc_pool);
1336 err_free_adev:
1337 kfree(adev);
1338 out:
1339 return ret;
1340 }
1341
1342 static void iop_chan_start_null_memcpy(struct iop_adma_chan *iop_chan)
1343 {
1344 struct iop_adma_desc_slot *sw_desc, *grp_start;
1345 dma_cookie_t cookie;
1346 int slot_cnt, slots_per_op;
1347
1348 <<<<<<< HEAD:drivers/dma/iop-adma.c
1349 dev_dbg(iop_chan->device->common.dev, "%s\n", __FUNCTION__);
1350 =======
1351 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1352 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
1353
1354 spin_lock_bh(&iop_chan->lock);
1355 slot_cnt = iop_chan_memcpy_slot_count(0, &slots_per_op);
1356 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1357 if (sw_desc) {
1358 grp_start = sw_desc->group_head;
1359
1360 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1361 sw_desc->async_tx.ack = 1;
1362 iop_desc_init_memcpy(grp_start, 0);
1363 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1364 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1365 iop_desc_set_memcpy_src_addr(grp_start, 0);
1366
1367 cookie = iop_chan->common.cookie;
1368 cookie++;
1369 if (cookie <= 1)
1370 cookie = 2;
1371
1372 /* initialize the completed cookie to be less than
1373 * the most recently used cookie
1374 */
1375 iop_chan->completed_cookie = cookie - 1;
1376 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1377
1378 /* channel should not be busy */
1379 BUG_ON(iop_chan_is_busy(iop_chan));
1380
1381 /* clear any prior error-status bits */
1382 iop_adma_device_clear_err_status(iop_chan);
1383
1384 /* disable operation */
1385 iop_chan_disable(iop_chan);
1386
1387 /* set the descriptor address */
1388 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1389
1390 /* 1/ don't add pre-chained descriptors
1391 * 2/ dummy read to flush next_desc write
1392 */
1393 BUG_ON(iop_desc_get_next_desc(sw_desc));
1394
1395 /* run the descriptor */
1396 iop_chan_enable(iop_chan);
1397 } else
1398 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1399 "failed to allocate null descriptor\n");
1400 spin_unlock_bh(&iop_chan->lock);
1401 }
1402
1403 static void iop_chan_start_null_xor(struct iop_adma_chan *iop_chan)
1404 {
1405 struct iop_adma_desc_slot *sw_desc, *grp_start;
1406 dma_cookie_t cookie;
1407 int slot_cnt, slots_per_op;
1408
1409 <<<<<<< HEAD:drivers/dma/iop-adma.c
1410 dev_dbg(iop_chan->device->common.dev, "%s\n", __FUNCTION__);
1411 =======
1412 dev_dbg(iop_chan->device->common.dev, "%s\n", __func__);
1413 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/dma/iop-adma.c
1414
1415 spin_lock_bh(&iop_chan->lock);
1416 slot_cnt = iop_chan_xor_slot_count(0, 2, &slots_per_op);
1417 sw_desc = iop_adma_alloc_slots(iop_chan, slot_cnt, slots_per_op);
1418 if (sw_desc) {
1419 grp_start = sw_desc->group_head;
1420 list_splice_init(&sw_desc->async_tx.tx_list, &iop_chan->chain);
1421 sw_desc->async_tx.ack = 1;
1422 iop_desc_init_null_xor(grp_start, 2, 0);
1423 iop_desc_set_byte_count(grp_start, iop_chan, 0);
1424 iop_desc_set_dest_addr(grp_start, iop_chan, 0);
1425 iop_desc_set_xor_src_addr(grp_start, 0, 0);
1426 iop_desc_set_xor_src_addr(grp_start, 1, 0);
1427
1428 cookie = iop_chan->common.cookie;
1429 cookie++;
1430 if (cookie <= 1)
1431 cookie = 2;
1432
1433 /* initialize the completed cookie to be less than
1434 * the most recently used cookie
1435 */
1436 iop_chan->completed_cookie = cookie - 1;
1437 iop_chan->common.cookie = sw_desc->async_tx.cookie = cookie;
1438
1439 /* channel should not be busy */
1440 BUG_ON(iop_chan_is_busy(iop_chan));
1441
1442 /* clear any prior error-status bits */
1443 iop_adma_device_clear_err_status(iop_chan);
1444
1445 /* disable operation */
1446 iop_chan_disable(iop_chan);
1447
1448 /* set the descriptor address */
1449 iop_chan_set_next_descriptor(iop_chan, sw_desc->async_tx.phys);
1450
1451 /* 1/ don't add pre-chained descriptors
1452 * 2/ dummy read to flush next_desc write
1453 */
1454 BUG_ON(iop_desc_get_next_desc(sw_desc));
1455
1456 /* run the descriptor */
1457 iop_chan_enable(iop_chan);
1458 } else
1459 dev_printk(KERN_ERR, iop_chan->device->common.dev,
1460 "failed to allocate null descriptor\n");
1461 spin_unlock_bh(&iop_chan->lock);
1462 }
1463
1464 static struct platform_driver iop_adma_driver = {
1465 .probe = iop_adma_probe,
1466 .remove = iop_adma_remove,
1467 .driver = {
1468 .owner = THIS_MODULE,
1469 .name = "iop-adma",
1470 },
1471 };
1472
1473 static int __init iop_adma_init (void)
1474 {
1475 return platform_driver_register(&iop_adma_driver);
1476 }
1477
1478 /* it's currently unsafe to unload this module */
1479 #if 0
1480 static void __exit iop_adma_exit (void)
1481 {
1482 platform_driver_unregister(&iop_adma_driver);
1483 return;
1484 }
1485 module_exit(iop_adma_exit);
1486 #endif
1487
1488 module_init(iop_adma_init);
1489
1490 MODULE_AUTHOR("Intel Corporation");
1491 MODULE_DESCRIPTION("IOP ADMA Engine Driver");
1492 MODULE_LICENSE("GPL");
WRT350N Kernel Patches