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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / char / agp / sis-agp.c
blobb2fbb299986e19060517cc71c6b3dabcda43d79d
1 /*
2 * SiS AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/agp_backend.h>
9 #include <linux/delay.h>
10 #include "agp.h"
11
12 #define SIS_ATTBASE 0x90
13 #define SIS_APSIZE 0x94
14 #define SIS_TLBCNTRL 0x97
15 #define SIS_TLBFLUSH 0x98
16
17 <<<<<<< HEAD:drivers/char/agp/sis-agp.c
18 =======
19 #define PCI_DEVICE_ID_SI_662 0x0662
20 #define PCI_DEVICE_ID_SI_671 0x0671
21
22 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/agp/sis-agp.c
23 static int __devinitdata agp_sis_force_delay = 0;
24 static int __devinitdata agp_sis_agp_spec = -1;
25
26 static int sis_fetch_size(void)
27 {
28 u8 temp_size;
29 int i;
30 struct aper_size_info_8 *values;
31
32 pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size);
33 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
34 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
35 if ((temp_size == values[i].size_value) ||
36 <<<<<<< HEAD:drivers/char/agp/sis-agp.c
37 ((temp_size & ~(0x03)) ==
38 (values[i].size_value & ~(0x03)))) {
39 =======
40 ((temp_size & ~(0x07)) ==
41 (values[i].size_value & ~(0x07)))) {
42 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/agp/sis-agp.c
43 agp_bridge->previous_size =
44 agp_bridge->current_size = (void *) (values + i);
45
46 agp_bridge->aperture_size_idx = i;
47 return values[i].size;
48 }
49 }
50
51 return 0;
52 }
53
54 static void sis_tlbflush(struct agp_memory *mem)
55 {
56 pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02);
57 }
58
59 static int sis_configure(void)
60 {
61 u32 temp;
62 struct aper_size_info_8 *current_size;
63
64 current_size = A_SIZE_8(agp_bridge->current_size);
65 pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05);
66 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
67 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
68 pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE,
69 agp_bridge->gatt_bus_addr);
70 pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
71 current_size->size_value);
72 return 0;
73 }
74
75 static void sis_cleanup(void)
76 {
77 struct aper_size_info_8 *previous_size;
78
79 previous_size = A_SIZE_8(agp_bridge->previous_size);
80 pci_write_config_byte(agp_bridge->dev, SIS_APSIZE,
81 (previous_size->size_value & ~(0x03)));
82 }
83
84 static void sis_delayed_enable(struct agp_bridge_data *bridge, u32 mode)
85 {
86 struct pci_dev *device = NULL;
87 u32 command;
88 int rate;
89
90 printk(KERN_INFO PFX "Found an AGP %d.%d compliant device at %s.\n",
91 agp_bridge->major_version,
92 agp_bridge->minor_version,
93 pci_name(agp_bridge->dev));
94
95 pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + PCI_AGP_STATUS, &command);
96 command = agp_collect_device_status(bridge, mode, command);
97 command |= AGPSTAT_AGP_ENABLE;
98 rate = (command & 0x7) << 2;
99
100 for_each_pci_dev(device) {
101 u8 agp = pci_find_capability(device, PCI_CAP_ID_AGP);
102 if (!agp)
103 continue;
104
105 printk(KERN_INFO PFX "Putting AGP V3 device at %s into %dx mode\n",
106 pci_name(device), rate);
107
108 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, command);
109
110 /*
111 * Weird: on some sis chipsets any rate change in the target
112 * command register triggers a 5ms screwup during which the master
113 * cannot be configured
114 */
115 if (device->device == bridge->dev->device) {
116 printk(KERN_INFO PFX "SiS delay workaround: giving bridge time to recover.\n");
117 msleep(10);
118 }
119 }
120 }
121
122 static const struct aper_size_info_8 sis_generic_sizes[7] =
123 {
124 {256, 65536, 6, 99},
125 {128, 32768, 5, 83},
126 {64, 16384, 4, 67},
127 {32, 8192, 3, 51},
128 {16, 4096, 2, 35},
129 {8, 2048, 1, 19},
130 {4, 1024, 0, 3}
131 };
132
133 static struct agp_bridge_driver sis_driver = {
134 .owner = THIS_MODULE,
135 .aperture_sizes = sis_generic_sizes,
136 .size_type = U8_APER_SIZE,
137 .num_aperture_sizes = 7,
138 .configure = sis_configure,
139 .fetch_size = sis_fetch_size,
140 .cleanup = sis_cleanup,
141 .tlb_flush = sis_tlbflush,
142 .mask_memory = agp_generic_mask_memory,
143 .masks = NULL,
144 .agp_enable = agp_generic_enable,
145 .cache_flush = global_cache_flush,
146 .create_gatt_table = agp_generic_create_gatt_table,
147 .free_gatt_table = agp_generic_free_gatt_table,
148 .insert_memory = agp_generic_insert_memory,
149 .remove_memory = agp_generic_remove_memory,
150 .alloc_by_type = agp_generic_alloc_by_type,
151 .free_by_type = agp_generic_free_by_type,
152 .agp_alloc_page = agp_generic_alloc_page,
153 .agp_destroy_page = agp_generic_destroy_page,
154 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
155 };
156
157 // chipsets that require the 'delay hack'
158 static int sis_broken_chipsets[] __devinitdata = {
159 PCI_DEVICE_ID_SI_648,
160 PCI_DEVICE_ID_SI_746,
161 0 // terminator
162 };
163
164 static void __devinit sis_get_driver(struct agp_bridge_data *bridge)
165 {
166 int i;
167
168 for (i=0; sis_broken_chipsets[i]!=0; ++i)
169 if (bridge->dev->device==sis_broken_chipsets[i])
170 break;
171
172 if (sis_broken_chipsets[i] || agp_sis_force_delay)
173 sis_driver.agp_enable=sis_delayed_enable;
174
175 // sis chipsets that indicate less than agp3.5
176 // are not actually fully agp3 compliant
177 if ((agp_bridge->major_version == 3 && agp_bridge->minor_version >= 5
178 && agp_sis_agp_spec!=0) || agp_sis_agp_spec==1) {
179 sis_driver.aperture_sizes = agp3_generic_sizes;
180 sis_driver.size_type = U16_APER_SIZE;
181 sis_driver.num_aperture_sizes = AGP_GENERIC_SIZES_ENTRIES;
182 sis_driver.configure = agp3_generic_configure;
183 sis_driver.fetch_size = agp3_generic_fetch_size;
184 sis_driver.cleanup = agp3_generic_cleanup;
185 sis_driver.tlb_flush = agp3_generic_tlbflush;
186 }
187 }
188
189
190 static int __devinit agp_sis_probe(struct pci_dev *pdev,
191 const struct pci_device_id *ent)
192 {
193 struct agp_bridge_data *bridge;
194 u8 cap_ptr;
195
196 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
197 if (!cap_ptr)
198 return -ENODEV;
199
200
201 printk(KERN_INFO PFX "Detected SiS chipset - id:%i\n", pdev->device);
202 bridge = agp_alloc_bridge();
203 if (!bridge)
204 return -ENOMEM;
205
206 bridge->driver = &sis_driver;
207 bridge->dev = pdev;
208 bridge->capndx = cap_ptr;
209
210 get_agp_version(bridge);
211
212 /* Fill in the mode register */
213 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
214 sis_get_driver(bridge);
215
216 pci_set_drvdata(pdev, bridge);
217 return agp_add_bridge(bridge);
218 }
219
220 static void __devexit agp_sis_remove(struct pci_dev *pdev)
221 {
222 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
223
224 agp_remove_bridge(bridge);
225 agp_put_bridge(bridge);
226 }
227
228 <<<<<<< HEAD:drivers/char/agp/sis-agp.c
229 =======
230 #ifdef CONFIG_PM
231
232 static int agp_sis_suspend(struct pci_dev *pdev, pm_message_t state)
233 {
234 pci_save_state(pdev);
235 pci_set_power_state(pdev, pci_choose_state(pdev, state));
236
237 return 0;
238 }
239
240 static int agp_sis_resume(struct pci_dev *pdev)
241 {
242 pci_set_power_state(pdev, PCI_D0);
243 pci_restore_state(pdev);
244
245 return sis_driver.configure();
246 }
247
248 #endif /* CONFIG_PM */
249
250 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/agp/sis-agp.c
251 static struct pci_device_id agp_sis_pci_table[] = {
252 {
253 .class = (PCI_CLASS_BRIDGE_HOST << 8),
254 .class_mask = ~0,
255 .vendor = PCI_VENDOR_ID_SI,
256 .device = PCI_DEVICE_ID_SI_5591_AGP,
257 .subvendor = PCI_ANY_ID,
258 .subdevice = PCI_ANY_ID,
259 },
260 {
261 .class = (PCI_CLASS_BRIDGE_HOST << 8),
262 .class_mask = ~0,
263 .vendor = PCI_VENDOR_ID_SI,
264 .device = PCI_DEVICE_ID_SI_530,
265 .subvendor = PCI_ANY_ID,
266 .subdevice = PCI_ANY_ID,
267 },
268 {
269 .class = (PCI_CLASS_BRIDGE_HOST << 8),
270 .class_mask = ~0,
271 .vendor = PCI_VENDOR_ID_SI,
272 .device = PCI_DEVICE_ID_SI_540,
273 .subvendor = PCI_ANY_ID,
274 .subdevice = PCI_ANY_ID,
275 },
276 {
277 .class = (PCI_CLASS_BRIDGE_HOST << 8),
278 .class_mask = ~0,
279 .vendor = PCI_VENDOR_ID_SI,
280 .device = PCI_DEVICE_ID_SI_550,
281 .subvendor = PCI_ANY_ID,
282 .subdevice = PCI_ANY_ID,
283 },
284 {
285 .class = (PCI_CLASS_BRIDGE_HOST << 8),
286 .class_mask = ~0,
287 .vendor = PCI_VENDOR_ID_SI,
288 .device = PCI_DEVICE_ID_SI_620,
289 .subvendor = PCI_ANY_ID,
290 .subdevice = PCI_ANY_ID,
291 },
292 {
293 .class = (PCI_CLASS_BRIDGE_HOST << 8),
294 .class_mask = ~0,
295 .vendor = PCI_VENDOR_ID_SI,
296 .device = PCI_DEVICE_ID_SI_630,
297 .subvendor = PCI_ANY_ID,
298 .subdevice = PCI_ANY_ID,
299 },
300 {
301 .class = (PCI_CLASS_BRIDGE_HOST << 8),
302 .class_mask = ~0,
303 .vendor = PCI_VENDOR_ID_SI,
304 .device = PCI_DEVICE_ID_SI_635,
305 .subvendor = PCI_ANY_ID,
306 .subdevice = PCI_ANY_ID,
307 },
308 {
309 .class = (PCI_CLASS_BRIDGE_HOST << 8),
310 .class_mask = ~0,
311 .vendor = PCI_VENDOR_ID_SI,
312 .device = PCI_DEVICE_ID_SI_645,
313 .subvendor = PCI_ANY_ID,
314 .subdevice = PCI_ANY_ID,
315 },
316 {
317 .class = (PCI_CLASS_BRIDGE_HOST << 8),
318 .class_mask = ~0,
319 .vendor = PCI_VENDOR_ID_SI,
320 .device = PCI_DEVICE_ID_SI_646,
321 .subvendor = PCI_ANY_ID,
322 .subdevice = PCI_ANY_ID,
323 },
324 {
325 .class = (PCI_CLASS_BRIDGE_HOST << 8),
326 .class_mask = ~0,
327 .vendor = PCI_VENDOR_ID_SI,
328 .device = PCI_DEVICE_ID_SI_648,
329 .subvendor = PCI_ANY_ID,
330 .subdevice = PCI_ANY_ID,
331 },
332 {
333 .class = (PCI_CLASS_BRIDGE_HOST << 8),
334 .class_mask = ~0,
335 .vendor = PCI_VENDOR_ID_SI,
336 .device = PCI_DEVICE_ID_SI_650,
337 .subvendor = PCI_ANY_ID,
338 .subdevice = PCI_ANY_ID,
339 },
340 {
341 .class = (PCI_CLASS_BRIDGE_HOST << 8),
342 .class_mask = ~0,
343 .vendor = PCI_VENDOR_ID_SI,
344 .device = PCI_DEVICE_ID_SI_651,
345 .subvendor = PCI_ANY_ID,
346 .subdevice = PCI_ANY_ID,
347 },
348 {
349 .class = (PCI_CLASS_BRIDGE_HOST << 8),
350 .class_mask = ~0,
351 .vendor = PCI_VENDOR_ID_SI,
352 .device = PCI_DEVICE_ID_SI_655,
353 .subvendor = PCI_ANY_ID,
354 .subdevice = PCI_ANY_ID,
355 },
356 {
357 .class = (PCI_CLASS_BRIDGE_HOST << 8),
358 .class_mask = ~0,
359 .vendor = PCI_VENDOR_ID_SI,
360 .device = PCI_DEVICE_ID_SI_661,
361 .subvendor = PCI_ANY_ID,
362 .subdevice = PCI_ANY_ID,
363 },
364 {
365 .class = (PCI_CLASS_BRIDGE_HOST << 8),
366 .class_mask = ~0,
367 .vendor = PCI_VENDOR_ID_SI,
368 <<<<<<< HEAD:drivers/char/agp/sis-agp.c
369 =======
370 .device = PCI_DEVICE_ID_SI_662,
371 .subvendor = PCI_ANY_ID,
372 .subdevice = PCI_ANY_ID,
373 },
374 {
375 .class = (PCI_CLASS_BRIDGE_HOST << 8),
376 .class_mask = ~0,
377 .vendor = PCI_VENDOR_ID_SI,
378 .device = PCI_DEVICE_ID_SI_671,
379 .subvendor = PCI_ANY_ID,
380 .subdevice = PCI_ANY_ID,
381 },
382 {
383 .class = (PCI_CLASS_BRIDGE_HOST << 8),
384 .class_mask = ~0,
385 .vendor = PCI_VENDOR_ID_SI,
386 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/agp/sis-agp.c
387 .device = PCI_DEVICE_ID_SI_730,
388 .subvendor = PCI_ANY_ID,
389 .subdevice = PCI_ANY_ID,
390 },
391 {
392 .class = (PCI_CLASS_BRIDGE_HOST << 8),
393 .class_mask = ~0,
394 .vendor = PCI_VENDOR_ID_SI,
395 .device = PCI_DEVICE_ID_SI_735,
396 .subvendor = PCI_ANY_ID,
397 .subdevice = PCI_ANY_ID,
398 },
399 {
400 .class = (PCI_CLASS_BRIDGE_HOST << 8),
401 .class_mask = ~0,
402 .vendor = PCI_VENDOR_ID_SI,
403 .device = PCI_DEVICE_ID_SI_740,
404 .subvendor = PCI_ANY_ID,
405 .subdevice = PCI_ANY_ID,
406 },
407 {
408 .class = (PCI_CLASS_BRIDGE_HOST << 8),
409 .class_mask = ~0,
410 .vendor = PCI_VENDOR_ID_SI,
411 .device = PCI_DEVICE_ID_SI_741,
412 .subvendor = PCI_ANY_ID,
413 .subdevice = PCI_ANY_ID,
414 },
415 {
416 .class = (PCI_CLASS_BRIDGE_HOST << 8),
417 .class_mask = ~0,
418 .vendor = PCI_VENDOR_ID_SI,
419 .device = PCI_DEVICE_ID_SI_745,
420 .subvendor = PCI_ANY_ID,
421 .subdevice = PCI_ANY_ID,
422 },
423 {
424 .class = (PCI_CLASS_BRIDGE_HOST << 8),
425 .class_mask = ~0,
426 .vendor = PCI_VENDOR_ID_SI,
427 .device = PCI_DEVICE_ID_SI_746,
428 .subvendor = PCI_ANY_ID,
429 .subdevice = PCI_ANY_ID,
430 },
431 {
432 .class = (PCI_CLASS_BRIDGE_HOST << 8),
433 .class_mask = ~0,
434 .vendor = PCI_VENDOR_ID_SI,
435 .device = PCI_DEVICE_ID_SI_760,
436 .subvendor = PCI_ANY_ID,
437 .subdevice = PCI_ANY_ID,
438 },
439 { }
440 };
441
442 MODULE_DEVICE_TABLE(pci, agp_sis_pci_table);
443
444 static struct pci_driver agp_sis_pci_driver = {
445 .name = "agpgart-sis",
446 .id_table = agp_sis_pci_table,
447 .probe = agp_sis_probe,
448 .remove = agp_sis_remove,
449 <<<<<<< HEAD:drivers/char/agp/sis-agp.c
450 =======
451 #ifdef CONFIG_PM
452 .suspend = agp_sis_suspend,
453 .resume = agp_sis_resume,
454 #endif
455 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/char/agp/sis-agp.c
456 };
457
458 static int __init agp_sis_init(void)
459 {
460 if (agp_off)
461 return -EINVAL;
462 return pci_register_driver(&agp_sis_pci_driver);
463 }
464
465 static void __exit agp_sis_cleanup(void)
466 {
467 pci_unregister_driver(&agp_sis_pci_driver);
468 }
469
470 module_init(agp_sis_init);
471 module_exit(agp_sis_cleanup);
472
473 module_param(agp_sis_force_delay, bool, 0);
474 MODULE_PARM_DESC(agp_sis_force_delay,"forces sis delay hack");
475 module_param(agp_sis_agp_spec, int, 0);
476 MODULE_PARM_DESC(agp_sis_agp_spec,"0=force sis init, 1=force generic agp3 init, default: autodetect");
477 MODULE_LICENSE("GPL and additional rights");
WRT350N Kernel Patches