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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / atm / idt77252.c
blob3e3c36b12c42611f805e34845940feaaa1e836e3
1 /*******************************************************************
2 * ident "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $"
3 *
4 * $Author: ecd $
5 * $Date: 2001/11/11 08:13:54 $
6 *
7 * Copyright (c) 2000 ATecoM GmbH
8 *
9 * The author may be reached at ecd@atecom.com.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 *******************************************************************/
32 static char const rcsid[] =
33 "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $";
34
35
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/skbuff.h>
40 #include <linux/kernel.h>
41 #include <linux/vmalloc.h>
42 #include <linux/netdevice.h>
43 #include <linux/atmdev.h>
44 #include <linux/atm.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/bitops.h>
48 #include <linux/wait.h>
49 #include <linux/jiffies.h>
50 #include <linux/mutex.h>
51
52 #include <asm/io.h>
53 #include <asm/uaccess.h>
54 #include <asm/atomic.h>
55 #include <asm/byteorder.h>
56
57 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
58 #include "suni.h"
59 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
60
61
62 #include "idt77252.h"
63 #include "idt77252_tables.h"
64
65 static unsigned int vpibits = 1;
66
67
68 #define ATM_IDT77252_SEND_IDLE 1
69
70
71 /*
72 * Debug HACKs.
73 */
74 #define DEBUG_MODULE 1
75 #undef HAVE_EEPROM /* does not work, yet. */
76
77 #ifdef CONFIG_ATM_IDT77252_DEBUG
78 static unsigned long debug = DBG_GENERAL;
79 #endif
80
81
82 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
83
84
85 /*
86 * SCQ Handling.
87 */
88 static struct scq_info *alloc_scq(struct idt77252_dev *, int);
89 static void free_scq(struct idt77252_dev *, struct scq_info *);
90 static int queue_skb(struct idt77252_dev *, struct vc_map *,
91 struct sk_buff *, int oam);
92 static void drain_scq(struct idt77252_dev *, struct vc_map *);
93 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
94 static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
95
96 /*
97 * FBQ Handling.
98 */
99 static int push_rx_skb(struct idt77252_dev *,
100 struct sk_buff *, int queue);
101 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
102 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
103 static void recycle_rx_pool_skb(struct idt77252_dev *,
104 struct rx_pool *);
105 static void add_rx_skb(struct idt77252_dev *, int queue,
106 unsigned int size, unsigned int count);
107
108 /*
109 * RSQ Handling.
110 */
111 static int init_rsq(struct idt77252_dev *);
112 static void deinit_rsq(struct idt77252_dev *);
113 static void idt77252_rx(struct idt77252_dev *);
114
115 /*
116 * TSQ handling.
117 */
118 static int init_tsq(struct idt77252_dev *);
119 static void deinit_tsq(struct idt77252_dev *);
120 static void idt77252_tx(struct idt77252_dev *);
121
122
123 /*
124 * ATM Interface.
125 */
126 static void idt77252_dev_close(struct atm_dev *dev);
127 static int idt77252_open(struct atm_vcc *vcc);
128 static void idt77252_close(struct atm_vcc *vcc);
129 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
130 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
131 int flags);
132 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
133 unsigned long addr);
134 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
135 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
136 int flags);
137 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
138 char *page);
139 static void idt77252_softint(struct work_struct *work);
140
141
142 static struct atmdev_ops idt77252_ops =
143 {
144 .dev_close = idt77252_dev_close,
145 .open = idt77252_open,
146 .close = idt77252_close,
147 .send = idt77252_send,
148 .send_oam = idt77252_send_oam,
149 .phy_put = idt77252_phy_put,
150 .phy_get = idt77252_phy_get,
151 .change_qos = idt77252_change_qos,
152 .proc_read = idt77252_proc_read,
153 .owner = THIS_MODULE
154 };
155
156 static struct idt77252_dev *idt77252_chain = NULL;
157 static unsigned int idt77252_sram_write_errors = 0;
158
159 /*****************************************************************************/
160 /* */
161 /* I/O and Utility Bus */
162 /* */
163 /*****************************************************************************/
164
165 static void
166 waitfor_idle(struct idt77252_dev *card)
167 {
168 u32 stat;
169
170 stat = readl(SAR_REG_STAT);
171 while (stat & SAR_STAT_CMDBZ)
172 stat = readl(SAR_REG_STAT);
173 }
174
175 static u32
176 read_sram(struct idt77252_dev *card, unsigned long addr)
177 {
178 unsigned long flags;
179 u32 value;
180
181 spin_lock_irqsave(&card->cmd_lock, flags);
182 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
183 waitfor_idle(card);
184 value = readl(SAR_REG_DR0);
185 spin_unlock_irqrestore(&card->cmd_lock, flags);
186 return value;
187 }
188
189 static void
190 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
191 {
192 unsigned long flags;
193
194 if ((idt77252_sram_write_errors == 0) &&
195 (((addr > card->tst[0] + card->tst_size - 2) &&
196 (addr < card->tst[0] + card->tst_size)) ||
197 ((addr > card->tst[1] + card->tst_size - 2) &&
198 (addr < card->tst[1] + card->tst_size)))) {
199 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
200 card->name, addr, value);
201 }
202
203 spin_lock_irqsave(&card->cmd_lock, flags);
204 writel(value, SAR_REG_DR0);
205 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
206 waitfor_idle(card);
207 spin_unlock_irqrestore(&card->cmd_lock, flags);
208 }
209
210 static u8
211 read_utility(void *dev, unsigned long ubus_addr)
212 {
213 struct idt77252_dev *card = dev;
214 unsigned long flags;
215 u8 value;
216
217 if (!card) {
218 printk("Error: No such device.\n");
219 return -1;
220 }
221
222 spin_lock_irqsave(&card->cmd_lock, flags);
223 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
224 waitfor_idle(card);
225 value = readl(SAR_REG_DR0);
226 spin_unlock_irqrestore(&card->cmd_lock, flags);
227 return value;
228 }
229
230 static void
231 write_utility(void *dev, unsigned long ubus_addr, u8 value)
232 {
233 struct idt77252_dev *card = dev;
234 unsigned long flags;
235
236 if (!card) {
237 printk("Error: No such device.\n");
238 return;
239 }
240
241 spin_lock_irqsave(&card->cmd_lock, flags);
242 writel((u32) value, SAR_REG_DR0);
243 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
244 waitfor_idle(card);
245 spin_unlock_irqrestore(&card->cmd_lock, flags);
246 }
247
248 #ifdef HAVE_EEPROM
249 static u32 rdsrtab[] =
250 {
251 SAR_GP_EECS | SAR_GP_EESCLK,
252 0,
253 SAR_GP_EESCLK, /* 0 */
254 0,
255 SAR_GP_EESCLK, /* 0 */
256 0,
257 SAR_GP_EESCLK, /* 0 */
258 0,
259 SAR_GP_EESCLK, /* 0 */
260 0,
261 SAR_GP_EESCLK, /* 0 */
262 SAR_GP_EEDO,
263 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
264 0,
265 SAR_GP_EESCLK, /* 0 */
266 SAR_GP_EEDO,
267 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
268 };
269
270 static u32 wrentab[] =
271 {
272 SAR_GP_EECS | SAR_GP_EESCLK,
273 0,
274 SAR_GP_EESCLK, /* 0 */
275 0,
276 SAR_GP_EESCLK, /* 0 */
277 0,
278 SAR_GP_EESCLK, /* 0 */
279 0,
280 SAR_GP_EESCLK, /* 0 */
281 SAR_GP_EEDO,
282 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
283 SAR_GP_EEDO,
284 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
285 0,
286 SAR_GP_EESCLK, /* 0 */
287 0,
288 SAR_GP_EESCLK /* 0 */
289 };
290
291 static u32 rdtab[] =
292 {
293 SAR_GP_EECS | SAR_GP_EESCLK,
294 0,
295 SAR_GP_EESCLK, /* 0 */
296 0,
297 SAR_GP_EESCLK, /* 0 */
298 0,
299 SAR_GP_EESCLK, /* 0 */
300 0,
301 SAR_GP_EESCLK, /* 0 */
302 0,
303 SAR_GP_EESCLK, /* 0 */
304 0,
305 SAR_GP_EESCLK, /* 0 */
306 SAR_GP_EEDO,
307 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
308 SAR_GP_EEDO,
309 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
310 };
311
312 static u32 wrtab[] =
313 {
314 SAR_GP_EECS | SAR_GP_EESCLK,
315 0,
316 SAR_GP_EESCLK, /* 0 */
317 0,
318 SAR_GP_EESCLK, /* 0 */
319 0,
320 SAR_GP_EESCLK, /* 0 */
321 0,
322 SAR_GP_EESCLK, /* 0 */
323 0,
324 SAR_GP_EESCLK, /* 0 */
325 0,
326 SAR_GP_EESCLK, /* 0 */
327 SAR_GP_EEDO,
328 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
329 0,
330 SAR_GP_EESCLK /* 0 */
331 };
332
333 static u32 clktab[] =
334 {
335 0,
336 SAR_GP_EESCLK,
337 0,
338 SAR_GP_EESCLK,
339 0,
340 SAR_GP_EESCLK,
341 0,
342 SAR_GP_EESCLK,
343 0,
344 SAR_GP_EESCLK,
345 0,
346 SAR_GP_EESCLK,
347 0,
348 SAR_GP_EESCLK,
349 0,
350 SAR_GP_EESCLK,
351 0
352 };
353
354 static u32
355 idt77252_read_gp(struct idt77252_dev *card)
356 {
357 u32 gp;
358
359 gp = readl(SAR_REG_GP);
360 #if 0
361 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
362 #endif
363 return gp;
364 }
365
366 static void
367 idt77252_write_gp(struct idt77252_dev *card, u32 value)
368 {
369 unsigned long flags;
370
371 #if 0
372 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
373 value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
374 value & SAR_GP_EEDO ? "1" : "0");
375 #endif
376
377 spin_lock_irqsave(&card->cmd_lock, flags);
378 waitfor_idle(card);
379 writel(value, SAR_REG_GP);
380 spin_unlock_irqrestore(&card->cmd_lock, flags);
381 }
382
383 static u8
384 idt77252_eeprom_read_status(struct idt77252_dev *card)
385 {
386 u8 byte;
387 u32 gp;
388 int i, j;
389
390 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
391
392 for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) {
393 idt77252_write_gp(card, gp | rdsrtab[i]);
394 udelay(5);
395 }
396 idt77252_write_gp(card, gp | SAR_GP_EECS);
397 udelay(5);
398
399 byte = 0;
400 for (i = 0, j = 0; i < 8; i++) {
401 byte <<= 1;
402
403 idt77252_write_gp(card, gp | clktab[j++]);
404 udelay(5);
405
406 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
407
408 idt77252_write_gp(card, gp | clktab[j++]);
409 udelay(5);
410 }
411 idt77252_write_gp(card, gp | SAR_GP_EECS);
412 udelay(5);
413
414 return byte;
415 }
416
417 static u8
418 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
419 {
420 u8 byte;
421 u32 gp;
422 int i, j;
423
424 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
425
426 for (i = 0; i < ARRAY_SIZE(rdtab); i++) {
427 idt77252_write_gp(card, gp | rdtab[i]);
428 udelay(5);
429 }
430 idt77252_write_gp(card, gp | SAR_GP_EECS);
431 udelay(5);
432
433 for (i = 0, j = 0; i < 8; i++) {
434 idt77252_write_gp(card, gp | clktab[j++] |
435 (offset & 1 ? SAR_GP_EEDO : 0));
436 udelay(5);
437
438 idt77252_write_gp(card, gp | clktab[j++] |
439 (offset & 1 ? SAR_GP_EEDO : 0));
440 udelay(5);
441
442 offset >>= 1;
443 }
444 idt77252_write_gp(card, gp | SAR_GP_EECS);
445 udelay(5);
446
447 byte = 0;
448 for (i = 0, j = 0; i < 8; i++) {
449 byte <<= 1;
450
451 idt77252_write_gp(card, gp | clktab[j++]);
452 udelay(5);
453
454 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
455
456 idt77252_write_gp(card, gp | clktab[j++]);
457 udelay(5);
458 }
459 idt77252_write_gp(card, gp | SAR_GP_EECS);
460 udelay(5);
461
462 return byte;
463 }
464
465 static void
466 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
467 {
468 u32 gp;
469 int i, j;
470
471 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
472
473 for (i = 0; i < ARRAY_SIZE(wrentab); i++) {
474 idt77252_write_gp(card, gp | wrentab[i]);
475 udelay(5);
476 }
477 idt77252_write_gp(card, gp | SAR_GP_EECS);
478 udelay(5);
479
480 for (i = 0; i < ARRAY_SIZE(wrtab); i++) {
481 idt77252_write_gp(card, gp | wrtab[i]);
482 udelay(5);
483 }
484 idt77252_write_gp(card, gp | SAR_GP_EECS);
485 udelay(5);
486
487 for (i = 0, j = 0; i < 8; i++) {
488 idt77252_write_gp(card, gp | clktab[j++] |
489 (offset & 1 ? SAR_GP_EEDO : 0));
490 udelay(5);
491
492 idt77252_write_gp(card, gp | clktab[j++] |
493 (offset & 1 ? SAR_GP_EEDO : 0));
494 udelay(5);
495
496 offset >>= 1;
497 }
498 idt77252_write_gp(card, gp | SAR_GP_EECS);
499 udelay(5);
500
501 for (i = 0, j = 0; i < 8; i++) {
502 idt77252_write_gp(card, gp | clktab[j++] |
503 (data & 1 ? SAR_GP_EEDO : 0));
504 udelay(5);
505
506 idt77252_write_gp(card, gp | clktab[j++] |
507 (data & 1 ? SAR_GP_EEDO : 0));
508 udelay(5);
509
510 data >>= 1;
511 }
512 idt77252_write_gp(card, gp | SAR_GP_EECS);
513 udelay(5);
514 }
515
516 static void
517 idt77252_eeprom_init(struct idt77252_dev *card)
518 {
519 u32 gp;
520
521 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
522
523 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
524 udelay(5);
525 idt77252_write_gp(card, gp | SAR_GP_EECS);
526 udelay(5);
527 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
528 udelay(5);
529 idt77252_write_gp(card, gp | SAR_GP_EECS);
530 udelay(5);
531 }
532 #endif /* HAVE_EEPROM */
533
534
535 #ifdef CONFIG_ATM_IDT77252_DEBUG
536 static void
537 dump_tct(struct idt77252_dev *card, int index)
538 {
539 unsigned long tct;
540 int i;
541
542 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
543
544 printk("%s: TCT %x:", card->name, index);
545 for (i = 0; i < 8; i++) {
546 printk(" %08x", read_sram(card, tct + i));
547 }
548 printk("\n");
549 }
550
551 static void
552 idt77252_tx_dump(struct idt77252_dev *card)
553 {
554 struct atm_vcc *vcc;
555 struct vc_map *vc;
556 int i;
557
558 <<<<<<< HEAD:drivers/atm/idt77252.c
559 printk("%s\n", __FUNCTION__);
560 =======
561 printk("%s\n", __func__);
562 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/atm/idt77252.c
563 for (i = 0; i < card->tct_size; i++) {
564 vc = card->vcs[i];
565 if (!vc)
566 continue;
567
568 vcc = NULL;
569 if (vc->rx_vcc)
570 vcc = vc->rx_vcc;
571 else if (vc->tx_vcc)
572 vcc = vc->tx_vcc;
573
574 if (!vcc)
575 continue;
576
577 printk("%s: Connection %d:\n", card->name, vc->index);
578 dump_tct(card, vc->index);
579 }
580 }
581 #endif
582
583
584 /*****************************************************************************/
585 /* */
586 /* SCQ Handling */
587 /* */
588 /*****************************************************************************/
589
590 static int
591 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
592 {
593 struct sb_pool *pool = &card->sbpool[queue];
594 int index;
595
596 index = pool->index;
597 while (pool->skb[index]) {
598 index = (index + 1) & FBQ_MASK;
599 if (index == pool->index)
600 return -ENOBUFS;
601 }
602
603 pool->skb[index] = skb;
604 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
605
606 pool->index = (index + 1) & FBQ_MASK;
607 return 0;
608 }
609
610 static void
611 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
612 {
613 unsigned int queue, index;
614 u32 handle;
615
616 handle = IDT77252_PRV_POOL(skb);
617
618 queue = POOL_QUEUE(handle);
619 if (queue > 3)
620 return;
621
622 index = POOL_INDEX(handle);
623 if (index > FBQ_SIZE - 1)
624 return;
625
626 card->sbpool[queue].skb[index] = NULL;
627 }
628
629 static struct sk_buff *
630 sb_pool_skb(struct idt77252_dev *card, u32 handle)
631 {
632 unsigned int queue, index;
633
634 queue = POOL_QUEUE(handle);
635 if (queue > 3)
636 return NULL;
637
638 index = POOL_INDEX(handle);
639 if (index > FBQ_SIZE - 1)
640 return NULL;
641
642 return card->sbpool[queue].skb[index];
643 }
644
645 static struct scq_info *
646 alloc_scq(struct idt77252_dev *card, int class)
647 {
648 struct scq_info *scq;
649
650 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL);
651 if (!scq)
652 return NULL;
653 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE,
654 &scq->paddr);
655 if (scq->base == NULL) {
656 kfree(scq);
657 return NULL;
658 }
659 memset(scq->base, 0, SCQ_SIZE);
660
661 scq->next = scq->base;
662 scq->last = scq->base + (SCQ_ENTRIES - 1);
663 atomic_set(&scq->used, 0);
664
665 spin_lock_init(&scq->lock);
666 spin_lock_init(&scq->skblock);
667
668 skb_queue_head_init(&scq->transmit);
669 skb_queue_head_init(&scq->pending);
670
671 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
672 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
673
674 return scq;
675 }
676
677 static void
678 free_scq(struct idt77252_dev *card, struct scq_info *scq)
679 {
680 struct sk_buff *skb;
681 struct atm_vcc *vcc;
682
683 pci_free_consistent(card->pcidev, SCQ_SIZE,
684 scq->base, scq->paddr);
685
686 while ((skb = skb_dequeue(&scq->transmit))) {
687 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
688 skb->len, PCI_DMA_TODEVICE);
689
690 vcc = ATM_SKB(skb)->vcc;
691 if (vcc->pop)
692 vcc->pop(vcc, skb);
693 else
694 dev_kfree_skb(skb);
695 }
696
697 while ((skb = skb_dequeue(&scq->pending))) {
698 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
699 skb->len, PCI_DMA_TODEVICE);
700
701 vcc = ATM_SKB(skb)->vcc;
702 if (vcc->pop)
703 vcc->pop(vcc, skb);
704 else
705 dev_kfree_skb(skb);
706 }
707
708 kfree(scq);
709 }
710
711
712 static int
713 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
714 {
715 struct scq_info *scq = vc->scq;
716 unsigned long flags;
717 struct scqe *tbd;
718 int entries;
719
720 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
721
722 atomic_inc(&scq->used);
723 entries = atomic_read(&scq->used);
724 if (entries > (SCQ_ENTRIES - 1)) {
725 atomic_dec(&scq->used);
726 goto out;
727 }
728
729 skb_queue_tail(&scq->transmit, skb);
730
731 spin_lock_irqsave(&vc->lock, flags);
732 if (vc->estimator) {
733 struct atm_vcc *vcc = vc->tx_vcc;
734 struct sock *sk = sk_atm(vcc);
735
736 vc->estimator->cells += (skb->len + 47) / 48;
737 if (atomic_read(&sk->sk_wmem_alloc) >
738 (sk->sk_sndbuf >> 1)) {
739 u32 cps = vc->estimator->maxcps;
740
741 vc->estimator->cps = cps;
742 vc->estimator->avcps = cps << 5;
743 if (vc->lacr < vc->init_er) {
744 vc->lacr = vc->init_er;
745 writel(TCMDQ_LACR | (vc->lacr << 16) |
746 vc->index, SAR_REG_TCMDQ);
747 }
748 }
749 }
750 spin_unlock_irqrestore(&vc->lock, flags);
751
752 tbd = &IDT77252_PRV_TBD(skb);
753
754 spin_lock_irqsave(&scq->lock, flags);
755 scq->next->word_1 = cpu_to_le32(tbd->word_1 |
756 SAR_TBD_TSIF | SAR_TBD_GTSI);
757 scq->next->word_2 = cpu_to_le32(tbd->word_2);
758 scq->next->word_3 = cpu_to_le32(tbd->word_3);
759 scq->next->word_4 = cpu_to_le32(tbd->word_4);
760
761 if (scq->next == scq->last)
762 scq->next = scq->base;
763 else
764 scq->next++;
765
766 write_sram(card, scq->scd,
767 scq->paddr +
768 (u32)((unsigned long)scq->next - (unsigned long)scq->base));
769 spin_unlock_irqrestore(&scq->lock, flags);
770
771 scq->trans_start = jiffies;
772
773 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
774 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
775 SAR_REG_TCMDQ);
776 }
777
778 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
779
780 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
781 card->name, atomic_read(&scq->used),
782 read_sram(card, scq->scd + 1), scq->next);
783
784 return 0;
785
786 out:
787 if (time_after(jiffies, scq->trans_start + HZ)) {
788 printk("%s: Error pushing TBD for %d.%d\n",
789 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
790 #ifdef CONFIG_ATM_IDT77252_DEBUG
791 idt77252_tx_dump(card);
792 #endif
793 scq->trans_start = jiffies;
794 }
795
796 return -ENOBUFS;
797 }
798
799
800 static void
801 drain_scq(struct idt77252_dev *card, struct vc_map *vc)
802 {
803 struct scq_info *scq = vc->scq;
804 struct sk_buff *skb;
805 struct atm_vcc *vcc;
806
807 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
808 card->name, atomic_read(&scq->used), scq->next);
809
810 skb = skb_dequeue(&scq->transmit);
811 if (skb) {
812 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
813
814 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
815 skb->len, PCI_DMA_TODEVICE);
816
817 vcc = ATM_SKB(skb)->vcc;
818
819 if (vcc->pop)
820 vcc->pop(vcc, skb);
821 else
822 dev_kfree_skb(skb);
823
824 atomic_inc(&vcc->stats->tx);
825 }
826
827 atomic_dec(&scq->used);
828
829 spin_lock(&scq->skblock);
830 while ((skb = skb_dequeue(&scq->pending))) {
831 if (push_on_scq(card, vc, skb)) {
832 skb_queue_head(&vc->scq->pending, skb);
833 break;
834 }
835 }
836 spin_unlock(&scq->skblock);
837 }
838
839 static int
840 queue_skb(struct idt77252_dev *card, struct vc_map *vc,
841 struct sk_buff *skb, int oam)
842 {
843 struct atm_vcc *vcc;
844 struct scqe *tbd;
845 unsigned long flags;
846 int error;
847 int aal;
848
849 if (skb->len == 0) {
850 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
851 return -EINVAL;
852 }
853
854 TXPRINTK("%s: Sending %d bytes of data.\n",
855 card->name, skb->len);
856
857 tbd = &IDT77252_PRV_TBD(skb);
858 vcc = ATM_SKB(skb)->vcc;
859
860 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data,
861 skb->len, PCI_DMA_TODEVICE);
862
863 error = -EINVAL;
864
865 if (oam) {
866 if (skb->len != 52)
867 goto errout;
868
869 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
870 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
871 tbd->word_3 = 0x00000000;
872 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
873 (skb->data[2] << 8) | (skb->data[3] << 0);
874
875 if (test_bit(VCF_RSV, &vc->flags))
876 vc = card->vcs[0];
877
878 goto done;
879 }
880
881 if (test_bit(VCF_RSV, &vc->flags)) {
882 printk("%s: Trying to transmit on reserved VC\n", card->name);
883 goto errout;
884 }
885
886 aal = vcc->qos.aal;
887
888 switch (aal) {
889 case ATM_AAL0:
890 case ATM_AAL34:
891 if (skb->len > 52)
892 goto errout;
893
894 if (aal == ATM_AAL0)
895 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
896 ATM_CELL_PAYLOAD;
897 else
898 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
899 ATM_CELL_PAYLOAD;
900
901 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
902 tbd->word_3 = 0x00000000;
903 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
904 (skb->data[2] << 8) | (skb->data[3] << 0);
905 break;
906
907 case ATM_AAL5:
908 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
909 tbd->word_2 = IDT77252_PRV_PADDR(skb);
910 tbd->word_3 = skb->len;
911 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
912 (vcc->vci << SAR_TBD_VCI_SHIFT);
913 break;
914
915 case ATM_AAL1:
916 case ATM_AAL2:
917 default:
918 printk("%s: Traffic type not supported.\n", card->name);
919 error = -EPROTONOSUPPORT;
920 goto errout;
921 }
922
923 done:
924 spin_lock_irqsave(&vc->scq->skblock, flags);
925 skb_queue_tail(&vc->scq->pending, skb);
926
927 while ((skb = skb_dequeue(&vc->scq->pending))) {
928 if (push_on_scq(card, vc, skb)) {
929 skb_queue_head(&vc->scq->pending, skb);
930 break;
931 }
932 }
933 spin_unlock_irqrestore(&vc->scq->skblock, flags);
934
935 return 0;
936
937 errout:
938 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
939 skb->len, PCI_DMA_TODEVICE);
940 return error;
941 }
942
943 static unsigned long
944 get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
945 {
946 int i;
947
948 for (i = 0; i < card->scd_size; i++) {
949 if (!card->scd2vc[i]) {
950 card->scd2vc[i] = vc;
951 vc->scd_index = i;
952 return card->scd_base + i * SAR_SRAM_SCD_SIZE;
953 }
954 }
955 return 0;
956 }
957
958 static void
959 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
960 {
961 write_sram(card, scq->scd, scq->paddr);
962 write_sram(card, scq->scd + 1, 0x00000000);
963 write_sram(card, scq->scd + 2, 0xffffffff);
964 write_sram(card, scq->scd + 3, 0x00000000);
965 }
966
967 static void
968 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
969 {
970 return;
971 }
972
973 /*****************************************************************************/
974 /* */
975 /* RSQ Handling */
976 /* */
977 /*****************************************************************************/
978
979 static int
980 init_rsq(struct idt77252_dev *card)
981 {
982 struct rsq_entry *rsqe;
983
984 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
985 &card->rsq.paddr);
986 if (card->rsq.base == NULL) {
987 printk("%s: can't allocate RSQ.\n", card->name);
988 return -1;
989 }
990 memset(card->rsq.base, 0, RSQSIZE);
991
992 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
993 card->rsq.next = card->rsq.last;
994 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
995 rsqe->word_4 = 0;
996
997 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
998 SAR_REG_RSQH);
999 writel(card->rsq.paddr, SAR_REG_RSQB);
1000
1001 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
1002 (unsigned long) card->rsq.base,
1003 readl(SAR_REG_RSQB));
1004 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
1005 card->name,
1006 readl(SAR_REG_RSQH),
1007 readl(SAR_REG_RSQB),
1008 readl(SAR_REG_RSQT));
1009
1010 return 0;
1011 }
1012
1013 static void
1014 deinit_rsq(struct idt77252_dev *card)
1015 {
1016 pci_free_consistent(card->pcidev, RSQSIZE,
1017 card->rsq.base, card->rsq.paddr);
1018 }
1019
1020 static void
1021 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1022 {
1023 struct atm_vcc *vcc;
1024 struct sk_buff *skb;
1025 struct rx_pool *rpp;
1026 struct vc_map *vc;
1027 u32 header, vpi, vci;
1028 u32 stat;
1029 int i;
1030
1031 stat = le32_to_cpu(rsqe->word_4);
1032
1033 if (stat & SAR_RSQE_IDLE) {
1034 RXPRINTK("%s: message about inactive connection.\n",
1035 card->name);
1036 return;
1037 }
1038
1039 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1040 if (skb == NULL) {
1041 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1042 <<<<<<< HEAD:drivers/atm/idt77252.c
1043 card->name, __FUNCTION__,
1044 =======
1045 card->name, __func__,
1046 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/atm/idt77252.c
1047 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1048 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1049 return;
1050 }
1051
1052 header = le32_to_cpu(rsqe->word_1);
1053 vpi = (header >> 16) & 0x00ff;
1054 vci = (header >> 0) & 0xffff;
1055
1056 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1057 card->name, vpi, vci, skb, skb->data);
1058
1059 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1060 printk("%s: SDU received for out-of-range vc %u.%u\n",
1061 card->name, vpi, vci);
1062 recycle_rx_skb(card, skb);
1063 return;
1064 }
1065
1066 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1067 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1068 printk("%s: SDU received on non RX vc %u.%u\n",
1069 card->name, vpi, vci);
1070 recycle_rx_skb(card, skb);
1071 return;
1072 }
1073
1074 vcc = vc->rx_vcc;
1075
1076 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb),
1077 skb_end_pointer(skb) - skb->data,
1078 PCI_DMA_FROMDEVICE);
1079
1080 if ((vcc->qos.aal == ATM_AAL0) ||
1081 (vcc->qos.aal == ATM_AAL34)) {
1082 struct sk_buff *sb;
1083 unsigned char *cell;
1084 u32 aal0;
1085
1086 cell = skb->data;
1087 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1088 if ((sb = dev_alloc_skb(64)) == NULL) {
1089 printk("%s: Can't allocate buffers for aal0.\n",
1090 card->name);
1091 atomic_add(i, &vcc->stats->rx_drop);
1092 break;
1093 }
1094 if (!atm_charge(vcc, sb->truesize)) {
1095 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1096 card->name);
1097 atomic_add(i - 1, &vcc->stats->rx_drop);
1098 dev_kfree_skb(sb);
1099 break;
1100 }
1101 aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1102 (vci << ATM_HDR_VCI_SHIFT);
1103 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1104 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
1105
1106 *((u32 *) sb->data) = aal0;
1107 skb_put(sb, sizeof(u32));
1108 memcpy(skb_put(sb, ATM_CELL_PAYLOAD),
1109 cell, ATM_CELL_PAYLOAD);
1110
1111 ATM_SKB(sb)->vcc = vcc;
1112 __net_timestamp(sb);
1113 vcc->push(vcc, sb);
1114 atomic_inc(&vcc->stats->rx);
1115
1116 cell += ATM_CELL_PAYLOAD;
1117 }
1118
1119 recycle_rx_skb(card, skb);
1120 return;
1121 }
1122 if (vcc->qos.aal != ATM_AAL5) {
1123 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1124 card->name, vcc->qos.aal);
1125 recycle_rx_skb(card, skb);
1126 return;
1127 }
1128 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1129
1130 rpp = &vc->rcv.rx_pool;
1131
1132 rpp->len += skb->len;
1133 if (!rpp->count++)
1134 rpp->first = skb;
1135 *rpp->last = skb;
1136 rpp->last = &skb->next;
1137
1138 if (stat & SAR_RSQE_EPDU) {
1139 unsigned char *l1l2;
1140 unsigned int len;
1141
1142 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1143
1144 len = (l1l2[0] << 8) | l1l2[1];
1145 len = len ? len : 0x10000;
1146
1147 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1148
1149 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1150 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1151 "(CDC: %08x)\n",
1152 card->name, len, rpp->len, readl(SAR_REG_CDC));
1153 recycle_rx_pool_skb(card, rpp);
1154 atomic_inc(&vcc->stats->rx_err);
1155 return;
1156 }
1157 if (stat & SAR_RSQE_CRC) {
1158 RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1159 recycle_rx_pool_skb(card, rpp);
1160 atomic_inc(&vcc->stats->rx_err);
1161 return;
1162 }
1163 if (rpp->count > 1) {
1164 struct sk_buff *sb;
1165
1166 skb = dev_alloc_skb(rpp->len);
1167 if (!skb) {
1168 RXPRINTK("%s: Can't alloc RX skb.\n",
1169 card->name);
1170 recycle_rx_pool_skb(card, rpp);
1171 atomic_inc(&vcc->stats->rx_err);
1172 return;
1173 }
1174 if (!atm_charge(vcc, skb->truesize)) {
1175 recycle_rx_pool_skb(card, rpp);
1176 dev_kfree_skb(skb);
1177 return;
1178 }
1179 sb = rpp->first;
1180 for (i = 0; i < rpp->count; i++) {
1181 memcpy(skb_put(skb, sb->len),
1182 sb->data, sb->len);
1183 sb = sb->next;
1184 }
1185
1186 recycle_rx_pool_skb(card, rpp);
1187
1188 skb_trim(skb, len);
1189 ATM_SKB(skb)->vcc = vcc;
1190 __net_timestamp(skb);
1191
1192 vcc->push(vcc, skb);
1193 atomic_inc(&vcc->stats->rx);
1194
1195 return;
1196 }
1197
1198 skb->next = NULL;
1199 flush_rx_pool(card, rpp);
1200
1201 if (!atm_charge(vcc, skb->truesize)) {
1202 recycle_rx_skb(card, skb);
1203 return;
1204 }
1205
1206 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1207 skb_end_pointer(skb) - skb->data,
1208 PCI_DMA_FROMDEVICE);
1209 sb_pool_remove(card, skb);
1210
1211 skb_trim(skb, len);
1212 ATM_SKB(skb)->vcc = vcc;
1213 __net_timestamp(skb);
1214
1215 vcc->push(vcc, skb);
1216 atomic_inc(&vcc->stats->rx);
1217
1218 if (skb->truesize > SAR_FB_SIZE_3)
1219 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1220 else if (skb->truesize > SAR_FB_SIZE_2)
1221 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1222 else if (skb->truesize > SAR_FB_SIZE_1)
1223 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1224 else
1225 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1226 return;
1227 }
1228 }
1229
1230 static void
1231 idt77252_rx(struct idt77252_dev *card)
1232 {
1233 struct rsq_entry *rsqe;
1234
1235 if (card->rsq.next == card->rsq.last)
1236 rsqe = card->rsq.base;
1237 else
1238 rsqe = card->rsq.next + 1;
1239
1240 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1241 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1242 return;
1243 }
1244
1245 do {
1246 dequeue_rx(card, rsqe);
1247 rsqe->word_4 = 0;
1248 card->rsq.next = rsqe;
1249 if (card->rsq.next == card->rsq.last)
1250 rsqe = card->rsq.base;
1251 else
1252 rsqe = card->rsq.next + 1;
1253 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1254
1255 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1256 SAR_REG_RSQH);
1257 }
1258
1259 static void
1260 idt77252_rx_raw(struct idt77252_dev *card)
1261 {
1262 struct sk_buff *queue;
1263 u32 head, tail;
1264 struct atm_vcc *vcc;
1265 struct vc_map *vc;
1266 struct sk_buff *sb;
1267
1268 if (card->raw_cell_head == NULL) {
1269 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1270 card->raw_cell_head = sb_pool_skb(card, handle);
1271 }
1272
1273 queue = card->raw_cell_head;
1274 if (!queue)
1275 return;
1276
1277 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1278 tail = readl(SAR_REG_RAWCT);
1279
1280 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue),
1281 skb_end_pointer(queue) - queue->head - 16,
1282 PCI_DMA_FROMDEVICE);
1283
1284 while (head != tail) {
1285 unsigned int vpi, vci, pti;
1286 u32 header;
1287
1288 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1289
1290 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1291 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1292 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1293
1294 #ifdef CONFIG_ATM_IDT77252_DEBUG
1295 if (debug & DBG_RAW_CELL) {
1296 int i;
1297
1298 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1299 card->name, (header >> 28) & 0x000f,
1300 (header >> 20) & 0x00ff,
1301 (header >> 4) & 0xffff,
1302 (header >> 1) & 0x0007,
1303 (header >> 0) & 0x0001);
1304 for (i = 16; i < 64; i++)
1305 printk(" %02x", queue->data[i]);
1306 printk("\n");
1307 }
1308 #endif
1309
1310 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1311 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1312 card->name, vpi, vci);
1313 goto drop;
1314 }
1315
1316 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1317 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1318 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1319 card->name, vpi, vci);
1320 goto drop;
1321 }
1322
1323 vcc = vc->rx_vcc;
1324
1325 if (vcc->qos.aal != ATM_AAL0) {
1326 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1327 card->name, vpi, vci);
1328 atomic_inc(&vcc->stats->rx_drop);
1329 goto drop;
1330 }
1331
1332 if ((sb = dev_alloc_skb(64)) == NULL) {
1333 printk("%s: Can't allocate buffers for AAL0.\n",
1334 card->name);
1335 atomic_inc(&vcc->stats->rx_err);
1336 goto drop;
1337 }
1338
1339 if (!atm_charge(vcc, sb->truesize)) {
1340 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1341 card->name);
1342 dev_kfree_skb(sb);
1343 goto drop;
1344 }
1345
1346 *((u32 *) sb->data) = header;
1347 skb_put(sb, sizeof(u32));
1348 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]),
1349 ATM_CELL_PAYLOAD);
1350
1351 ATM_SKB(sb)->vcc = vcc;
1352 __net_timestamp(sb);
1353 vcc->push(vcc, sb);
1354 atomic_inc(&vcc->stats->rx);
1355
1356 drop:
1357 skb_pull(queue, 64);
1358
1359 head = IDT77252_PRV_PADDR(queue)
1360 + (queue->data - queue->head - 16);
1361
1362 if (queue->len < 128) {
1363 struct sk_buff *next;
1364 u32 handle;
1365
1366 head = le32_to_cpu(*(u32 *) &queue->data[0]);
1367 handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1368
1369 next = sb_pool_skb(card, handle);
1370 recycle_rx_skb(card, queue);
1371
1372 if (next) {
1373 card->raw_cell_head = next;
1374 queue = card->raw_cell_head;
1375 pci_dma_sync_single_for_cpu(card->pcidev,
1376 IDT77252_PRV_PADDR(queue),
1377 (skb_end_pointer(queue) -
1378 queue->data),
1379 PCI_DMA_FROMDEVICE);
1380 } else {
1381 card->raw_cell_head = NULL;
1382 printk("%s: raw cell queue overrun\n",
1383 card->name);
1384 break;
1385 }
1386 }
1387 }
1388 }
1389
1390
1391 /*****************************************************************************/
1392 /* */
1393 /* TSQ Handling */
1394 /* */
1395 /*****************************************************************************/
1396
1397 static int
1398 init_tsq(struct idt77252_dev *card)
1399 {
1400 struct tsq_entry *tsqe;
1401
1402 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
1403 &card->tsq.paddr);
1404 if (card->tsq.base == NULL) {
1405 printk("%s: can't allocate TSQ.\n", card->name);
1406 return -1;
1407 }
1408 memset(card->tsq.base, 0, TSQSIZE);
1409
1410 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1411 card->tsq.next = card->tsq.last;
1412 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1413 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1414
1415 writel(card->tsq.paddr, SAR_REG_TSQB);
1416 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1417 SAR_REG_TSQH);
1418
1419 return 0;
1420 }
1421
1422 static void
1423 deinit_tsq(struct idt77252_dev *card)
1424 {
1425 pci_free_consistent(card->pcidev, TSQSIZE,
1426 card->tsq.base, card->tsq.paddr);
1427 }
1428
1429 static void
1430 idt77252_tx(struct idt77252_dev *card)
1431 {
1432 struct tsq_entry *tsqe;
1433 unsigned int vpi, vci;
1434 struct vc_map *vc;
1435 u32 conn, stat;
1436
1437 if (card->tsq.next == card->tsq.last)
1438 tsqe = card->tsq.base;
1439 else
1440 tsqe = card->tsq.next + 1;
1441
1442 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
1443 card->tsq.base, card->tsq.next, card->tsq.last);
1444 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1445 readl(SAR_REG_TSQB),
1446 readl(SAR_REG_TSQT),
1447 readl(SAR_REG_TSQH));
1448
1449 stat = le32_to_cpu(tsqe->word_2);
1450
1451 if (stat & SAR_TSQE_INVALID)
1452 return;
1453
1454 do {
1455 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1456 le32_to_cpu(tsqe->word_1),
1457 le32_to_cpu(tsqe->word_2));
1458
1459 switch (stat & SAR_TSQE_TYPE) {
1460 case SAR_TSQE_TYPE_TIMER:
1461 TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1462 break;
1463
1464 case SAR_TSQE_TYPE_IDLE:
1465
1466 conn = le32_to_cpu(tsqe->word_1);
1467
1468 if (SAR_TSQE_TAG(stat) == 0x10) {
1469 #ifdef NOTDEF
1470 printk("%s: Connection %d halted.\n",
1471 card->name,
1472 le32_to_cpu(tsqe->word_1) & 0x1fff);
1473 #endif
1474 break;
1475 }
1476
1477 vc = card->vcs[conn & 0x1fff];
1478 if (!vc) {
1479 printk("%s: could not find VC from conn %d\n",
1480 card->name, conn & 0x1fff);
1481 break;
1482 }
1483
1484 printk("%s: Connection %d IDLE.\n",
1485 card->name, vc->index);
1486
1487 set_bit(VCF_IDLE, &vc->flags);
1488 break;
1489
1490 case SAR_TSQE_TYPE_TSR:
1491
1492 conn = le32_to_cpu(tsqe->word_1);
1493
1494 vc = card->vcs[conn & 0x1fff];
1495 if (!vc) {
1496 printk("%s: no VC at index %d\n",
1497 card->name,
1498 le32_to_cpu(tsqe->word_1) & 0x1fff);
1499 break;
1500 }
1501
1502 drain_scq(card, vc);
1503 break;
1504
1505 case SAR_TSQE_TYPE_TBD_COMP:
1506
1507 conn = le32_to_cpu(tsqe->word_1);
1508
1509 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1510 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1511
1512 if (vpi >= (1 << card->vpibits) ||
1513 vci >= (1 << card->vcibits)) {
1514 printk("%s: TBD complete: "
1515 "out of range VPI.VCI %u.%u\n",
1516 card->name, vpi, vci);
1517 break;
1518 }
1519
1520 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1521 if (!vc) {
1522 printk("%s: TBD complete: "
1523 "no VC at VPI.VCI %u.%u\n",
1524 card->name, vpi, vci);
1525 break;
1526 }
1527
1528 drain_scq(card, vc);
1529 break;
1530 }
1531
1532 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1533
1534 card->tsq.next = tsqe;
1535 if (card->tsq.next == card->tsq.last)
1536 tsqe = card->tsq.base;
1537 else
1538 tsqe = card->tsq.next + 1;
1539
1540 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1541 card->tsq.base, card->tsq.next, card->tsq.last);
1542
1543 stat = le32_to_cpu(tsqe->word_2);
1544
1545 } while (!(stat & SAR_TSQE_INVALID));
1546
1547 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1548 SAR_REG_TSQH);
1549
1550 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1551 card->index, readl(SAR_REG_TSQH),
1552 readl(SAR_REG_TSQT), card->tsq.next);
1553 }
1554
1555
1556 static void
1557 tst_timer(unsigned long data)
1558 {
1559 struct idt77252_dev *card = (struct idt77252_dev *)data;
1560 unsigned long base, idle, jump;
1561 unsigned long flags;
1562 u32 pc;
1563 int e;
1564
1565 spin_lock_irqsave(&card->tst_lock, flags);
1566
1567 base = card->tst[card->tst_index];
1568 idle = card->tst[card->tst_index ^ 1];
1569
1570 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1571 jump = base + card->tst_size - 2;
1572
1573 pc = readl(SAR_REG_NOW) >> 2;
1574 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1575 mod_timer(&card->tst_timer, jiffies + 1);
1576 goto out;
1577 }
1578
1579 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1580
1581 card->tst_index ^= 1;
1582 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1583
1584 base = card->tst[card->tst_index];
1585 idle = card->tst[card->tst_index ^ 1];
1586
1587 for (e = 0; e < card->tst_size - 2; e++) {
1588 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1589 write_sram(card, idle + e,
1590 card->soft_tst[e].tste & TSTE_MASK);
1591 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1592 }
1593 }
1594 }
1595
1596 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1597
1598 for (e = 0; e < card->tst_size - 2; e++) {
1599 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1600 write_sram(card, idle + e,
1601 card->soft_tst[e].tste & TSTE_MASK);
1602 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1603 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1604 }
1605 }
1606
1607 jump = base + card->tst_size - 2;
1608
1609 write_sram(card, jump, TSTE_OPC_NULL);
1610 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1611
1612 mod_timer(&card->tst_timer, jiffies + 1);
1613 }
1614
1615 out:
1616 spin_unlock_irqrestore(&card->tst_lock, flags);
1617 }
1618
1619 static int
1620 __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1621 int n, unsigned int opc)
1622 {
1623 unsigned long cl, avail;
1624 unsigned long idle;
1625 int e, r;
1626 u32 data;
1627
1628 avail = card->tst_size - 2;
1629 for (e = 0; e < avail; e++) {
1630 if (card->soft_tst[e].vc == NULL)
1631 break;
1632 }
1633 if (e >= avail) {
1634 printk("%s: No free TST entries found\n", card->name);
1635 return -1;
1636 }
1637
1638 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1639 card->name, vc ? vc->index : -1, e);
1640
1641 r = n;
1642 cl = avail;
1643 data = opc & TSTE_OPC_MASK;
1644 if (vc && (opc != TSTE_OPC_NULL))
1645 data = opc | vc->index;
1646
1647 idle = card->tst[card->tst_index ^ 1];
1648
1649 /*
1650 * Fill Soft TST.
1651 */
1652 while (r > 0) {
1653 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1654 if (vc)
1655 card->soft_tst[e].vc = vc;
1656 else
1657 card->soft_tst[e].vc = (void *)-1;
1658
1659 card->soft_tst[e].tste = data;
1660 if (timer_pending(&card->tst_timer))
1661 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1662 else {
1663 write_sram(card, idle + e, data);
1664 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1665 }
1666
1667 cl -= card->tst_size;
1668 r--;
1669 }
1670
1671 if (++e == avail)
1672 e = 0;
1673 cl += n;
1674 }
1675
1676 return 0;
1677 }
1678
1679 static int
1680 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1681 {
1682 unsigned long flags;
1683 int res;
1684
1685 spin_lock_irqsave(&card->tst_lock, flags);
1686
1687 res = __fill_tst(card, vc, n, opc);
1688
1689 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1690 if (!timer_pending(&card->tst_timer))
1691 mod_timer(&card->tst_timer, jiffies + 1);
1692
1693 spin_unlock_irqrestore(&card->tst_lock, flags);
1694 return res;
1695 }
1696
1697 static int
1698 __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1699 {
1700 unsigned long idle;
1701 int e;
1702
1703 idle = card->tst[card->tst_index ^ 1];
1704
1705 for (e = 0; e < card->tst_size - 2; e++) {
1706 if (card->soft_tst[e].vc == vc) {
1707 card->soft_tst[e].vc = NULL;
1708
1709 card->soft_tst[e].tste = TSTE_OPC_VAR;
1710 if (timer_pending(&card->tst_timer))
1711 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1712 else {
1713 write_sram(card, idle + e, TSTE_OPC_VAR);
1714 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1715 }
1716 }
1717 }
1718
1719 return 0;
1720 }
1721
1722 static int
1723 clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1724 {
1725 unsigned long flags;
1726 int res;
1727
1728 spin_lock_irqsave(&card->tst_lock, flags);
1729
1730 res = __clear_tst(card, vc);
1731
1732 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1733 if (!timer_pending(&card->tst_timer))
1734 mod_timer(&card->tst_timer, jiffies + 1);
1735
1736 spin_unlock_irqrestore(&card->tst_lock, flags);
1737 return res;
1738 }
1739
1740 static int
1741 change_tst(struct idt77252_dev *card, struct vc_map *vc,
1742 int n, unsigned int opc)
1743 {
1744 unsigned long flags;
1745 int res;
1746
1747 spin_lock_irqsave(&card->tst_lock, flags);
1748
1749 __clear_tst(card, vc);
1750 res = __fill_tst(card, vc, n, opc);
1751
1752 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1753 if (!timer_pending(&card->tst_timer))
1754 mod_timer(&card->tst_timer, jiffies + 1);
1755
1756 spin_unlock_irqrestore(&card->tst_lock, flags);
1757 return res;
1758 }
1759
1760
1761 static int
1762 set_tct(struct idt77252_dev *card, struct vc_map *vc)
1763 {
1764 unsigned long tct;
1765
1766 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1767
1768 switch (vc->class) {
1769 case SCHED_CBR:
1770 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1771 card->name, tct, vc->scq->scd);
1772
1773 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1774 write_sram(card, tct + 1, 0);
1775 write_sram(card, tct + 2, 0);
1776 write_sram(card, tct + 3, 0);
1777 write_sram(card, tct + 4, 0);
1778 write_sram(card, tct + 5, 0);
1779 write_sram(card, tct + 6, 0);
1780 write_sram(card, tct + 7, 0);
1781 break;
1782
1783 case SCHED_UBR:
1784 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1785 card->name, tct, vc->scq->scd);
1786
1787 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1788 write_sram(card, tct + 1, 0);
1789 write_sram(card, tct + 2, TCT_TSIF);
1790 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1791 write_sram(card, tct + 4, 0);
1792 write_sram(card, tct + 5, vc->init_er);
1793 write_sram(card, tct + 6, 0);
1794 write_sram(card, tct + 7, TCT_FLAG_UBR);
1795 break;
1796
1797 case SCHED_VBR:
1798 case SCHED_ABR:
1799 default:
1800 return -ENOSYS;
1801 }
1802
1803 return 0;
1804 }
1805
1806 /*****************************************************************************/
1807 /* */
1808 /* FBQ Handling */
1809 /* */
1810 /*****************************************************************************/
1811
1812 static __inline__ int
1813 idt77252_fbq_level(struct idt77252_dev *card, int queue)
1814 {
1815 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1816 }
1817
1818 static __inline__ int
1819 idt77252_fbq_full(struct idt77252_dev *card, int queue)
1820 {
1821 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1822 }
1823
1824 static int
1825 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1826 {
1827 unsigned long flags;
1828 u32 handle;
1829 u32 addr;
1830
1831 skb->data = skb->head;
1832 skb_reset_tail_pointer(skb);
1833 skb->len = 0;
1834
1835 skb_reserve(skb, 16);
1836
1837 switch (queue) {
1838 case 0:
1839 skb_put(skb, SAR_FB_SIZE_0);
1840 break;
1841 case 1:
1842 skb_put(skb, SAR_FB_SIZE_1);
1843 break;
1844 case 2:
1845 skb_put(skb, SAR_FB_SIZE_2);
1846 break;
1847 case 3:
1848 skb_put(skb, SAR_FB_SIZE_3);
1849 break;
1850 default:
1851 return -1;
1852 }
1853
1854 if (idt77252_fbq_full(card, queue))
1855 return -1;
1856
1857 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1858
1859 handle = IDT77252_PRV_POOL(skb);
1860 addr = IDT77252_PRV_PADDR(skb);
1861
1862 spin_lock_irqsave(&card->cmd_lock, flags);
1863 writel(handle, card->fbq[queue]);
1864 writel(addr, card->fbq[queue]);
1865 spin_unlock_irqrestore(&card->cmd_lock, flags);
1866
1867 return 0;
1868 }
1869
1870 static void
1871 add_rx_skb(struct idt77252_dev *card, int queue,
1872 unsigned int size, unsigned int count)
1873 {
1874 struct sk_buff *skb;
1875 dma_addr_t paddr;
1876 u32 handle;
1877
1878 while (count--) {
1879 skb = dev_alloc_skb(size);
1880 if (!skb)
1881 return;
1882
1883 if (sb_pool_add(card, skb, queue)) {
1884 <<<<<<< HEAD:drivers/atm/idt77252.c
1885 printk("%s: SB POOL full\n", __FUNCTION__);
1886 =======
1887 printk("%s: SB POOL full\n", __func__);
1888 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/atm/idt77252.c
1889 goto outfree;
1890 }
1891
1892 paddr = pci_map_single(card->pcidev, skb->data,
1893 skb_end_pointer(skb) - skb->data,
1894 PCI_DMA_FROMDEVICE);
1895 IDT77252_PRV_PADDR(skb) = paddr;
1896
1897 if (push_rx_skb(card, skb, queue)) {
1898 <<<<<<< HEAD:drivers/atm/idt77252.c
1899 printk("%s: FB QUEUE full\n", __FUNCTION__);
1900 =======
1901 printk("%s: FB QUEUE full\n", __func__);
1902 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/atm/idt77252.c
1903 goto outunmap;
1904 }
1905 }
1906
1907 return;
1908
1909 outunmap:
1910 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1911 skb_end_pointer(skb) - skb->data, PCI_DMA_FROMDEVICE);
1912
1913 handle = IDT77252_PRV_POOL(skb);
1914 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1915
1916 outfree:
1917 dev_kfree_skb(skb);
1918 }
1919
1920
1921 static void
1922 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1923 {
1924 u32 handle = IDT77252_PRV_POOL(skb);
1925 int err;
1926
1927 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb),
1928 skb_end_pointer(skb) - skb->data,
1929 PCI_DMA_FROMDEVICE);
1930
1931 err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1932 if (err) {
1933 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1934 skb_end_pointer(skb) - skb->data,
1935 PCI_DMA_FROMDEVICE);
1936 sb_pool_remove(card, skb);
1937 dev_kfree_skb(skb);
1938 }
1939 }
1940
1941 static void
1942 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1943 {
1944 rpp->len = 0;
1945 rpp->count = 0;
1946 rpp->first = NULL;
1947 rpp->last = &rpp->first;
1948 }
1949
1950 static void
1951 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1952 {
1953 struct sk_buff *skb, *next;
1954 int i;
1955
1956 skb = rpp->first;
1957 for (i = 0; i < rpp->count; i++) {
1958 next = skb->next;
1959 skb->next = NULL;
1960 recycle_rx_skb(card, skb);
1961 skb = next;
1962 }
1963 flush_rx_pool(card, rpp);
1964 }
1965
1966 /*****************************************************************************/
1967 /* */
1968 /* ATM Interface */
1969 /* */
1970 /*****************************************************************************/
1971
1972 static void
1973 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1974 {
1975 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1976 }
1977
1978 static unsigned char
1979 idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1980 {
1981 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1982 }
1983
1984 static inline int
1985 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1986 {
1987 struct atm_dev *dev = vcc->dev;
1988 struct idt77252_dev *card = dev->dev_data;
1989 struct vc_map *vc = vcc->dev_data;
1990 int err;
1991
1992 if (vc == NULL) {
1993 printk("%s: NULL connection in send().\n", card->name);
1994 atomic_inc(&vcc->stats->tx_err);
1995 dev_kfree_skb(skb);
1996 return -EINVAL;
1997 }
1998 if (!test_bit(VCF_TX, &vc->flags)) {
1999 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
2000 atomic_inc(&vcc->stats->tx_err);
2001 dev_kfree_skb(skb);
2002 return -EINVAL;
2003 }
2004
2005 switch (vcc->qos.aal) {
2006 case ATM_AAL0:
2007 case ATM_AAL1:
2008 case ATM_AAL5:
2009 break;
2010 default:
2011 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2012 atomic_inc(&vcc->stats->tx_err);
2013 dev_kfree_skb(skb);
2014 return -EINVAL;
2015 }
2016
2017 if (skb_shinfo(skb)->nr_frags != 0) {
2018 printk("%s: No scatter-gather yet.\n", card->name);
2019 atomic_inc(&vcc->stats->tx_err);
2020 dev_kfree_skb(skb);
2021 return -EINVAL;
2022 }
2023 ATM_SKB(skb)->vcc = vcc;
2024
2025 err = queue_skb(card, vc, skb, oam);
2026 if (err) {
2027 atomic_inc(&vcc->stats->tx_err);
2028 dev_kfree_skb(skb);
2029 return err;
2030 }
2031
2032 return 0;
2033 }
2034
2035 int
2036 idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
2037 {
2038 return idt77252_send_skb(vcc, skb, 0);
2039 }
2040
2041 static int
2042 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2043 {
2044 struct atm_dev *dev = vcc->dev;
2045 struct idt77252_dev *card = dev->dev_data;
2046 struct sk_buff *skb;
2047
2048 skb = dev_alloc_skb(64);
2049 if (!skb) {
2050 printk("%s: Out of memory in send_oam().\n", card->name);
2051 atomic_inc(&vcc->stats->tx_err);
2052 return -ENOMEM;
2053 }
2054 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
2055
2056 memcpy(skb_put(skb, 52), cell, 52);
2057
2058 return idt77252_send_skb(vcc, skb, 1);
2059 }
2060
2061 static __inline__ unsigned int
2062 idt77252_fls(unsigned int x)
2063 {
2064 int r = 1;
2065
2066 if (x == 0)
2067 return 0;
2068 if (x & 0xffff0000) {
2069 x >>= 16;
2070 r += 16;
2071 }
2072 if (x & 0xff00) {
2073 x >>= 8;
2074 r += 8;
2075 }
2076 if (x & 0xf0) {
2077 x >>= 4;
2078 r += 4;
2079 }
2080 if (x & 0xc) {
2081 x >>= 2;
2082 r += 2;
2083 }
2084 if (x & 0x2)
2085 r += 1;
2086 return r;
2087 }
2088
2089 static u16
2090 idt77252_int_to_atmfp(unsigned int rate)
2091 {
2092 u16 m, e;
2093
2094 if (rate == 0)
2095 return 0;
2096 e = idt77252_fls(rate) - 1;
2097 if (e < 9)
2098 m = (rate - (1 << e)) << (9 - e);
2099 else if (e == 9)
2100 m = (rate - (1 << e));
2101 else /* e > 9 */
2102 m = (rate - (1 << e)) >> (e - 9);
2103 return 0x4000 | (e << 9) | m;
2104 }
2105
2106 static u8
2107 idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2108 {
2109 u16 afp;
2110
2111 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2112 if (pcr < 0)
2113 return rate_to_log[(afp >> 5) & 0x1ff];
2114 return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2115 }
2116
2117 static void
2118 idt77252_est_timer(unsigned long data)
2119 {
2120 struct vc_map *vc = (struct vc_map *)data;
2121 struct idt77252_dev *card = vc->card;
2122 struct rate_estimator *est;
2123 unsigned long flags;
2124 u32 rate, cps;
2125 u64 ncells;
2126 u8 lacr;
2127
2128 spin_lock_irqsave(&vc->lock, flags);
2129 est = vc->estimator;
2130 if (!est)
2131 goto out;
2132
2133 ncells = est->cells;
2134
2135 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2136 est->last_cells = ncells;
2137 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2138 est->cps = (est->avcps + 0x1f) >> 5;
2139
2140 cps = est->cps;
2141 if (cps < (est->maxcps >> 4))
2142 cps = est->maxcps >> 4;
2143
2144 lacr = idt77252_rate_logindex(card, cps);
2145 if (lacr > vc->max_er)
2146 lacr = vc->max_er;
2147
2148 if (lacr != vc->lacr) {
2149 vc->lacr = lacr;
2150 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2151 }
2152
2153 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2154 add_timer(&est->timer);
2155
2156 out:
2157 spin_unlock_irqrestore(&vc->lock, flags);
2158 }
2159
2160 static struct rate_estimator *
2161 idt77252_init_est(struct vc_map *vc, int pcr)
2162 {
2163 struct rate_estimator *est;
2164
2165 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2166 if (!est)
2167 return NULL;
2168 est->maxcps = pcr < 0 ? -pcr : pcr;
2169 est->cps = est->maxcps;
2170 est->avcps = est->cps << 5;
2171
2172 est->interval = 2; /* XXX: make this configurable */
2173 est->ewma_log = 2; /* XXX: make this configurable */
2174 init_timer(&est->timer);
2175 est->timer.data = (unsigned long)vc;
2176 est->timer.function = idt77252_est_timer;
2177
2178 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2179 add_timer(&est->timer);
2180
2181 return est;
2182 }
2183
2184 static int
2185 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2186 struct atm_vcc *vcc, struct atm_qos *qos)
2187 {
2188 int tst_free, tst_used, tst_entries;
2189 unsigned long tmpl, modl;
2190 int tcr, tcra;
2191
2192 if ((qos->txtp.max_pcr == 0) &&
2193 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2194 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2195 card->name);
2196 return -EINVAL;
2197 }
2198
2199 tst_used = 0;
2200 tst_free = card->tst_free;
2201 if (test_bit(VCF_TX, &vc->flags))
2202 tst_used = vc->ntste;
2203 tst_free += tst_used;
2204
2205 tcr = atm_pcr_goal(&qos->txtp);
2206 tcra = tcr >= 0 ? tcr : -tcr;
2207
2208 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2209
2210 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2211 modl = tmpl % (unsigned long)card->utopia_pcr;
2212
2213 tst_entries = (int) (tmpl / card->utopia_pcr);
2214 if (tcr > 0) {
2215 if (modl > 0)
2216 tst_entries++;
2217 } else if (tcr == 0) {
2218 tst_entries = tst_free - SAR_TST_RESERVED;
2219 if (tst_entries <= 0) {
2220 printk("%s: no CBR bandwidth free.\n", card->name);
2221 return -ENOSR;
2222 }
2223 }
2224
2225 if (tst_entries == 0) {
2226 printk("%s: selected CBR bandwidth < granularity.\n",
2227 card->name);
2228 return -EINVAL;
2229 }
2230
2231 if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2232 printk("%s: not enough CBR bandwidth free.\n", card->name);
2233 return -ENOSR;
2234 }
2235
2236 vc->ntste = tst_entries;
2237
2238 card->tst_free = tst_free - tst_entries;
2239 if (test_bit(VCF_TX, &vc->flags)) {
2240 if (tst_used == tst_entries)
2241 return 0;
2242
2243 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2244 card->name, tst_used, tst_entries);
2245 change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2246 return 0;
2247 }
2248
2249 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2250 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2251 return 0;
2252 }
2253
2254 static int
2255 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2256 struct atm_vcc *vcc, struct atm_qos *qos)
2257 {
2258 unsigned long flags;
2259 int tcr;
2260
2261 spin_lock_irqsave(&vc->lock, flags);
2262 if (vc->estimator) {
2263 del_timer(&vc->estimator->timer);
2264 kfree(vc->estimator);
2265 vc->estimator = NULL;
2266 }
2267 spin_unlock_irqrestore(&vc->lock, flags);
2268
2269 tcr = atm_pcr_goal(&qos->txtp);
2270 if (tcr == 0)
2271 tcr = card->link_pcr;
2272
2273 vc->estimator = idt77252_init_est(vc, tcr);
2274
2275 vc->class = SCHED_UBR;
2276 vc->init_er = idt77252_rate_logindex(card, tcr);
2277 vc->lacr = vc->init_er;
2278 if (tcr < 0)
2279 vc->max_er = vc->init_er;
2280 else
2281 vc->max_er = 0xff;
2282
2283 return 0;
2284 }
2285
2286 static int
2287 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2288 struct atm_vcc *vcc, struct atm_qos *qos)
2289 {
2290 int error;
2291
2292 if (test_bit(VCF_TX, &vc->flags))
2293 return -EBUSY;
2294
2295 switch (qos->txtp.traffic_class) {
2296 case ATM_CBR:
2297 vc->class = SCHED_CBR;
2298 break;
2299
2300 case ATM_UBR:
2301 vc->class = SCHED_UBR;
2302 break;
2303
2304 case ATM_VBR:
2305 case ATM_ABR:
2306 default:
2307 return -EPROTONOSUPPORT;
2308 }
2309
2310 vc->scq = alloc_scq(card, vc->class);
2311 if (!vc->scq) {
2312 printk("%s: can't get SCQ.\n", card->name);
2313 return -ENOMEM;
2314 }
2315
2316 vc->scq->scd = get_free_scd(card, vc);
2317 if (vc->scq->scd == 0) {
2318 printk("%s: no SCD available.\n", card->name);
2319 free_scq(card, vc->scq);
2320 return -ENOMEM;
2321 }
2322
2323 fill_scd(card, vc->scq, vc->class);
2324
2325 if (set_tct(card, vc)) {
2326 printk("%s: class %d not supported.\n",
2327 card->name, qos->txtp.traffic_class);
2328
2329 card->scd2vc[vc->scd_index] = NULL;
2330 free_scq(card, vc->scq);
2331 return -EPROTONOSUPPORT;
2332 }
2333
2334 switch (vc->class) {
2335 case SCHED_CBR:
2336 error = idt77252_init_cbr(card, vc, vcc, qos);
2337 if (error) {
2338 card->scd2vc[vc->scd_index] = NULL;
2339 free_scq(card, vc->scq);
2340 return error;
2341 }
2342
2343 clear_bit(VCF_IDLE, &vc->flags);
2344 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2345 break;
2346
2347 case SCHED_UBR:
2348 error = idt77252_init_ubr(card, vc, vcc, qos);
2349 if (error) {
2350 card->scd2vc[vc->scd_index] = NULL;
2351 free_scq(card, vc->scq);
2352 return error;
2353 }
2354
2355 set_bit(VCF_IDLE, &vc->flags);
2356 break;
2357 }
2358
2359 vc->tx_vcc = vcc;
2360 set_bit(VCF_TX, &vc->flags);
2361 return 0;
2362 }
2363
2364 static int
2365 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2366 struct atm_vcc *vcc, struct atm_qos *qos)
2367 {
2368 unsigned long flags;
2369 unsigned long addr;
2370 u32 rcte = 0;
2371
2372 if (test_bit(VCF_RX, &vc->flags))
2373 return -EBUSY;
2374
2375 vc->rx_vcc = vcc;
2376 set_bit(VCF_RX, &vc->flags);
2377
2378 if ((vcc->vci == 3) || (vcc->vci == 4))
2379 return 0;
2380
2381 flush_rx_pool(card, &vc->rcv.rx_pool);
2382
2383 rcte |= SAR_RCTE_CONNECTOPEN;
2384 rcte |= SAR_RCTE_RAWCELLINTEN;
2385
2386 switch (qos->aal) {
2387 case ATM_AAL0:
2388 rcte |= SAR_RCTE_RCQ;
2389 break;
2390 case ATM_AAL1:
2391 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2392 break;
2393 case ATM_AAL34:
2394 rcte |= SAR_RCTE_AAL34;
2395 break;
2396 case ATM_AAL5:
2397 rcte |= SAR_RCTE_AAL5;
2398 break;
2399 default:
2400 rcte |= SAR_RCTE_RCQ;
2401 break;
2402 }
2403
2404 if (qos->aal != ATM_AAL5)
2405 rcte |= SAR_RCTE_FBP_1;
2406 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2407 rcte |= SAR_RCTE_FBP_3;
2408 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2409 rcte |= SAR_RCTE_FBP_2;
2410 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2411 rcte |= SAR_RCTE_FBP_1;
2412 else
2413 rcte |= SAR_RCTE_FBP_01;
2414
2415 addr = card->rct_base + (vc->index << 2);
2416
2417 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2418 write_sram(card, addr, rcte);
2419
2420 spin_lock_irqsave(&card->cmd_lock, flags);
2421 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2422 waitfor_idle(card);
2423 spin_unlock_irqrestore(&card->cmd_lock, flags);
2424
2425 return 0;
2426 }
2427
2428 static int
2429 idt77252_open(struct atm_vcc *vcc)
2430 {
2431 struct atm_dev *dev = vcc->dev;
2432 struct idt77252_dev *card = dev->dev_data;
2433 struct vc_map *vc;
2434 unsigned int index;
2435 unsigned int inuse;
2436 int error;
2437 int vci = vcc->vci;
2438 short vpi = vcc->vpi;
2439
2440 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2441 return 0;
2442
2443 if (vpi >= (1 << card->vpibits)) {
2444 printk("%s: unsupported VPI: %d\n", card->name, vpi);
2445 return -EINVAL;
2446 }
2447
2448 if (vci >= (1 << card->vcibits)) {
2449 printk("%s: unsupported VCI: %d\n", card->name, vci);
2450 return -EINVAL;
2451 }
2452
2453 set_bit(ATM_VF_ADDR, &vcc->flags);
2454
2455 mutex_lock(&card->mutex);
2456
2457 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2458
2459 switch (vcc->qos.aal) {
2460 case ATM_AAL0:
2461 case ATM_AAL1:
2462 case ATM_AAL5:
2463 break;
2464 default:
2465 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2466 mutex_unlock(&card->mutex);
2467 return -EPROTONOSUPPORT;
2468 }
2469
2470 index = VPCI2VC(card, vpi, vci);
2471 if (!card->vcs[index]) {
2472 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2473 if (!card->vcs[index]) {
2474 printk("%s: can't alloc vc in open()\n", card->name);
2475 mutex_unlock(&card->mutex);
2476 return -ENOMEM;
2477 }
2478 card->vcs[index]->card = card;
2479 card->vcs[index]->index = index;
2480
2481 spin_lock_init(&card->vcs[index]->lock);
2482 }
2483 vc = card->vcs[index];
2484
2485 vcc->dev_data = vc;
2486
2487 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2488 card->name, vc->index, vcc->vpi, vcc->vci,
2489 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2490 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2491 vcc->qos.rxtp.max_sdu);
2492
2493 inuse = 0;
2494 if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2495 test_bit(VCF_TX, &vc->flags))
2496 inuse = 1;
2497 if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2498 test_bit(VCF_RX, &vc->flags))
2499 inuse += 2;
2500
2501 if (inuse) {
2502 printk("%s: %s vci already in use.\n", card->name,
2503 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2504 mutex_unlock(&card->mutex);
2505 return -EADDRINUSE;
2506 }
2507
2508 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2509 error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2510 if (error) {
2511 mutex_unlock(&card->mutex);
2512 return error;
2513 }
2514 }
2515
2516 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2517 error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2518 if (error) {
2519 mutex_unlock(&card->mutex);
2520 return error;
2521 }
2522 }
2523
2524 set_bit(ATM_VF_READY, &vcc->flags);
2525
2526 mutex_unlock(&card->mutex);
2527 return 0;
2528 }
2529
2530 static void
2531 idt77252_close(struct atm_vcc *vcc)
2532 {
2533 struct atm_dev *dev = vcc->dev;
2534 struct idt77252_dev *card = dev->dev_data;
2535 struct vc_map *vc = vcc->dev_data;
2536 unsigned long flags;
2537 unsigned long addr;
2538 unsigned long timeout;
2539
2540 mutex_lock(&card->mutex);
2541
2542 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2543 card->name, vc->index, vcc->vpi, vcc->vci);
2544
2545 clear_bit(ATM_VF_READY, &vcc->flags);
2546
2547 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2548
2549 spin_lock_irqsave(&vc->lock, flags);
2550 clear_bit(VCF_RX, &vc->flags);
2551 vc->rx_vcc = NULL;
2552 spin_unlock_irqrestore(&vc->lock, flags);
2553
2554 if ((vcc->vci == 3) || (vcc->vci == 4))
2555 goto done;
2556
2557 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2558
2559 spin_lock_irqsave(&card->cmd_lock, flags);
2560 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2561 waitfor_idle(card);
2562 spin_unlock_irqrestore(&card->cmd_lock, flags);
2563
2564 if (vc->rcv.rx_pool.count) {
2565 DPRINTK("%s: closing a VC with pending rx buffers.\n",
2566 card->name);
2567
2568 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2569 }
2570 }
2571
2572 done:
2573 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2574
2575 spin_lock_irqsave(&vc->lock, flags);
2576 clear_bit(VCF_TX, &vc->flags);
2577 clear_bit(VCF_IDLE, &vc->flags);
2578 clear_bit(VCF_RSV, &vc->flags);
2579 vc->tx_vcc = NULL;
2580
2581 if (vc->estimator) {
2582 del_timer(&vc->estimator->timer);
2583 kfree(vc->estimator);
2584 vc->estimator = NULL;
2585 }
2586 spin_unlock_irqrestore(&vc->lock, flags);
2587
2588 timeout = 5 * 1000;
2589 while (atomic_read(&vc->scq->used) > 0) {
2590 timeout = msleep_interruptible(timeout);
2591 if (!timeout)
2592 break;
2593 }
2594 if (!timeout)
2595 printk("%s: SCQ drain timeout: %u used\n",
2596 card->name, atomic_read(&vc->scq->used));
2597
2598 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2599 clear_scd(card, vc->scq, vc->class);
2600
2601 if (vc->class == SCHED_CBR) {
2602 clear_tst(card, vc);
2603 card->tst_free += vc->ntste;
2604 vc->ntste = 0;
2605 }
2606
2607 card->scd2vc[vc->scd_index] = NULL;
2608 free_scq(card, vc->scq);
2609 }
2610
2611 mutex_unlock(&card->mutex);
2612 }
2613
2614 static int
2615 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2616 {
2617 struct atm_dev *dev = vcc->dev;
2618 struct idt77252_dev *card = dev->dev_data;
2619 struct vc_map *vc = vcc->dev_data;
2620 int error = 0;
2621
2622 mutex_lock(&card->mutex);
2623
2624 if (qos->txtp.traffic_class != ATM_NONE) {
2625 if (!test_bit(VCF_TX, &vc->flags)) {
2626 error = idt77252_init_tx(card, vc, vcc, qos);
2627 if (error)
2628 goto out;
2629 } else {
2630 switch (qos->txtp.traffic_class) {
2631 case ATM_CBR:
2632 error = idt77252_init_cbr(card, vc, vcc, qos);
2633 if (error)
2634 goto out;
2635 break;
2636
2637 case ATM_UBR:
2638 error = idt77252_init_ubr(card, vc, vcc, qos);
2639 if (error)
2640 goto out;
2641
2642 if (!test_bit(VCF_IDLE, &vc->flags)) {
2643 writel(TCMDQ_LACR | (vc->lacr << 16) |
2644 vc->index, SAR_REG_TCMDQ);
2645 }
2646 break;
2647
2648 case ATM_VBR:
2649 case ATM_ABR:
2650 error = -EOPNOTSUPP;
2651 goto out;
2652 }
2653 }
2654 }
2655
2656 if ((qos->rxtp.traffic_class != ATM_NONE) &&
2657 !test_bit(VCF_RX, &vc->flags)) {
2658 error = idt77252_init_rx(card, vc, vcc, qos);
2659 if (error)
2660 goto out;
2661 }
2662
2663 memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2664
2665 set_bit(ATM_VF_HASQOS, &vcc->flags);
2666
2667 out:
2668 mutex_unlock(&card->mutex);
2669 return error;
2670 }
2671
2672 static int
2673 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2674 {
2675 struct idt77252_dev *card = dev->dev_data;
2676 int i, left;
2677
2678 left = (int) *pos;
2679 if (!left--)
2680 return sprintf(page, "IDT77252 Interrupts:\n");
2681 if (!left--)
2682 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
2683 if (!left--)
2684 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2685 if (!left--)
2686 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
2687 if (!left--)
2688 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2689 if (!left--)
2690 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
2691 if (!left--)
2692 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2693 if (!left--)
2694 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2695 if (!left--)
2696 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
2697 if (!left--)
2698 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
2699 if (!left--)
2700 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2701 if (!left--)
2702 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2703 if (!left--)
2704 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2705 if (!left--)
2706 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2707 if (!left--)
2708 return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2709
2710 for (i = 0; i < card->tct_size; i++) {
2711 unsigned long tct;
2712 struct atm_vcc *vcc;
2713 struct vc_map *vc;
2714 char *p;
2715
2716 vc = card->vcs[i];
2717 if (!vc)
2718 continue;
2719
2720 vcc = NULL;
2721 if (vc->tx_vcc)
2722 vcc = vc->tx_vcc;
2723 if (!vcc)
2724 continue;
2725 if (left--)
2726 continue;
2727
2728 p = page;
2729 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2730 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2731
2732 for (i = 0; i < 8; i++)
2733 p += sprintf(p, " %08x", read_sram(card, tct + i));
2734 p += sprintf(p, "\n");
2735 return p - page;
2736 }
2737 return 0;
2738 }
2739
2740 /*****************************************************************************/
2741 /* */
2742 /* Interrupt handler */
2743 /* */
2744 /*****************************************************************************/
2745
2746 static void
2747 idt77252_collect_stat(struct idt77252_dev *card)
2748 {
2749 u32 cdc, vpec, icc;
2750
2751 cdc = readl(SAR_REG_CDC);
2752 vpec = readl(SAR_REG_VPEC);
2753 icc = readl(SAR_REG_ICC);
2754
2755 #ifdef NOTDEF
2756 printk("%s:", card->name);
2757
2758 if (cdc & 0x7f0000) {
2759 char *s = "";
2760
2761 printk(" [");
2762 if (cdc & (1 << 22)) {
2763 printk("%sRM ID", s);
2764 s = " | ";
2765 }
2766 if (cdc & (1 << 21)) {
2767 printk("%sCON TAB", s);
2768 s = " | ";
2769 }
2770 if (cdc & (1 << 20)) {
2771 printk("%sNO FB", s);
2772 s = " | ";
2773 }
2774 if (cdc & (1 << 19)) {
2775 printk("%sOAM CRC", s);
2776 s = " | ";
2777 }
2778 if (cdc & (1 << 18)) {
2779 printk("%sRM CRC", s);
2780 s = " | ";
2781 }
2782 if (cdc & (1 << 17)) {
2783 printk("%sRM FIFO", s);
2784 s = " | ";
2785 }
2786 if (cdc & (1 << 16)) {
2787 printk("%sRX FIFO", s);
2788 s = " | ";
2789 }
2790 printk("]");
2791 }
2792
2793 printk(" CDC %04x, VPEC %04x, ICC: %04x\n",
2794 cdc & 0xffff, vpec & 0xffff, icc & 0xffff);
2795 #endif
2796 }
2797
2798 static irqreturn_t
2799 idt77252_interrupt(int irq, void *dev_id)
2800 {
2801 struct idt77252_dev *card = dev_id;
2802 u32 stat;
2803
2804 stat = readl(SAR_REG_STAT) & 0xffff;
2805 if (!stat) /* no interrupt for us */
2806 return IRQ_NONE;
2807
2808 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2809 printk("%s: Re-entering irq_handler()\n", card->name);
2810 goto out;
2811 }
2812
2813 writel(stat, SAR_REG_STAT); /* reset interrupt */
2814
2815 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */
2816 INTPRINTK("%s: TSIF\n", card->name);
2817 card->irqstat[15]++;
2818 idt77252_tx(card);
2819 }
2820 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */
2821 INTPRINTK("%s: TXICP\n", card->name);
2822 card->irqstat[14]++;
2823 #ifdef CONFIG_ATM_IDT77252_DEBUG
2824 idt77252_tx_dump(card);
2825 #endif
2826 }
2827 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */
2828 INTPRINTK("%s: TSQF\n", card->name);
2829 card->irqstat[12]++;
2830 idt77252_tx(card);
2831 }
2832 if (stat & SAR_STAT_TMROF) { /* Timer overflow */
2833 INTPRINTK("%s: TMROF\n", card->name);
2834 card->irqstat[11]++;
2835 idt77252_collect_stat(card);
2836 }
2837
2838 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */
2839 INTPRINTK("%s: EPDU\n", card->name);
2840 card->irqstat[5]++;
2841 idt77252_rx(card);
2842 }
2843 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */
2844 INTPRINTK("%s: RSQAF\n", card->name);
2845 card->irqstat[1]++;
2846 idt77252_rx(card);
2847 }
2848 if (stat & SAR_STAT_RSQF) { /* RSQ is full */
2849 INTPRINTK("%s: RSQF\n", card->name);
2850 card->irqstat[6]++;
2851 idt77252_rx(card);
2852 }
2853 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */
2854 INTPRINTK("%s: RAWCF\n", card->name);
2855 card->irqstat[4]++;
2856 idt77252_rx_raw(card);
2857 }
2858
2859 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */
2860 INTPRINTK("%s: PHYI", card->name);
2861 card->irqstat[10]++;
2862 if (card->atmdev->phy && card->atmdev->phy->interrupt)
2863 card->atmdev->phy->interrupt(card->atmdev);
2864 }
2865
2866 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2867 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2868
2869 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2870
2871 INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2872
2873 if (stat & SAR_STAT_FBQ0A)
2874 card->irqstat[2]++;
2875 if (stat & SAR_STAT_FBQ1A)
2876 card->irqstat[3]++;
2877 if (stat & SAR_STAT_FBQ2A)
2878 card->irqstat[7]++;
2879 if (stat & SAR_STAT_FBQ3A)
2880 card->irqstat[8]++;
2881
2882 schedule_work(&card->tqueue);
2883 }
2884
2885 out:
2886 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2887 return IRQ_HANDLED;
2888 }
2889
2890 static void
2891 idt77252_softint(struct work_struct *work)
2892 {
2893 struct idt77252_dev *card =
2894 container_of(work, struct idt77252_dev, tqueue);
2895 u32 stat;
2896 int done;
2897
2898 for (done = 1; ; done = 1) {
2899 stat = readl(SAR_REG_STAT) >> 16;
2900
2901 if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2902 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2903 done = 0;
2904 }
2905
2906 stat >>= 4;
2907 if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2908 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2909 done = 0;
2910 }
2911
2912 stat >>= 4;
2913 if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2914 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2915 done = 0;
2916 }
2917
2918 stat >>= 4;
2919 if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2920 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2921 done = 0;
2922 }
2923
2924 if (done)
2925 break;
2926 }
2927
2928 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2929 }
2930
2931
2932 static int
2933 open_card_oam(struct idt77252_dev *card)
2934 {
2935 unsigned long flags;
2936 unsigned long addr;
2937 struct vc_map *vc;
2938 int vpi, vci;
2939 int index;
2940 u32 rcte;
2941
2942 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2943 for (vci = 3; vci < 5; vci++) {
2944 index = VPCI2VC(card, vpi, vci);
2945
2946 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2947 if (!vc) {
2948 printk("%s: can't alloc vc\n", card->name);
2949 return -ENOMEM;
2950 }
2951 vc->index = index;
2952 card->vcs[index] = vc;
2953
2954 flush_rx_pool(card, &vc->rcv.rx_pool);
2955
2956 rcte = SAR_RCTE_CONNECTOPEN |
2957 SAR_RCTE_RAWCELLINTEN |
2958 SAR_RCTE_RCQ |
2959 SAR_RCTE_FBP_1;
2960
2961 addr = card->rct_base + (vc->index << 2);
2962 write_sram(card, addr, rcte);
2963
2964 spin_lock_irqsave(&card->cmd_lock, flags);
2965 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2966 SAR_REG_CMD);
2967 waitfor_idle(card);
2968 spin_unlock_irqrestore(&card->cmd_lock, flags);
2969 }
2970 }
2971
2972 return 0;
2973 }
2974
2975 static void
2976 close_card_oam(struct idt77252_dev *card)
2977 {
2978 unsigned long flags;
2979 unsigned long addr;
2980 struct vc_map *vc;
2981 int vpi, vci;
2982 int index;
2983
2984 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2985 for (vci = 3; vci < 5; vci++) {
2986 index = VPCI2VC(card, vpi, vci);
2987 vc = card->vcs[index];
2988
2989 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2990
2991 spin_lock_irqsave(&card->cmd_lock, flags);
2992 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
2993 SAR_REG_CMD);
2994 waitfor_idle(card);
2995 spin_unlock_irqrestore(&card->cmd_lock, flags);
2996
2997 if (vc->rcv.rx_pool.count) {
2998 DPRINTK("%s: closing a VC "
2999 "with pending rx buffers.\n",
3000 card->name);
3001
3002 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
3003 }
3004 }
3005 }
3006 }
3007
3008 static int
3009 open_card_ubr0(struct idt77252_dev *card)
3010 {
3011 struct vc_map *vc;
3012
3013 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
3014 if (!vc) {
3015 printk("%s: can't alloc vc\n", card->name);
3016 return -ENOMEM;
3017 }
3018 card->vcs[0] = vc;
3019 vc->class = SCHED_UBR0;
3020
3021 vc->scq = alloc_scq(card, vc->class);
3022 if (!vc->scq) {
3023 printk("%s: can't get SCQ.\n", card->name);
3024 return -ENOMEM;
3025 }
3026
3027 card->scd2vc[0] = vc;
3028 vc->scd_index = 0;
3029 vc->scq->scd = card->scd_base;
3030
3031 fill_scd(card, vc->scq, vc->class);
3032
3033 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
3034 write_sram(card, card->tct_base + 1, 0);
3035 write_sram(card, card->tct_base + 2, 0);
3036 write_sram(card, card->tct_base + 3, 0);
3037 write_sram(card, card->tct_base + 4, 0);
3038 write_sram(card, card->tct_base + 5, 0);
3039 write_sram(card, card->tct_base + 6, 0);
3040 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
3041
3042 clear_bit(VCF_IDLE, &vc->flags);
3043 writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
3044 return 0;
3045 }
3046
3047 static int
3048 idt77252_dev_open(struct idt77252_dev *card)
3049 {
3050 u32 conf;
3051
3052 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3053 printk("%s: SAR not yet initialized.\n", card->name);
3054 return -1;
3055 }
3056
3057 conf = SAR_CFG_RXPTH| /* enable receive path */
3058 SAR_RX_DELAY | /* interrupt on complete PDU */
3059 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3060 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3061 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3062 SAR_CFG_FBIE | /* interrupt on low free buffers */
3063 SAR_CFG_TXEN | /* transmit operation enable */
3064 SAR_CFG_TXINT | /* interrupt on transmit status */
3065 SAR_CFG_TXUIE | /* interrupt on transmit underrun */
3066 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */
3067 SAR_CFG_PHYIE /* enable PHY interrupts */
3068 ;
3069
3070 #ifdef CONFIG_ATM_IDT77252_RCV_ALL
3071 /* Test RAW cell receive. */
3072 conf |= SAR_CFG_VPECA;
3073 #endif
3074
3075 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3076
3077 if (open_card_oam(card)) {
3078 printk("%s: Error initializing OAM.\n", card->name);
3079 return -1;
3080 }
3081
3082 if (open_card_ubr0(card)) {
3083 printk("%s: Error initializing UBR0.\n", card->name);
3084 return -1;
3085 }
3086
3087 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3088 return 0;
3089 }
3090
3091 void
3092 idt77252_dev_close(struct atm_dev *dev)
3093 {
3094 struct idt77252_dev *card = dev->dev_data;
3095 u32 conf;
3096
3097 close_card_oam(card);
3098
3099 conf = SAR_CFG_RXPTH | /* enable receive path */
3100 SAR_RX_DELAY | /* interrupt on complete PDU */
3101 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3102 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3103 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3104 SAR_CFG_FBIE | /* interrupt on low free buffers */
3105 SAR_CFG_TXEN | /* transmit operation enable */
3106 SAR_CFG_TXINT | /* interrupt on transmit status */
3107 SAR_CFG_TXUIE | /* interrupt on xmit underrun */
3108 SAR_CFG_TXSFI /* interrupt on TSQ almost full */
3109 ;
3110
3111 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3112
3113 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3114 }
3115
3116
3117 /*****************************************************************************/
3118 /* */
3119 /* Initialisation and Deinitialization of IDT77252 */
3120 /* */
3121 /*****************************************************************************/
3122
3123
3124 static void
3125 deinit_card(struct idt77252_dev *card)
3126 {
3127 struct sk_buff *skb;
3128 int i, j;
3129
3130 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3131 printk("%s: SAR not yet initialized.\n", card->name);
3132 return;
3133 }
3134 DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3135
3136 writel(0, SAR_REG_CFG);
3137
3138 if (card->atmdev)
3139 atm_dev_deregister(card->atmdev);
3140
3141 for (i = 0; i < 4; i++) {
3142 for (j = 0; j < FBQ_SIZE; j++) {
3143 skb = card->sbpool[i].skb[j];
3144 if (skb) {
3145 pci_unmap_single(card->pcidev,
3146 IDT77252_PRV_PADDR(skb),
3147 (skb_end_pointer(skb) -
3148 skb->data),
3149 PCI_DMA_FROMDEVICE);
3150 card->sbpool[i].skb[j] = NULL;
3151 dev_kfree_skb(skb);
3152 }
3153 }
3154 }
3155
3156 vfree(card->soft_tst);
3157
3158 vfree(card->scd2vc);
3159
3160 vfree(card->vcs);
3161
3162 if (card->raw_cell_hnd) {
3163 pci_free_consistent(card->pcidev, 2 * sizeof(u32),
3164 card->raw_cell_hnd, card->raw_cell_paddr);
3165 }
3166
3167 if (card->rsq.base) {
3168 DIPRINTK("%s: Release RSQ ...\n", card->name);
3169 deinit_rsq(card);
3170 }
3171
3172 if (card->tsq.base) {
3173 DIPRINTK("%s: Release TSQ ...\n", card->name);
3174 deinit_tsq(card);
3175 }
3176
3177 DIPRINTK("idt77252: Release IRQ.\n");
3178 free_irq(card->pcidev->irq, card);
3179
3180 for (i = 0; i < 4; i++) {
3181 if (card->fbq[i])
3182 iounmap(card->fbq[i]);
3183 }
3184
3185 if (card->membase)
3186 iounmap(card->membase);
3187
3188 clear_bit(IDT77252_BIT_INIT, &card->flags);
3189 DIPRINTK("%s: Card deinitialized.\n", card->name);
3190 }
3191
3192
3193 static int __devinit
3194 init_sram(struct idt77252_dev *card)
3195 {
3196 int i;
3197
3198 for (i = 0; i < card->sramsize; i += 4)
3199 write_sram(card, (i >> 2), 0);
3200
3201 /* set SRAM layout for THIS card */
3202 if (card->sramsize == (512 * 1024)) {
3203 card->tct_base = SAR_SRAM_TCT_128_BASE;
3204 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3205 / SAR_SRAM_TCT_SIZE;
3206 card->rct_base = SAR_SRAM_RCT_128_BASE;
3207 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3208 / SAR_SRAM_RCT_SIZE;
3209 card->rt_base = SAR_SRAM_RT_128_BASE;
3210 card->scd_base = SAR_SRAM_SCD_128_BASE;
3211 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3212 / SAR_SRAM_SCD_SIZE;
3213 card->tst[0] = SAR_SRAM_TST1_128_BASE;
3214 card->tst[1] = SAR_SRAM_TST2_128_BASE;
3215 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3216 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3217 card->abrst_size = SAR_ABRSTD_SIZE_8K;
3218 card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3219 card->fifo_size = SAR_RXFD_SIZE_32K;
3220 } else {
3221 card->tct_base = SAR_SRAM_TCT_32_BASE;
3222 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3223 / SAR_SRAM_TCT_SIZE;
3224 card->rct_base = SAR_SRAM_RCT_32_BASE;
3225 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3226 / SAR_SRAM_RCT_SIZE;
3227 card->rt_base = SAR_SRAM_RT_32_BASE;
3228 card->scd_base = SAR_SRAM_SCD_32_BASE;
3229 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3230 / SAR_SRAM_SCD_SIZE;
3231 card->tst[0] = SAR_SRAM_TST1_32_BASE;
3232 card->tst[1] = SAR_SRAM_TST2_32_BASE;
3233 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3234 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3235 card->abrst_size = SAR_ABRSTD_SIZE_1K;
3236 card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3237 card->fifo_size = SAR_RXFD_SIZE_4K;
3238 }
3239
3240 /* Initialize TCT */
3241 for (i = 0; i < card->tct_size; i++) {
3242 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3243 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3244 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3245 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3246 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3247 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3248 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3249 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3250 }
3251
3252 /* Initialize RCT */
3253 for (i = 0; i < card->rct_size; i++) {
3254 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3255 (u32) SAR_RCTE_RAWCELLINTEN);
3256 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3257 (u32) 0);
3258 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3259 (u32) 0);
3260 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3261 (u32) 0xffffffff);
3262 }
3263
3264 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 |
3265 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3266 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 |
3267 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3268 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 |
3269 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3270 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 |
3271 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3272
3273 /* Initialize rate table */
3274 for (i = 0; i < 256; i++) {
3275 write_sram(card, card->rt_base + i, log_to_rate[i]);
3276 }
3277
3278 for (i = 0; i < 128; i++) {
3279 unsigned int tmp;
3280
3281 tmp = rate_to_log[(i << 2) + 0] << 0;
3282 tmp |= rate_to_log[(i << 2) + 1] << 8;
3283 tmp |= rate_to_log[(i << 2) + 2] << 16;
3284 tmp |= rate_to_log[(i << 2) + 3] << 24;
3285 write_sram(card, card->rt_base + 256 + i, tmp);
3286 }
3287
3288 #if 0 /* Fill RDF and AIR tables. */
3289 for (i = 0; i < 128; i++) {
3290 unsigned int tmp;
3291
3292 tmp = RDF[0][(i << 1) + 0] << 16;
3293 tmp |= RDF[0][(i << 1) + 1] << 0;
3294 write_sram(card, card->rt_base + 512 + i, tmp);
3295 }
3296
3297 for (i = 0; i < 128; i++) {
3298 unsigned int tmp;
3299
3300 tmp = AIR[0][(i << 1) + 0] << 16;
3301 tmp |= AIR[0][(i << 1) + 1] << 0;
3302 write_sram(card, card->rt_base + 640 + i, tmp);
3303 }
3304 #endif
3305
3306 IPRINTK("%s: initialize rate table ...\n", card->name);
3307 writel(card->rt_base << 2, SAR_REG_RTBL);
3308
3309 /* Initialize TSTs */
3310 IPRINTK("%s: initialize TST ...\n", card->name);
3311 card->tst_free = card->tst_size - 2; /* last two are jumps */
3312
3313 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3314 write_sram(card, i, TSTE_OPC_VAR);
3315 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3316 idt77252_sram_write_errors = 1;
3317 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3318 idt77252_sram_write_errors = 0;
3319 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3320 write_sram(card, i, TSTE_OPC_VAR);
3321 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3322 idt77252_sram_write_errors = 1;
3323 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3324 idt77252_sram_write_errors = 0;
3325
3326 card->tst_index = 0;
3327 writel(card->tst[0] << 2, SAR_REG_TSTB);
3328
3329 /* Initialize ABRSTD and Receive FIFO */
3330 IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3331 writel(card->abrst_size | (card->abrst_base << 2),
3332 SAR_REG_ABRSTD);
3333
3334 IPRINTK("%s: initialize receive fifo ...\n", card->name);
3335 writel(card->fifo_size | (card->fifo_base << 2),
3336 SAR_REG_RXFD);
3337
3338 IPRINTK("%s: SRAM initialization complete.\n", card->name);
3339 return 0;
3340 }
3341
3342 static int __devinit
3343 init_card(struct atm_dev *dev)
3344 {
3345 struct idt77252_dev *card = dev->dev_data;
3346 struct pci_dev *pcidev = card->pcidev;
3347 unsigned long tmpl, modl;
3348 unsigned int linkrate, rsvdcr;
3349 unsigned int tst_entries;
3350 struct net_device *tmp;
3351 char tname[10];
3352
3353 u32 size;
3354 u_char pci_byte;
3355 u32 conf;
3356 int i, k;
3357
3358 if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3359 printk("Error: SAR already initialized.\n");
3360 return -1;
3361 }
3362
3363 /*****************************************************************/
3364 /* P C I C O N F I G U R A T I O N */
3365 /*****************************************************************/
3366
3367 /* Set PCI Retry-Timeout and TRDY timeout */
3368 IPRINTK("%s: Checking PCI retries.\n", card->name);
3369 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3370 printk("%s: can't read PCI retry timeout.\n", card->name);
3371 deinit_card(card);
3372 return -1;
3373 }
3374 if (pci_byte != 0) {
3375 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3376 card->name, pci_byte);
3377 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3378 printk("%s: can't set PCI retry timeout.\n",
3379 card->name);
3380 deinit_card(card);
3381 return -1;
3382 }
3383 }
3384 IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3385 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3386 printk("%s: can't read PCI TRDY timeout.\n", card->name);
3387 deinit_card(card);
3388 return -1;
3389 }
3390 if (pci_byte != 0) {
3391 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3392 card->name, pci_byte);
3393 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3394 printk("%s: can't set PCI TRDY timeout.\n", card->name);
3395 deinit_card(card);
3396 return -1;
3397 }
3398 }
3399 /* Reset Timer register */
3400 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3401 printk("%s: resetting timer overflow.\n", card->name);
3402 writel(SAR_STAT_TMROF, SAR_REG_STAT);
3403 }
3404 IPRINTK("%s: Request IRQ ... ", card->name);
3405 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_DISABLED|IRQF_SHARED,
3406 card->name, card) != 0) {
3407 printk("%s: can't allocate IRQ.\n", card->name);
3408 deinit_card(card);
3409 return -1;
3410 }
3411 IPRINTK("got %d.\n", pcidev->irq);
3412
3413 /*****************************************************************/
3414 /* C H E C K A N D I N I T S R A M */
3415 /*****************************************************************/
3416
3417 IPRINTK("%s: Initializing SRAM\n", card->name);
3418
3419 /* preset size of connecton table, so that init_sram() knows about it */
3420 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */
3421 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */
3422 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */
3423 #ifndef ATM_IDT77252_SEND_IDLE
3424 SAR_CFG_NO_IDLE | /* Do not send idle cells */
3425 #endif
3426 0;
3427
3428 if (card->sramsize == (512 * 1024))
3429 conf |= SAR_CFG_CNTBL_1k;
3430 else
3431 conf |= SAR_CFG_CNTBL_512;
3432
3433 switch (vpibits) {
3434 case 0:
3435 conf |= SAR_CFG_VPVCS_0;
3436 break;
3437 default:
3438 case 1:
3439 conf |= SAR_CFG_VPVCS_1;
3440 break;
3441 case 2:
3442 conf |= SAR_CFG_VPVCS_2;
3443 break;
3444 case 8:
3445 conf |= SAR_CFG_VPVCS_8;
3446 break;
3447 }
3448
3449 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3450
3451 if (init_sram(card) < 0)
3452 return -1;
3453
3454 /********************************************************************/
3455 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
3456 /********************************************************************/
3457 /* Initialize TSQ */
3458 if (0 != init_tsq(card)) {
3459 deinit_card(card);
3460 return -1;
3461 }
3462 /* Initialize RSQ */
3463 if (0 != init_rsq(card)) {
3464 deinit_card(card);
3465 return -1;
3466 }
3467
3468 card->vpibits = vpibits;
3469 if (card->sramsize == (512 * 1024)) {
3470 card->vcibits = 10 - card->vpibits;
3471 } else {
3472 card->vcibits = 9 - card->vpibits;
3473 }
3474
3475 card->vcimask = 0;
3476 for (k = 0, i = 1; k < card->vcibits; k++) {
3477 card->vcimask |= i;
3478 i <<= 1;
3479 }
3480
3481 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3482 writel(0, SAR_REG_VPM);
3483
3484 /* Little Endian Order */
3485 writel(0, SAR_REG_GP);
3486
3487 /* Initialize RAW Cell Handle Register */
3488 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32),
3489 &card->raw_cell_paddr);
3490 if (!card->raw_cell_hnd) {
3491 printk("%s: memory allocation failure.\n", card->name);
3492 deinit_card(card);
3493 return -1;
3494 }
3495 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32));
3496 writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3497 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3498 card->raw_cell_hnd);
3499
3500 size = sizeof(struct vc_map *) * card->tct_size;
3501 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3502 if (NULL == (card->vcs = vmalloc(size))) {
3503 printk("%s: memory allocation failure.\n", card->name);
3504 deinit_card(card);
3505 return -1;
3506 }
3507 memset(card->vcs, 0, size);
3508
3509 size = sizeof(struct vc_map *) * card->scd_size;
3510 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3511 card->name, size);
3512 if (NULL == (card->scd2vc = vmalloc(size))) {
3513 printk("%s: memory allocation failure.\n", card->name);
3514 deinit_card(card);
3515 return -1;
3516 }
3517 memset(card->scd2vc, 0, size);
3518
3519 size = sizeof(struct tst_info) * (card->tst_size - 2);
3520 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3521 card->name, size);
3522 if (NULL == (card->soft_tst = vmalloc(size))) {
3523 printk("%s: memory allocation failure.\n", card->name);
3524 deinit_card(card);
3525 return -1;
3526 }
3527 for (i = 0; i < card->tst_size - 2; i++) {
3528 card->soft_tst[i].tste = TSTE_OPC_VAR;
3529 card->soft_tst[i].vc = NULL;
3530 }
3531
3532 if (dev->phy == NULL) {
3533 printk("%s: No LT device defined.\n", card->name);
3534 deinit_card(card);
3535 return -1;
3536 }
3537 if (dev->phy->ioctl == NULL) {
3538 printk("%s: LT had no IOCTL funtion defined.\n", card->name);
3539 deinit_card(card);
3540 return -1;
3541 }
3542
3543 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3544 /*
3545 * this is a jhs hack to get around special functionality in the
3546 * phy driver for the atecom hardware; the functionality doesn't
3547 * exist in the linux atm suni driver
3548 *
3549 * it isn't the right way to do things, but as the guy from NIST
3550 * said, talking about their measurement of the fine structure
3551 * constant, "it's good enough for government work."
3552 */
3553 linkrate = 149760000;
3554 #endif
3555
3556 card->link_pcr = (linkrate / 8 / 53);
3557 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3558 card->name, linkrate, card->link_pcr);
3559
3560 #ifdef ATM_IDT77252_SEND_IDLE
3561 card->utopia_pcr = card->link_pcr;
3562 #else
3563 card->utopia_pcr = (160000000 / 8 / 54);
3564 #endif
3565
3566 rsvdcr = 0;
3567 if (card->utopia_pcr > card->link_pcr)
3568 rsvdcr = card->utopia_pcr - card->link_pcr;
3569
3570 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3571 modl = tmpl % (unsigned long)card->utopia_pcr;
3572 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3573 if (modl)
3574 tst_entries++;
3575 card->tst_free -= tst_entries;
3576 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3577
3578 #ifdef HAVE_EEPROM
3579 idt77252_eeprom_init(card);
3580 printk("%s: EEPROM: %02x:", card->name,
3581 idt77252_eeprom_read_status(card));
3582
3583 for (i = 0; i < 0x80; i++) {
3584 printk(" %02x",
3585 idt77252_eeprom_read_byte(card, i)
3586 );
3587 }
3588 printk("\n");
3589 #endif /* HAVE_EEPROM */
3590
3591 /*
3592 * XXX: <hack>
3593 */
3594 sprintf(tname, "eth%d", card->index);
3595 tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */
3596 if (tmp) {
3597 memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3598
3599 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n",
3600 card->name, card->atmdev->esi[0], card->atmdev->esi[1],
3601 card->atmdev->esi[2], card->atmdev->esi[3],
3602 card->atmdev->esi[4], card->atmdev->esi[5]);
3603 }
3604 /*
3605 * XXX: </hack>
3606 */
3607
3608 /* Set Maximum Deficit Count for now. */
3609 writel(0xffff, SAR_REG_MDFCT);
3610
3611 set_bit(IDT77252_BIT_INIT, &card->flags);
3612
3613 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3614 return 0;
3615 }
3616
3617
3618 /*****************************************************************************/
3619 /* */
3620 /* Probing of IDT77252 ABR SAR */
3621 /* */
3622 /*****************************************************************************/
3623
3624
3625 static int __devinit
3626 idt77252_preset(struct idt77252_dev *card)
3627 {
3628 u16 pci_command;
3629
3630 /*****************************************************************/
3631 /* P C I C O N F I G U R A T I O N */
3632 /*****************************************************************/
3633
3634 XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3635 card->name);
3636 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3637 printk("%s: can't read PCI_COMMAND.\n", card->name);
3638 deinit_card(card);
3639 return -1;
3640 }
3641 if (!(pci_command & PCI_COMMAND_IO)) {
3642 printk("%s: PCI_COMMAND: %04x (???)\n",
3643 card->name, pci_command);
3644 deinit_card(card);
3645 return (-1);
3646 }
3647 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3648 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3649 printk("%s: can't write PCI_COMMAND.\n", card->name);
3650 deinit_card(card);
3651 return -1;
3652 }
3653 /*****************************************************************/
3654 /* G E N E R I C R E S E T */
3655 /*****************************************************************/
3656
3657 /* Software reset */
3658 writel(SAR_CFG_SWRST, SAR_REG_CFG);
3659 mdelay(1);
3660 writel(0, SAR_REG_CFG);
3661
3662 IPRINTK("%s: Software resetted.\n", card->name);
3663 return 0;
3664 }
3665
3666
3667 static unsigned long __devinit
3668 probe_sram(struct idt77252_dev *card)
3669 {
3670 u32 data, addr;
3671
3672 writel(0, SAR_REG_DR0);
3673 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3674
3675 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3676 writel(ATM_POISON, SAR_REG_DR0);
3677 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3678
3679 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3680 data = readl(SAR_REG_DR0);
3681
3682 if (data != 0)
3683 break;
3684 }
3685
3686 return addr * sizeof(u32);
3687 }
3688
3689 static int __devinit
3690 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
3691 {
3692 static struct idt77252_dev **last = &idt77252_chain;
3693 static int index = 0;
3694
3695 unsigned long membase, srambase;
3696 struct idt77252_dev *card;
3697 struct atm_dev *dev;
3698 int i, err;
3699
3700
3701 if ((err = pci_enable_device(pcidev))) {
3702 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
3703 return err;
3704 }
3705
3706 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3707 if (!card) {
3708 printk("idt77252-%d: can't allocate private data\n", index);
3709 err = -ENOMEM;
3710 goto err_out_disable_pdev;
3711 }
3712 card->revision = pcidev->revision;
3713 card->index = index;
3714 card->pcidev = pcidev;
3715 sprintf(card->name, "idt77252-%d", card->index);
3716
3717 INIT_WORK(&card->tqueue, idt77252_softint);
3718
3719 membase = pci_resource_start(pcidev, 1);
3720 srambase = pci_resource_start(pcidev, 2);
3721
3722 mutex_init(&card->mutex);
3723 spin_lock_init(&card->cmd_lock);
3724 spin_lock_init(&card->tst_lock);
3725
3726 init_timer(&card->tst_timer);
3727 card->tst_timer.data = (unsigned long)card;
3728 card->tst_timer.function = tst_timer;
3729
3730 /* Do the I/O remapping... */
3731 card->membase = ioremap(membase, 1024);
3732 if (!card->membase) {
3733 printk("%s: can't ioremap() membase\n", card->name);
3734 err = -EIO;
3735 goto err_out_free_card;
3736 }
3737
3738 if (idt77252_preset(card)) {
3739 printk("%s: preset failed\n", card->name);
3740 err = -EIO;
3741 goto err_out_iounmap;
3742 }
3743
3744 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL);
3745 if (!dev) {
3746 printk("%s: can't register atm device\n", card->name);
3747 err = -EIO;
3748 goto err_out_iounmap;
3749 }
3750 dev->dev_data = card;
3751 card->atmdev = dev;
3752
3753 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3754 suni_init(dev);
3755 if (!dev->phy) {
3756 printk("%s: can't init SUNI\n", card->name);
3757 err = -EIO;
3758 goto err_out_deinit_card;
3759 }
3760 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
3761
3762 card->sramsize = probe_sram(card);
3763
3764 for (i = 0; i < 4; i++) {
3765 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
3766 if (!card->fbq[i]) {
3767 printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3768 err = -EIO;
3769 goto err_out_deinit_card;
3770 }
3771 }
3772
3773 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3774 card->name, ((card->revision > 1) && (card->revision < 25)) ?
3775 'A' + card->revision - 1 : '?', membase, srambase,
3776 card->sramsize / 1024);
3777
3778 if (init_card(dev)) {
3779 printk("%s: init_card failed\n", card->name);
3780 err = -EIO;
3781 goto err_out_deinit_card;
3782 }
3783
3784 dev->ci_range.vpi_bits = card->vpibits;
3785 dev->ci_range.vci_bits = card->vcibits;
3786 dev->link_rate = card->link_pcr;
3787
3788 if (dev->phy->start)
3789 dev->phy->start(dev);
3790
3791 if (idt77252_dev_open(card)) {
3792 printk("%s: dev_open failed\n", card->name);
3793 err = -EIO;
3794 goto err_out_stop;
3795 }
3796
3797 *last = card;
3798 last = &card->next;
3799 index++;
3800
3801 return 0;
3802
3803 err_out_stop:
3804 if (dev->phy->stop)
3805 dev->phy->stop(dev);
3806
3807 err_out_deinit_card:
3808 deinit_card(card);
3809
3810 err_out_iounmap:
3811 iounmap(card->membase);
3812
3813 err_out_free_card:
3814 kfree(card);
3815
3816 err_out_disable_pdev:
3817 pci_disable_device(pcidev);
3818 return err;
3819 }
3820
3821 static struct pci_device_id idt77252_pci_tbl[] =
3822 {
3823 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252,
3824 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
3825 { 0, }
3826 };
3827
3828 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
3829
3830 static struct pci_driver idt77252_driver = {
3831 .name = "idt77252",
3832 .id_table = idt77252_pci_tbl,
3833 .probe = idt77252_init_one,
3834 };
3835
3836 static int __init idt77252_init(void)
3837 {
3838 struct sk_buff *skb;
3839
3840 <<<<<<< HEAD:drivers/atm/idt77252.c
3841 printk("%s: at %p\n", __FUNCTION__, idt77252_init);
3842 =======
3843 printk("%s: at %p\n", __func__, idt77252_init);
3844 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/atm/idt77252.c
3845
3846 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
3847 sizeof(struct idt77252_skb_prv)) {
3848 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
3849 <<<<<<< HEAD:drivers/atm/idt77252.c
3850 __FUNCTION__, (unsigned long) sizeof(skb->cb),
3851 =======
3852 __func__, (unsigned long) sizeof(skb->cb),
3853 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/atm/idt77252.c
3854 (unsigned long) sizeof(struct atm_skb_data) +
3855 sizeof(struct idt77252_skb_prv));
3856 return -EIO;
3857 }
3858
3859 return pci_register_driver(&idt77252_driver);
3860 }
3861
3862 static void __exit idt77252_exit(void)
3863 {
3864 struct idt77252_dev *card;
3865 struct atm_dev *dev;
3866
3867 pci_unregister_driver(&idt77252_driver);
3868
3869 while (idt77252_chain) {
3870 card = idt77252_chain;
3871 dev = card->atmdev;
3872 idt77252_chain = card->next;
3873
3874 if (dev->phy->stop)
3875 dev->phy->stop(dev);
3876 deinit_card(card);
3877 pci_disable_device(card->pcidev);
3878 kfree(card);
3879 }
3880
3881 DIPRINTK("idt77252: finished cleanup-module().\n");
3882 }
3883
3884 module_init(idt77252_init);
3885 module_exit(idt77252_exit);
3886
3887 MODULE_LICENSE("GPL");
3888
3889 module_param(vpibits, uint, 0);
3890 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3891 #ifdef CONFIG_ATM_IDT77252_DEBUG
3892 module_param(debug, ulong, 0644);
3893 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
3894 #endif
3895
3896 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3897 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");
WRT350N Kernel Patches