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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / atm / firestream.c
blobef40d66fe5908241f5a6f3b59f8c704478eb0baa
1
2 /* drivers/atm/firestream.c - FireStream 155 (MB86697) and
3 * FireStream 50 (MB86695) device driver
4 */
5
6 /* Written & (C) 2000 by R.E.Wolff@BitWizard.nl
7 * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA
8 * and ambassador.c Copyright (C) 1995-1999 Madge Networks Ltd
9 */
10
11 /*
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
16
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the Free Software
24 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25
26 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
27 system and in the file COPYING in the Linux kernel source.
28 */
29
30
31 #include <linux/module.h>
32 #include <linux/sched.h>
33 #include <linux/kernel.h>
34 #include <linux/mm.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/errno.h>
38 #include <linux/atm.h>
39 #include <linux/atmdev.h>
40 #include <linux/sonet.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/delay.h>
44 #include <linux/ioport.h> /* for request_region */
45 #include <linux/uio.h>
46 #include <linux/init.h>
47 #include <linux/capability.h>
48 #include <linux/bitops.h>
49 #include <asm/byteorder.h>
50 #include <asm/system.h>
51 #include <asm/string.h>
52 #include <asm/io.h>
53 #include <asm/atomic.h>
54 #include <asm/uaccess.h>
55 #include <linux/wait.h>
56
57 #include "firestream.h"
58
59 static int loopback = 0;
60 static int num=0x5a;
61
62 /* According to measurements (but they look suspicious to me!) done in
63 * '97, 37% of the packets are one cell in size. So it pays to have
64 * buffers allocated at that size. A large jump in percentage of
65 * packets occurs at packets around 536 bytes in length. So it also
66 * pays to have those pre-allocated. Unfortunately, we can't fully
67 * take advantage of this as the majority of the packets is likely to
68 * be TCP/IP (As where obviously the measurement comes from) There the
69 * link would be opened with say a 1500 byte MTU, and we can't handle
70 * smaller buffers more efficiently than the larger ones. -- REW
71 */
72
73 /* Due to the way Linux memory management works, specifying "576" as
74 * an allocation size here isn't going to help. They are allocated
75 * from 1024-byte regions anyway. With the size of the sk_buffs (quite
76 * large), it doesn't pay to allocate the smallest size (64) -- REW */
77
78 /* This is all guesswork. Hard numbers to back this up or disprove this,
79 * are appreciated. -- REW */
80
81 /* The last entry should be about 64k. However, the "buffer size" is
82 * passed to the chip in a 16 bit field. I don't know how "65536"
83 * would be interpreted. -- REW */
84
85 #define NP FS_NR_FREE_POOLS
86 static int rx_buf_sizes[NP] = {128, 256, 512, 1024, 2048, 4096, 16384, 65520};
87 /* log2: 7 8 9 10 11 12 14 16 */
88
89 #if 0
90 static int rx_pool_sizes[NP] = {1024, 1024, 512, 256, 128, 64, 32, 32};
91 #else
92 /* debug */
93 static int rx_pool_sizes[NP] = {128, 128, 128, 64, 64, 64, 32, 32};
94 #endif
95 /* log2: 10 10 9 8 7 6 5 5 */
96 /* sumlog2: 17 18 18 18 18 18 19 21 */
97 /* mem allocated: 128k 256k 256k 256k 256k 256k 512k 2M */
98 /* tot mem: almost 4M */
99
100 /* NP is shorter, so that it fits on a single line. */
101 #undef NP
102
103
104 /* Small hardware gotcha:
105
106 The FS50 CAM (VP/VC match registers) always take the lowest channel
107 number that matches. This is not a problem.
108
109 However, they also ignore whether the channel is enabled or
110 not. This means that if you allocate channel 0 to 1.2 and then
111 channel 1 to 0.0, then disabeling channel 0 and writing 0 to the
112 match channel for channel 0 will "steal" the traffic from channel
113 1, even if you correctly disable channel 0.
114
115 Workaround:
116
117 - When disabling channels, write an invalid VP/VC value to the
118 match register. (We use 0xffffffff, which in the worst case
119 matches VP/VC = <maxVP>/<maxVC>, but I expect it not to match
120 anything as some "when not in use, program to 0" bits are now
121 programmed to 1...)
122
123 - Don't initialize the match registers to 0, as 0.0 is a valid
124 channel.
125 */
126
127
128 /* Optimization hints and tips.
129
130 The FireStream chips are very capable of reducing the amount of
131 "interrupt-traffic" for the CPU. This driver requests an interrupt on EVERY
132 action. You could try to minimize this a bit.
133
134 Besides that, the userspace->kernel copy and the PCI bus are the
135 performance limiting issues for this driver.
136
137 You could queue up a bunch of outgoing packets without telling the
138 FireStream. I'm not sure that's going to win you much though. The
139 Linux layer won't tell us in advance when it's not going to give us
140 any more packets in a while. So this is tricky to implement right without
141 introducing extra delays.
142
143 -- REW
144 */
145
146
147
148
149 /* The strings that define what the RX queue entry is all about. */
150 /* Fujitsu: Please tell me which ones can have a pointer to a
151 freepool descriptor! */
152 static char *res_strings[] = {
153 "RX OK: streaming not EOP",
154 "RX OK: streaming EOP",
155 "RX OK: Single buffer packet",
156 "RX OK: packet mode",
157 "RX OK: F4 OAM (end to end)",
158 "RX OK: F4 OAM (Segment)",
159 "RX OK: F5 OAM (end to end)",
160 "RX OK: F5 OAM (Segment)",
161 "RX OK: RM cell",
162 "RX OK: TRANSP cell",
163 "RX OK: TRANSPC cell",
164 "Unmatched cell",
165 "reserved 12",
166 "reserved 13",
167 "reserved 14",
168 "Unrecognized cell",
169 "reserved 16",
170 "reassemby abort: AAL5 abort",
171 "packet purged",
172 "packet ageing timeout",
173 "channel ageing timeout",
174 "calculated length error",
175 "programmed length limit error",
176 "aal5 crc32 error",
177 "oam transp or transpc crc10 error",
178 "reserved 25",
179 "reserved 26",
180 "reserved 27",
181 "reserved 28",
182 "reserved 29",
183 "reserved 30",
184 "reassembly abort: no buffers",
185 "receive buffer overflow",
186 "change in GFC",
187 "receive buffer full",
188 "low priority discard - no receive descriptor",
189 "low priority discard - missing end of packet",
190 "reserved 41",
191 "reserved 42",
192 "reserved 43",
193 "reserved 44",
194 "reserved 45",
195 "reserved 46",
196 "reserved 47",
197 "reserved 48",
198 "reserved 49",
199 "reserved 50",
200 "reserved 51",
201 "reserved 52",
202 "reserved 53",
203 "reserved 54",
204 "reserved 55",
205 "reserved 56",
206 "reserved 57",
207 "reserved 58",
208 "reserved 59",
209 "reserved 60",
210 "reserved 61",
211 "reserved 62",
212 "reserved 63",
213 };
214
215 static char *irq_bitname[] = {
216 "LPCO",
217 "DPCO",
218 "RBRQ0_W",
219 "RBRQ1_W",
220 "RBRQ2_W",
221 "RBRQ3_W",
222 "RBRQ0_NF",
223 "RBRQ1_NF",
224 "RBRQ2_NF",
225 "RBRQ3_NF",
226 "BFP_SC",
227 "INIT",
228 "INIT_ERR",
229 "USCEO",
230 "UPEC0",
231 "VPFCO",
232 "CRCCO",
233 "HECO",
234 "TBRQ_W",
235 "TBRQ_NF",
236 "CTPQ_E",
237 "GFC_C0",
238 "PCI_FTL",
239 "CSQ_W",
240 "CSQ_NF",
241 "EXT_INT",
242 "RXDMA_S"
243 };
244
245
246 #define PHY_EOF -1
247 #define PHY_CLEARALL -2
248
249 struct reginit_item {
250 int reg, val;
251 };
252
253
254 static struct reginit_item PHY_NTC_INIT[] __devinitdata = {
255 { PHY_CLEARALL, 0x40 },
256 { 0x12, 0x0001 },
257 { 0x13, 0x7605 },
258 { 0x1A, 0x0001 },
259 { 0x1B, 0x0005 },
260 { 0x38, 0x0003 },
261 { 0x39, 0x0006 }, /* changed here to make loopback */
262 { 0x01, 0x5262 },
263 { 0x15, 0x0213 },
264 { 0x00, 0x0003 },
265 { PHY_EOF, 0}, /* -1 signals end of list */
266 };
267
268
269 /* Safetyfeature: If the card interrupts more than this number of times
270 in a jiffy (1/100th of a second) then we just disable the interrupt and
271 print a message. This prevents the system from hanging.
272
273 150000 packets per second is close to the limit a PC is going to have
274 anyway. We therefore have to disable this for production. -- REW */
275 #undef IRQ_RATE_LIMIT // 100
276
277 /* Interrupts work now. Unlike serial cards, ATM cards don't work all
278 that great without interrupts. -- REW */
279 #undef FS_POLL_FREQ // 100
280
281 /*
282 This driver can spew a whole lot of debugging output at you. If you
283 need maximum performance, you should disable the DEBUG define. To
284 aid in debugging in the field, I'm leaving the compile-time debug
285 features enabled, and disable them "runtime". That allows me to
286 instruct people with problems to enable debugging without requiring
287 them to recompile... -- REW
288 */
289 #define DEBUG
290
291 #ifdef DEBUG
292 #define fs_dprintk(f, str...) if (fs_debug & f) printk (str)
293 #else
294 #define fs_dprintk(f, str...) /* nothing */
295 #endif
296
297
298 static int fs_keystream = 0;
299
300 #ifdef DEBUG
301 /* I didn't forget to set this to zero before shipping. Hit me with a stick
302 if you get this with the debug default not set to zero again. -- REW */
303 static int fs_debug = 0;
304 #else
305 #define fs_debug 0
306 #endif
307
308 #ifdef MODULE
309 #ifdef DEBUG
310 module_param(fs_debug, int, 0644);
311 #endif
312 module_param(loopback, int, 0);
313 module_param(num, int, 0);
314 module_param(fs_keystream, int, 0);
315 /* XXX Add rx_buf_sizes, and rx_pool_sizes As per request Amar. -- REW */
316 #endif
317
318
319 #define FS_DEBUG_FLOW 0x00000001
320 #define FS_DEBUG_OPEN 0x00000002
321 #define FS_DEBUG_QUEUE 0x00000004
322 #define FS_DEBUG_IRQ 0x00000008
323 #define FS_DEBUG_INIT 0x00000010
324 #define FS_DEBUG_SEND 0x00000020
325 #define FS_DEBUG_PHY 0x00000040
326 #define FS_DEBUG_CLEANUP 0x00000080
327 #define FS_DEBUG_QOS 0x00000100
328 #define FS_DEBUG_TXQ 0x00000200
329 #define FS_DEBUG_ALLOC 0x00000400
330 #define FS_DEBUG_TXMEM 0x00000800
331 #define FS_DEBUG_QSIZE 0x00001000
332
333
334 <<<<<<< HEAD:drivers/atm/firestream.c
335 #define func_enter() fs_dprintk (FS_DEBUG_FLOW, "fs: enter %s\n", __FUNCTION__)
336 #define func_exit() fs_dprintk (FS_DEBUG_FLOW, "fs: exit %s\n", __FUNCTION__)
337 =======
338 #define func_enter() fs_dprintk(FS_DEBUG_FLOW, "fs: enter %s\n", __func__)
339 #define func_exit() fs_dprintk(FS_DEBUG_FLOW, "fs: exit %s\n", __func__)
340 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/atm/firestream.c
341
342
343 static struct fs_dev *fs_boards = NULL;
344
345 #ifdef DEBUG
346
347 static void my_hd (void *addr, int len)
348 {
349 int j, ch;
350 unsigned char *ptr = addr;
351
352 while (len > 0) {
353 printk ("%p ", ptr);
354 for (j=0;j < ((len < 16)?len:16);j++) {
355 printk ("%02x %s", ptr[j], (j==7)?" ":"");
356 }
357 for ( ;j < 16;j++) {
358 printk (" %s", (j==7)?" ":"");
359 }
360 for (j=0;j < ((len < 16)?len:16);j++) {
361 ch = ptr[j];
362 printk ("%c", (ch < 0x20)?'.':((ch > 0x7f)?'.':ch));
363 }
364 printk ("\n");
365 ptr += 16;
366 len -= 16;
367 }
368 }
369 #else /* DEBUG */
370 static void my_hd (void *addr, int len){}
371 #endif /* DEBUG */
372
373 /********** free an skb (as per ATM device driver documentation) **********/
374
375 /* Hmm. If this is ATM specific, why isn't there an ATM routine for this?
376 * I copied it over from the ambassador driver. -- REW */
377
378 static inline void fs_kfree_skb (struct sk_buff * skb)
379 {
380 if (ATM_SKB(skb)->vcc->pop)
381 ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
382 else
383 dev_kfree_skb_any (skb);
384 }
385
386
387
388
389 /* It seems the ATM forum recommends this horribly complicated 16bit
390 * floating point format. Turns out the Ambassador uses the exact same
391 * encoding. I just copied it over. If Mitch agrees, I'll move it over
392 * to the atm_misc file or something like that. (and remove it from
393 * here and the ambassador driver) -- REW
394 */
395
396 /* The good thing about this format is that it is monotonic. So,
397 a conversion routine need not be very complicated. To be able to
398 round "nearest" we need to take along a few extra bits. Lets
399 put these after 16 bits, so that we can just return the top 16
400 bits of the 32bit number as the result:
401
402 int mr (unsigned int rate, int r)
403 {
404 int e = 16+9;
405 static int round[4]={0, 0, 0xffff, 0x8000};
406 if (!rate) return 0;
407 while (rate & 0xfc000000) {
408 rate >>= 1;
409 e++;
410 }
411 while (! (rate & 0xfe000000)) {
412 rate <<= 1;
413 e--;
414 }
415
416 // Now the mantissa is in positions bit 16-25. Excepf for the "hidden 1" that's in bit 26.
417 rate &= ~0x02000000;
418 // Next add in the exponent
419 rate |= e << (16+9);
420 // And perform the rounding:
421 return (rate + round[r]) >> 16;
422 }
423
424 14 lines-of-code. Compare that with the 120 that the Ambassador
425 guys needed. (would be 8 lines shorter if I'd try to really reduce
426 the number of lines:
427
428 int mr (unsigned int rate, int r)
429 {
430 int e = 16+9;
431 static int round[4]={0, 0, 0xffff, 0x8000};
432 if (!rate) return 0;
433 for (; rate & 0xfc000000 ;rate >>= 1, e++);
434 for (;!(rate & 0xfe000000);rate <<= 1, e--);
435 return ((rate & ~0x02000000) | (e << (16+9)) + round[r]) >> 16;
436 }
437
438 Exercise for the reader: Remove one more line-of-code, without
439 cheating. (Just joining two lines is cheating). (I know it's
440 possible, don't think you've beat me if you found it... If you
441 manage to lose two lines or more, keep me updated! ;-)
442
443 -- REW */
444
445
446 #define ROUND_UP 1
447 #define ROUND_DOWN 2
448 #define ROUND_NEAREST 3
449 /********** make rate (not quite as much fun as Horizon) **********/
450
451 static unsigned int make_rate (unsigned int rate, int r,
452 u16 * bits, unsigned int * actual)
453 {
454 unsigned char exp = -1; /* hush gcc */
455 unsigned int man = -1; /* hush gcc */
456
457 fs_dprintk (FS_DEBUG_QOS, "make_rate %u", rate);
458
459 /* rates in cells per second, ITU format (nasty 16-bit floating-point)
460 given 5-bit e and 9-bit m:
461 rate = EITHER (1+m/2^9)*2^e OR 0
462 bits = EITHER 1<<14 | e<<9 | m OR 0
463 (bit 15 is "reserved", bit 14 "non-zero")
464 smallest rate is 0 (special representation)
465 largest rate is (1+511/512)*2^31 = 4290772992 (< 2^32-1)
466 smallest non-zero rate is (1+0/512)*2^0 = 1 (> 0)
467 simple algorithm:
468 find position of top bit, this gives e
469 remove top bit and shift (rounding if feeling clever) by 9-e
470 */
471 /* Ambassador ucode bug: please don't set bit 14! so 0 rate not
472 representable. // This should move into the ambassador driver
473 when properly merged. -- REW */
474
475 if (rate > 0xffc00000U) {
476 /* larger than largest representable rate */
477
478 if (r == ROUND_UP) {
479 return -EINVAL;
480 } else {
481 exp = 31;
482 man = 511;
483 }
484
485 } else if (rate) {
486 /* representable rate */
487
488 exp = 31;
489 man = rate;
490
491 /* invariant: rate = man*2^(exp-31) */
492 while (!(man & (1<<31))) {
493 exp = exp - 1;
494 man = man<<1;
495 }
496
497 /* man has top bit set
498 rate = (2^31+(man-2^31))*2^(exp-31)
499 rate = (1+(man-2^31)/2^31)*2^exp
500 */
501 man = man<<1;
502 man &= 0xffffffffU; /* a nop on 32-bit systems */
503 /* rate = (1+man/2^32)*2^exp
504
505 exp is in the range 0 to 31, man is in the range 0 to 2^32-1
506 time to lose significance... we want m in the range 0 to 2^9-1
507 rounding presents a minor problem... we first decide which way
508 we are rounding (based on given rounding direction and possibly
509 the bits of the mantissa that are to be discarded).
510 */
511
512 switch (r) {
513 case ROUND_DOWN: {
514 /* just truncate */
515 man = man>>(32-9);
516 break;
517 }
518 case ROUND_UP: {
519 /* check all bits that we are discarding */
520 if (man & (~0U>>9)) {
521 man = (man>>(32-9)) + 1;
522 if (man == (1<<9)) {
523 /* no need to check for round up outside of range */
524 man = 0;
525 exp += 1;
526 }
527 } else {
528 man = (man>>(32-9));
529 }
530 break;
531 }
532 case ROUND_NEAREST: {
533 /* check msb that we are discarding */
534 if (man & (1<<(32-9-1))) {
535 man = (man>>(32-9)) + 1;
536 if (man == (1<<9)) {
537 /* no need to check for round up outside of range */
538 man = 0;
539 exp += 1;
540 }
541 } else {
542 man = (man>>(32-9));
543 }
544 break;
545 }
546 }
547
548 } else {
549 /* zero rate - not representable */
550
551 if (r == ROUND_DOWN) {
552 return -EINVAL;
553 } else {
554 exp = 0;
555 man = 0;
556 }
557 }
558
559 fs_dprintk (FS_DEBUG_QOS, "rate: man=%u, exp=%hu", man, exp);
560
561 if (bits)
562 *bits = /* (1<<14) | */ (exp<<9) | man;
563
564 if (actual)
565 *actual = (exp >= 9)
566 ? (1 << exp) + (man << (exp-9))
567 : (1 << exp) + ((man + (1<<(9-exp-1))) >> (9-exp));
568
569 return 0;
570 }
571
572
573
574
575 /* FireStream access routines */
576 /* For DEEP-DOWN debugging these can be rigged to intercept accesses to
577 certain registers or to just log all accesses. */
578
579 static inline void write_fs (struct fs_dev *dev, int offset, u32 val)
580 {
581 writel (val, dev->base + offset);
582 }
583
584
585 static inline u32 read_fs (struct fs_dev *dev, int offset)
586 {
587 return readl (dev->base + offset);
588 }
589
590
591
592 static inline struct FS_QENTRY *get_qentry (struct fs_dev *dev, struct queue *q)
593 {
594 return bus_to_virt (read_fs (dev, Q_WP(q->offset)) & Q_ADDR_MASK);
595 }
596
597
598 static void submit_qentry (struct fs_dev *dev, struct queue *q, struct FS_QENTRY *qe)
599 {
600 u32 wp;
601 struct FS_QENTRY *cqe;
602
603 /* XXX Sanity check: the write pointer can be checked to be
604 still the same as the value passed as qe... -- REW */
605 /* udelay (5); */
606 while ((wp = read_fs (dev, Q_WP (q->offset))) & Q_FULL) {
607 fs_dprintk (FS_DEBUG_TXQ, "Found queue at %x full. Waiting.\n",
608 q->offset);
609 schedule ();
610 }
611
612 wp &= ~0xf;
613 cqe = bus_to_virt (wp);
614 if (qe != cqe) {
615 fs_dprintk (FS_DEBUG_TXQ, "q mismatch! %p %p\n", qe, cqe);
616 }
617
618 write_fs (dev, Q_WP(q->offset), Q_INCWRAP);
619
620 {
621 static int c;
622 if (!(c++ % 100))
623 {
624 int rp, wp;
625 rp = read_fs (dev, Q_RP(q->offset));
626 wp = read_fs (dev, Q_WP(q->offset));
627 fs_dprintk (FS_DEBUG_TXQ, "q at %d: %x-%x: %x entries.\n",
628 q->offset, rp, wp, wp-rp);
629 }
630 }
631 }
632
633 #ifdef DEBUG_EXTRA
634 static struct FS_QENTRY pq[60];
635 static int qp;
636
637 static struct FS_BPENTRY dq[60];
638 static int qd;
639 static void *da[60];
640 #endif
641
642 static void submit_queue (struct fs_dev *dev, struct queue *q,
643 u32 cmd, u32 p1, u32 p2, u32 p3)
644 {
645 struct FS_QENTRY *qe;
646
647 qe = get_qentry (dev, q);
648 qe->cmd = cmd;
649 qe->p0 = p1;
650 qe->p1 = p2;
651 qe->p2 = p3;
652 submit_qentry (dev, q, qe);
653
654 #ifdef DEBUG_EXTRA
655 pq[qp].cmd = cmd;
656 pq[qp].p0 = p1;
657 pq[qp].p1 = p2;
658 pq[qp].p2 = p3;
659 qp++;
660 if (qp >= 60) qp = 0;
661 #endif
662 }
663
664 /* Test the "other" way one day... -- REW */
665 #if 1
666 #define submit_command submit_queue
667 #else
668
669 static void submit_command (struct fs_dev *dev, struct queue *q,
670 u32 cmd, u32 p1, u32 p2, u32 p3)
671 {
672 write_fs (dev, CMDR0, cmd);
673 write_fs (dev, CMDR1, p1);
674 write_fs (dev, CMDR2, p2);
675 write_fs (dev, CMDR3, p3);
676 }
677 #endif
678
679
680
681 static void process_return_queue (struct fs_dev *dev, struct queue *q)
682 {
683 long rq;
684 struct FS_QENTRY *qe;
685 void *tc;
686
687 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
688 fs_dprintk (FS_DEBUG_QUEUE, "reaping return queue entry at %lx\n", rq);
689 qe = bus_to_virt (rq);
690
691 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x. (%d)\n",
692 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
693
694 switch (STATUS_CODE (qe)) {
695 case 5:
696 tc = bus_to_virt (qe->p0);
697 fs_dprintk (FS_DEBUG_ALLOC, "Free tc: %p\n", tc);
698 kfree (tc);
699 break;
700 }
701
702 write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
703 }
704 }
705
706
707 static void process_txdone_queue (struct fs_dev *dev, struct queue *q)
708 {
709 long rq;
710 long tmp;
711 struct FS_QENTRY *qe;
712 struct sk_buff *skb;
713 struct FS_BPENTRY *td;
714
715 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
716 fs_dprintk (FS_DEBUG_QUEUE, "reaping txdone entry at %lx\n", rq);
717 qe = bus_to_virt (rq);
718
719 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x: %d\n",
720 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
721
722 if (STATUS_CODE (qe) != 2)
723 fs_dprintk (FS_DEBUG_TXMEM, "queue entry: %08x %08x %08x %08x: %d\n",
724 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
725
726
727 switch (STATUS_CODE (qe)) {
728 case 0x01: /* This is for AAL0 where we put the chip in streaming mode */
729 /* Fall through */
730 case 0x02:
731 /* Process a real txdone entry. */
732 tmp = qe->p0;
733 if (tmp & 0x0f)
734 printk (KERN_WARNING "td not aligned: %ld\n", tmp);
735 tmp &= ~0x0f;
736 td = bus_to_virt (tmp);
737
738 fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p.\n",
739 td->flags, td->next, td->bsa, td->aal_bufsize, td->skb );
740
741 skb = td->skb;
742 if (skb == FS_VCC (ATM_SKB(skb)->vcc)->last_skb) {
743 wake_up_interruptible (& FS_VCC (ATM_SKB(skb)->vcc)->close_wait);
744 FS_VCC (ATM_SKB(skb)->vcc)->last_skb = NULL;
745 }
746 td->dev->ntxpckts--;
747
748 {
749 static int c=0;
750
751 if (!(c++ % 100)) {
752 fs_dprintk (FS_DEBUG_QSIZE, "[%d]", td->dev->ntxpckts);
753 }
754 }
755
756 atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
757
758 fs_dprintk (FS_DEBUG_TXMEM, "i");
759 fs_dprintk (FS_DEBUG_ALLOC, "Free t-skb: %p\n", skb);
760 fs_kfree_skb (skb);
761
762 fs_dprintk (FS_DEBUG_ALLOC, "Free trans-d: %p\n", td);
763 memset (td, ATM_POISON_FREE, sizeof(struct FS_BPENTRY));
764 kfree (td);
765 break;
766 default:
767 /* Here we get the tx purge inhibit command ... */
768 /* Action, I believe, is "don't do anything". -- REW */
769 ;
770 }
771
772 write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
773 }
774 }
775
776
777 static void process_incoming (struct fs_dev *dev, struct queue *q)
778 {
779 long rq;
780 struct FS_QENTRY *qe;
781 struct FS_BPENTRY *pe;
782 struct sk_buff *skb;
783 unsigned int channo;
784 struct atm_vcc *atm_vcc;
785
786 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
787 fs_dprintk (FS_DEBUG_QUEUE, "reaping incoming queue entry at %lx\n", rq);
788 qe = bus_to_virt (rq);
789
790 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x. ",
791 qe->cmd, qe->p0, qe->p1, qe->p2);
792
793 fs_dprintk (FS_DEBUG_QUEUE, "-> %x: %s\n",
794 STATUS_CODE (qe),
795 res_strings[STATUS_CODE(qe)]);
796
797 pe = bus_to_virt (qe->p0);
798 fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p %p.\n",
799 pe->flags, pe->next, pe->bsa, pe->aal_bufsize,
800 pe->skb, pe->fp);
801
802 channo = qe->cmd & 0xffff;
803
804 if (channo < dev->nchannels)
805 atm_vcc = dev->atm_vccs[channo];
806 else
807 atm_vcc = NULL;
808
809 /* Single buffer packet */
810 switch (STATUS_CODE (qe)) {
811 case 0x1:
812 /* Fall through for streaming mode */
813 case 0x2:/* Packet received OK.... */
814 if (atm_vcc) {
815 skb = pe->skb;
816 pe->fp->n--;
817 #if 0
818 fs_dprintk (FS_DEBUG_QUEUE, "Got skb: %p\n", skb);
819 if (FS_DEBUG_QUEUE & fs_debug) my_hd (bus_to_virt (pe->bsa), 0x20);
820 #endif
821 skb_put (skb, qe->p1 & 0xffff);
822 ATM_SKB(skb)->vcc = atm_vcc;
823 atomic_inc(&atm_vcc->stats->rx);
824 __net_timestamp(skb);
825 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p (pushed)\n", skb);
826 atm_vcc->push (atm_vcc, skb);
827 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
828 kfree (pe);
829 } else {
830 printk (KERN_ERR "Got a receive on a non-open channel %d.\n", channo);
831 }
832 break;
833 case 0x17:/* AAL 5 CRC32 error. IFF the length field is nonzero, a buffer
834 has been consumed and needs to be processed. -- REW */
835 if (qe->p1 & 0xffff) {
836 pe = bus_to_virt (qe->p0);
837 pe->fp->n--;
838 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", pe->skb);
839 dev_kfree_skb_any (pe->skb);
840 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
841 kfree (pe);
842 }
843 if (atm_vcc)
844 atomic_inc(&atm_vcc->stats->rx_drop);
845 break;
846 case 0x1f: /* Reassembly abort: no buffers. */
847 /* Silently increment error counter. */
848 if (atm_vcc)
849 atomic_inc(&atm_vcc->stats->rx_drop);
850 break;
851 default: /* Hmm. Haven't written the code to handle the others yet... -- REW */
852 printk (KERN_WARNING "Don't know what to do with RX status %x: %s.\n",
853 STATUS_CODE(qe), res_strings[STATUS_CODE (qe)]);
854 }
855 write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
856 }
857 }
858
859
860
861 #define DO_DIRECTION(tp) ((tp)->traffic_class != ATM_NONE)
862
863 static int fs_open(struct atm_vcc *atm_vcc)
864 {
865 struct fs_dev *dev;
866 struct fs_vcc *vcc;
867 struct fs_transmit_config *tc;
868 struct atm_trafprm * txtp;
869 struct atm_trafprm * rxtp;
870 /* struct fs_receive_config *rc;*/
871 /* struct FS_QENTRY *qe; */
872 int error;
873 int bfp;
874 int to;
875 unsigned short tmc0;
876 short vpi = atm_vcc->vpi;
877 int vci = atm_vcc->vci;
878
879 func_enter ();
880
881 dev = FS_DEV(atm_vcc->dev);
882 fs_dprintk (FS_DEBUG_OPEN, "fs: open on dev: %p, vcc at %p\n",
883 dev, atm_vcc);
884
885 if (vci != ATM_VPI_UNSPEC && vpi != ATM_VCI_UNSPEC)
886 set_bit(ATM_VF_ADDR, &atm_vcc->flags);
887
888 if ((atm_vcc->qos.aal != ATM_AAL5) &&
889 (atm_vcc->qos.aal != ATM_AAL2))
890 return -EINVAL; /* XXX AAL0 */
891
892 fs_dprintk (FS_DEBUG_OPEN, "fs: (itf %d): open %d.%d\n",
893 atm_vcc->dev->number, atm_vcc->vpi, atm_vcc->vci);
894
895 /* XXX handle qos parameters (rate limiting) ? */
896
897 vcc = kmalloc(sizeof(struct fs_vcc), GFP_KERNEL);
898 fs_dprintk (FS_DEBUG_ALLOC, "Alloc VCC: %p(%Zd)\n", vcc, sizeof(struct fs_vcc));
899 if (!vcc) {
900 clear_bit(ATM_VF_ADDR, &atm_vcc->flags);
901 return -ENOMEM;
902 }
903
904 atm_vcc->dev_data = vcc;
905 vcc->last_skb = NULL;
906
907 init_waitqueue_head (&vcc->close_wait);
908
909 txtp = &atm_vcc->qos.txtp;
910 rxtp = &atm_vcc->qos.rxtp;
911
912 if (!test_bit(ATM_VF_PARTIAL, &atm_vcc->flags)) {
913 if (IS_FS50(dev)) {
914 /* Increment the channel numer: take a free one next time. */
915 for (to=33;to;to--, dev->channo++) {
916 /* We only have 32 channels */
917 if (dev->channo >= 32)
918 dev->channo = 0;
919 /* If we need to do RX, AND the RX is inuse, try the next */
920 if (DO_DIRECTION(rxtp) && dev->atm_vccs[dev->channo])
921 continue;
922 /* If we need to do TX, AND the TX is inuse, try the next */
923 if (DO_DIRECTION(txtp) && test_bit (dev->channo, dev->tx_inuse))
924 continue;
925 /* Ok, both are free! (or not needed) */
926 break;
927 }
928 if (!to) {
929 printk ("No more free channels for FS50..\n");
930 return -EBUSY;
931 }
932 vcc->channo = dev->channo;
933 dev->channo &= dev->channel_mask;
934
935 } else {
936 vcc->channo = (vpi << FS155_VCI_BITS) | (vci);
937 if (((DO_DIRECTION(rxtp) && dev->atm_vccs[vcc->channo])) ||
938 ( DO_DIRECTION(txtp) && test_bit (vcc->channo, dev->tx_inuse))) {
939 printk ("Channel is in use for FS155.\n");
940 return -EBUSY;
941 }
942 }
943 fs_dprintk (FS_DEBUG_OPEN, "OK. Allocated channel %x(%d).\n",
944 vcc->channo, vcc->channo);
945 }
946
947 if (DO_DIRECTION (txtp)) {
948 tc = kmalloc (sizeof (struct fs_transmit_config), GFP_KERNEL);
949 fs_dprintk (FS_DEBUG_ALLOC, "Alloc tc: %p(%Zd)\n",
950 tc, sizeof (struct fs_transmit_config));
951 if (!tc) {
952 fs_dprintk (FS_DEBUG_OPEN, "fs: can't alloc transmit_config.\n");
953 return -ENOMEM;
954 }
955
956 /* Allocate the "open" entry from the high priority txq. This makes
957 it most likely that the chip will notice it. It also prevents us
958 from having to wait for completion. On the other hand, we may
959 need to wait for completion anyway, to see if it completed
960 successfully. */
961
962 switch (atm_vcc->qos.aal) {
963 case ATM_AAL2:
964 case ATM_AAL0:
965 tc->flags = 0
966 | TC_FLAGS_TRANSPARENT_PAYLOAD
967 | TC_FLAGS_PACKET
968 | (1 << 28)
969 | TC_FLAGS_TYPE_UBR /* XXX Change to VBR -- PVDL */
970 | TC_FLAGS_CAL0;
971 break;
972 case ATM_AAL5:
973 tc->flags = 0
974 | TC_FLAGS_AAL5
975 | TC_FLAGS_PACKET /* ??? */
976 | TC_FLAGS_TYPE_CBR
977 | TC_FLAGS_CAL0;
978 break;
979 default:
980 printk ("Unknown aal: %d\n", atm_vcc->qos.aal);
981 tc->flags = 0;
982 }
983 /* Docs are vague about this atm_hdr field. By the way, the FS
984 * chip makes odd errors if lower bits are set.... -- REW */
985 tc->atm_hdr = (vpi << 20) | (vci << 4);
986 {
987 int pcr = atm_pcr_goal (txtp);
988
989 fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
990
991 /* XXX Hmm. officially we're only allowed to do this if rounding
992 is round_down -- REW */
993 if (IS_FS50(dev)) {
994 if (pcr > 51840000/53/8) pcr = 51840000/53/8;
995 } else {
996 if (pcr > 155520000/53/8) pcr = 155520000/53/8;
997 }
998 if (!pcr) {
999 /* no rate cap */
1000 tmc0 = IS_FS50(dev)?0x61BE:0x64c9; /* Just copied over the bits from Fujitsu -- REW */
1001 } else {
1002 int r;
1003 if (pcr < 0) {
1004 r = ROUND_DOWN;
1005 pcr = -pcr;
1006 } else {
1007 r = ROUND_UP;
1008 }
1009 error = make_rate (pcr, r, &tmc0, NULL);
1010 if (error) {
1011 kfree(tc);
1012 return error;
1013 }
1014 }
1015 fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
1016 }
1017
1018 tc->TMC[0] = tmc0 | 0x4000;
1019 tc->TMC[1] = 0; /* Unused */
1020 tc->TMC[2] = 0; /* Unused */
1021 tc->TMC[3] = 0; /* Unused */
1022
1023 tc->spec = 0; /* UTOPIA address, UDF, HEC: Unused -> 0 */
1024 tc->rtag[0] = 0; /* What should I do with routing tags???
1025 -- Not used -- AS -- Thanks -- REW*/
1026 tc->rtag[1] = 0;
1027 tc->rtag[2] = 0;
1028
1029 if (fs_debug & FS_DEBUG_OPEN) {
1030 fs_dprintk (FS_DEBUG_OPEN, "TX config record:\n");
1031 my_hd (tc, sizeof (*tc));
1032 }
1033
1034 /* We now use the "submit_command" function to submit commands to
1035 the firestream. There is a define up near the definition of
1036 that routine that switches this routine between immediate write
1037 to the immediate comamnd registers and queuing the commands in
1038 the HPTXQ for execution. This last technique might be more
1039 efficient if we know we're going to submit a whole lot of
1040 commands in one go, but this driver is not setup to be able to
1041 use such a construct. So it probably doen't matter much right
1042 now. -- REW */
1043
1044 /* The command is IMMediate and INQueue. The parameters are out-of-line.. */
1045 submit_command (dev, &dev->hp_txq,
1046 QE_CMD_CONFIG_TX | QE_CMD_IMM_INQ | vcc->channo,
1047 virt_to_bus (tc), 0, 0);
1048
1049 submit_command (dev, &dev->hp_txq,
1050 QE_CMD_TX_EN | QE_CMD_IMM_INQ | vcc->channo,
1051 0, 0, 0);
1052 set_bit (vcc->channo, dev->tx_inuse);
1053 }
1054
1055 if (DO_DIRECTION (rxtp)) {
1056 dev->atm_vccs[vcc->channo] = atm_vcc;
1057
1058 for (bfp = 0;bfp < FS_NR_FREE_POOLS; bfp++)
1059 if (atm_vcc->qos.rxtp.max_sdu <= dev->rx_fp[bfp].bufsize) break;
1060 if (bfp >= FS_NR_FREE_POOLS) {
1061 fs_dprintk (FS_DEBUG_OPEN, "No free pool fits sdu: %d.\n",
1062 atm_vcc->qos.rxtp.max_sdu);
1063 /* XXX Cleanup? -- Would just calling fs_close work??? -- REW */
1064
1065 /* XXX clear tx inuse. Close TX part? */
1066 dev->atm_vccs[vcc->channo] = NULL;
1067 kfree (vcc);
1068 return -EINVAL;
1069 }
1070
1071 switch (atm_vcc->qos.aal) {
1072 case ATM_AAL0:
1073 case ATM_AAL2:
1074 submit_command (dev, &dev->hp_txq,
1075 QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo,
1076 RC_FLAGS_TRANSP |
1077 RC_FLAGS_BFPS_BFP * bfp |
1078 RC_FLAGS_RXBM_PSB, 0, 0);
1079 break;
1080 case ATM_AAL5:
1081 submit_command (dev, &dev->hp_txq,
1082 QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo,
1083 RC_FLAGS_AAL5 |
1084 RC_FLAGS_BFPS_BFP * bfp |
1085 RC_FLAGS_RXBM_PSB, 0, 0);
1086 break;
1087 };
1088 if (IS_FS50 (dev)) {
1089 submit_command (dev, &dev->hp_txq,
1090 QE_CMD_REG_WR | QE_CMD_IMM_INQ,
1091 0x80 + vcc->channo,
1092 (vpi << 16) | vci, 0 ); /* XXX -- Use defines. */
1093 }
1094 submit_command (dev, &dev->hp_txq,
1095 QE_CMD_RX_EN | QE_CMD_IMM_INQ | vcc->channo,
1096 0, 0, 0);
1097 }
1098
1099 /* Indicate we're done! */
1100 set_bit(ATM_VF_READY, &atm_vcc->flags);
1101
1102 func_exit ();
1103 return 0;
1104 }
1105
1106
1107 static void fs_close(struct atm_vcc *atm_vcc)
1108 {
1109 struct fs_dev *dev = FS_DEV (atm_vcc->dev);
1110 struct fs_vcc *vcc = FS_VCC (atm_vcc);
1111 struct atm_trafprm * txtp;
1112 struct atm_trafprm * rxtp;
1113
1114 func_enter ();
1115
1116 clear_bit(ATM_VF_READY, &atm_vcc->flags);
1117
1118 fs_dprintk (FS_DEBUG_QSIZE, "--==**[%d]**==--", dev->ntxpckts);
1119 if (vcc->last_skb) {
1120 fs_dprintk (FS_DEBUG_QUEUE, "Waiting for skb %p to be sent.\n",
1121 vcc->last_skb);
1122 /* We're going to wait for the last packet to get sent on this VC. It would
1123 be impolite not to send them don't you think?
1124 XXX
1125 We don't know which packets didn't get sent. So if we get interrupted in
1126 this sleep_on, we'll lose any reference to these packets. Memory leak!
1127 On the other hand, it's awfully convenient that we can abort a "close" that
1128 is taking too long. Maybe just use non-interruptible sleep on? -- REW */
1129 interruptible_sleep_on (& vcc->close_wait);
1130 }
1131
1132 txtp = &atm_vcc->qos.txtp;
1133 rxtp = &atm_vcc->qos.rxtp;
1134
1135
1136 /* See App note XXX (Unpublished as of now) for the reason for the
1137 removal of the "CMD_IMM_INQ" part of the TX_PURGE_INH... -- REW */
1138
1139 if (DO_DIRECTION (txtp)) {
1140 submit_command (dev, &dev->hp_txq,
1141 QE_CMD_TX_PURGE_INH | /*QE_CMD_IMM_INQ|*/ vcc->channo, 0,0,0);
1142 clear_bit (vcc->channo, dev->tx_inuse);
1143 }
1144
1145 if (DO_DIRECTION (rxtp)) {
1146 submit_command (dev, &dev->hp_txq,
1147 QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1148 dev->atm_vccs [vcc->channo] = NULL;
1149
1150 /* This means that this is configured as a receive channel */
1151 if (IS_FS50 (dev)) {
1152 /* Disable the receive filter. Is 0/0 indeed an invalid receive
1153 channel? -- REW. Yes it is. -- Hang. Ok. I'll use -1
1154 (0xfff...) -- REW */
1155 submit_command (dev, &dev->hp_txq,
1156 QE_CMD_REG_WR | QE_CMD_IMM_INQ,
1157 0x80 + vcc->channo, -1, 0 );
1158 }
1159 }
1160
1161 fs_dprintk (FS_DEBUG_ALLOC, "Free vcc: %p\n", vcc);
1162 kfree (vcc);
1163
1164 func_exit ();
1165 }
1166
1167
1168 static int fs_send (struct atm_vcc *atm_vcc, struct sk_buff *skb)
1169 {
1170 struct fs_dev *dev = FS_DEV (atm_vcc->dev);
1171 struct fs_vcc *vcc = FS_VCC (atm_vcc);
1172 struct FS_BPENTRY *td;
1173
1174 func_enter ();
1175
1176 fs_dprintk (FS_DEBUG_TXMEM, "I");
1177 fs_dprintk (FS_DEBUG_SEND, "Send: atm_vcc %p skb %p vcc %p dev %p\n",
1178 atm_vcc, skb, vcc, dev);
1179
1180 fs_dprintk (FS_DEBUG_ALLOC, "Alloc t-skb: %p (atm_send)\n", skb);
1181
1182 ATM_SKB(skb)->vcc = atm_vcc;
1183
1184 vcc->last_skb = skb;
1185
1186 td = kmalloc (sizeof (struct FS_BPENTRY), GFP_ATOMIC);
1187 fs_dprintk (FS_DEBUG_ALLOC, "Alloc transd: %p(%Zd)\n", td, sizeof (struct FS_BPENTRY));
1188 if (!td) {
1189 /* Oops out of mem */
1190 return -ENOMEM;
1191 }
1192
1193 fs_dprintk (FS_DEBUG_SEND, "first word in buffer: %x\n",
1194 *(int *) skb->data);
1195
1196 td->flags = TD_EPI | TD_DATA | skb->len;
1197 td->next = 0;
1198 td->bsa = virt_to_bus (skb->data);
1199 td->skb = skb;
1200 td->dev = dev;
1201 dev->ntxpckts++;
1202
1203 #ifdef DEBUG_EXTRA
1204 da[qd] = td;
1205 dq[qd].flags = td->flags;
1206 dq[qd].next = td->next;
1207 dq[qd].bsa = td->bsa;
1208 dq[qd].skb = td->skb;
1209 dq[qd].dev = td->dev;
1210 qd++;
1211 if (qd >= 60) qd = 0;
1212 #endif
1213
1214 submit_queue (dev, &dev->hp_txq,
1215 QE_TRANSMIT_DE | vcc->channo,
1216 virt_to_bus (td), 0,
1217 virt_to_bus (td));
1218
1219 fs_dprintk (FS_DEBUG_QUEUE, "in send: txq %d txrq %d\n",
1220 read_fs (dev, Q_EA (dev->hp_txq.offset)) -
1221 read_fs (dev, Q_SA (dev->hp_txq.offset)),
1222 read_fs (dev, Q_EA (dev->tx_relq.offset)) -
1223 read_fs (dev, Q_SA (dev->tx_relq.offset)));
1224
1225 func_exit ();
1226 return 0;
1227 }
1228
1229
1230 /* Some function placeholders for functions we don't yet support. */
1231
1232 #if 0
1233 static int fs_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
1234 {
1235 func_enter ();
1236 func_exit ();
1237 return -ENOIOCTLCMD;
1238 }
1239
1240
1241 static int fs_getsockopt(struct atm_vcc *vcc,int level,int optname,
1242 void __user *optval,int optlen)
1243 {
1244 func_enter ();
1245 func_exit ();
1246 return 0;
1247 }
1248
1249
1250 static int fs_setsockopt(struct atm_vcc *vcc,int level,int optname,
1251 void __user *optval,int optlen)
1252 {
1253 func_enter ();
1254 func_exit ();
1255 return 0;
1256 }
1257
1258
1259 static void fs_phy_put(struct atm_dev *dev,unsigned char value,
1260 unsigned long addr)
1261 {
1262 func_enter ();
1263 func_exit ();
1264 }
1265
1266
1267 static unsigned char fs_phy_get(struct atm_dev *dev,unsigned long addr)
1268 {
1269 func_enter ();
1270 func_exit ();
1271 return 0;
1272 }
1273
1274
1275 static int fs_change_qos(struct atm_vcc *vcc,struct atm_qos *qos,int flags)
1276 {
1277 func_enter ();
1278 func_exit ();
1279 return 0;
1280 };
1281
1282 #endif
1283
1284
1285 static const struct atmdev_ops ops = {
1286 .open = fs_open,
1287 .close = fs_close,
1288 .send = fs_send,
1289 .owner = THIS_MODULE,
1290 /* ioctl: fs_ioctl, */
1291 /* getsockopt: fs_getsockopt, */
1292 /* setsockopt: fs_setsockopt, */
1293 /* change_qos: fs_change_qos, */
1294
1295 /* For now implement these internally here... */
1296 /* phy_put: fs_phy_put, */
1297 /* phy_get: fs_phy_get, */
1298 };
1299
1300
1301 static void __devinit undocumented_pci_fix (struct pci_dev *pdev)
1302 {
1303 u32 tint;
1304
1305 /* The Windows driver says: */
1306 /* Switch off FireStream Retry Limit Threshold
1307 */
1308
1309 /* The register at 0x28 is documented as "reserved", no further
1310 comments. */
1311
1312 pci_read_config_dword (pdev, 0x28, &tint);
1313 if (tint != 0x80) {
1314 tint = 0x80;
1315 pci_write_config_dword (pdev, 0x28, tint);
1316 }
1317 }
1318
1319
1320
1321 /**************************************************************************
1322 * PHY routines *
1323 **************************************************************************/
1324
1325 static void __devinit write_phy (struct fs_dev *dev, int regnum, int val)
1326 {
1327 submit_command (dev, &dev->hp_txq, QE_CMD_PRP_WR | QE_CMD_IMM_INQ,
1328 regnum, val, 0);
1329 }
1330
1331 static int __devinit init_phy (struct fs_dev *dev, struct reginit_item *reginit)
1332 {
1333 int i;
1334
1335 func_enter ();
1336 while (reginit->reg != PHY_EOF) {
1337 if (reginit->reg == PHY_CLEARALL) {
1338 /* "PHY_CLEARALL means clear all registers. Numregisters is in "val". */
1339 for (i=0;i<reginit->val;i++) {
1340 write_phy (dev, i, 0);
1341 }
1342 } else {
1343 write_phy (dev, reginit->reg, reginit->val);
1344 }
1345 reginit++;
1346 }
1347 func_exit ();
1348 return 0;
1349 }
1350
1351 static void reset_chip (struct fs_dev *dev)
1352 {
1353 int i;
1354
1355 write_fs (dev, SARMODE0, SARMODE0_SRTS0);
1356
1357 /* Undocumented delay */
1358 udelay (128);
1359
1360 /* The "internal registers are documented to all reset to zero, but
1361 comments & code in the Windows driver indicates that the pools are
1362 NOT reset. */
1363 for (i=0;i < FS_NR_FREE_POOLS;i++) {
1364 write_fs (dev, FP_CNF (RXB_FP(i)), 0);
1365 write_fs (dev, FP_SA (RXB_FP(i)), 0);
1366 write_fs (dev, FP_EA (RXB_FP(i)), 0);
1367 write_fs (dev, FP_CNT (RXB_FP(i)), 0);
1368 write_fs (dev, FP_CTU (RXB_FP(i)), 0);
1369 }
1370
1371 /* The same goes for the match channel registers, although those are
1372 NOT documented that way in the Windows driver. -- REW */
1373 /* The Windows driver DOES write 0 to these registers somewhere in
1374 the init sequence. However, a small hardware-feature, will
1375 prevent reception of data on VPI/VCI = 0/0 (Unless the channel
1376 allocated happens to have no disabled channels that have a lower
1377 number. -- REW */
1378
1379 /* Clear the match channel registers. */
1380 if (IS_FS50 (dev)) {
1381 for (i=0;i<FS50_NR_CHANNELS;i++) {
1382 write_fs (dev, 0x200 + i * 4, -1);
1383 }
1384 }
1385 }
1386
1387 static void __devinit *aligned_kmalloc (int size, gfp_t flags, int alignment)
1388 {
1389 void *t;
1390
1391 if (alignment <= 0x10) {
1392 t = kmalloc (size, flags);
1393 if ((unsigned long)t & (alignment-1)) {
1394 printk ("Kmalloc doesn't align things correctly! %p\n", t);
1395 kfree (t);
1396 return aligned_kmalloc (size, flags, alignment * 4);
1397 }
1398 return t;
1399 }
1400 printk (KERN_ERR "Request for > 0x10 alignment not yet implemented (hard!)\n");
1401 return NULL;
1402 }
1403
1404 static int __devinit init_q (struct fs_dev *dev,
1405 struct queue *txq, int queue, int nentries, int is_rq)
1406 {
1407 int sz = nentries * sizeof (struct FS_QENTRY);
1408 struct FS_QENTRY *p;
1409
1410 func_enter ();
1411
1412 fs_dprintk (FS_DEBUG_INIT, "Inititing queue at %x: %d entries:\n",
1413 queue, nentries);
1414
1415 p = aligned_kmalloc (sz, GFP_KERNEL, 0x10);
1416 fs_dprintk (FS_DEBUG_ALLOC, "Alloc queue: %p(%d)\n", p, sz);
1417
1418 if (!p) return 0;
1419
1420 write_fs (dev, Q_SA(queue), virt_to_bus(p));
1421 write_fs (dev, Q_EA(queue), virt_to_bus(p+nentries-1));
1422 write_fs (dev, Q_WP(queue), virt_to_bus(p));
1423 write_fs (dev, Q_RP(queue), virt_to_bus(p));
1424 if (is_rq) {
1425 /* Configuration for the receive queue: 0: interrupt immediately,
1426 no pre-warning to empty queues: We do our best to keep the
1427 queue filled anyway. */
1428 write_fs (dev, Q_CNF(queue), 0 );
1429 }
1430
1431 txq->sa = p;
1432 txq->ea = p;
1433 txq->offset = queue;
1434
1435 func_exit ();
1436 return 1;
1437 }
1438
1439
1440 static int __devinit init_fp (struct fs_dev *dev,
1441 struct freepool *fp, int queue, int bufsize, int nr_buffers)
1442 {
1443 func_enter ();
1444
1445 fs_dprintk (FS_DEBUG_INIT, "Inititing free pool at %x:\n", queue);
1446
1447 write_fs (dev, FP_CNF(queue), (bufsize * RBFP_RBS) | RBFP_RBSVAL | RBFP_CME);
1448 write_fs (dev, FP_SA(queue), 0);
1449 write_fs (dev, FP_EA(queue), 0);
1450 write_fs (dev, FP_CTU(queue), 0);
1451 write_fs (dev, FP_CNT(queue), 0);
1452
1453 fp->offset = queue;
1454 fp->bufsize = bufsize;
1455 fp->nr_buffers = nr_buffers;
1456
1457 func_exit ();
1458 return 1;
1459 }
1460
1461
1462 static inline int nr_buffers_in_freepool (struct fs_dev *dev, struct freepool *fp)
1463 {
1464 #if 0
1465 /* This seems to be unreliable.... */
1466 return read_fs (dev, FP_CNT (fp->offset));
1467 #else
1468 return fp->n;
1469 #endif
1470 }
1471
1472
1473 /* Check if this gets going again if a pool ever runs out. -- Yes, it
1474 does. I've seen "receive abort: no buffers" and things started
1475 working again after that... -- REW */
1476
1477 static void top_off_fp (struct fs_dev *dev, struct freepool *fp,
1478 gfp_t gfp_flags)
1479 {
1480 struct FS_BPENTRY *qe, *ne;
1481 struct sk_buff *skb;
1482 int n = 0;
1483 u32 qe_tmp;
1484
1485 fs_dprintk (FS_DEBUG_QUEUE, "Topping off queue at %x (%d-%d/%d)\n",
1486 fp->offset, read_fs (dev, FP_CNT (fp->offset)), fp->n,
1487 fp->nr_buffers);
1488 while (nr_buffers_in_freepool(dev, fp) < fp->nr_buffers) {
1489
1490 skb = alloc_skb (fp->bufsize, gfp_flags);
1491 fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-skb: %p(%d)\n", skb, fp->bufsize);
1492 if (!skb) break;
1493 ne = kmalloc (sizeof (struct FS_BPENTRY), gfp_flags);
1494 fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-d: %p(%Zd)\n", ne, sizeof (struct FS_BPENTRY));
1495 if (!ne) {
1496 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", skb);
1497 dev_kfree_skb_any (skb);
1498 break;
1499 }
1500
1501 fs_dprintk (FS_DEBUG_QUEUE, "Adding skb %p desc %p -> %p(%p) ",
1502 skb, ne, skb->data, skb->head);
1503 n++;
1504 ne->flags = FP_FLAGS_EPI | fp->bufsize;
1505 ne->next = virt_to_bus (NULL);
1506 ne->bsa = virt_to_bus (skb->data);
1507 ne->aal_bufsize = fp->bufsize;
1508 ne->skb = skb;
1509 ne->fp = fp;
1510
1511 /*
1512 * FIXME: following code encodes and decodes
1513 * machine pointers (could be 64-bit) into a
1514 * 32-bit register.
1515 */
1516
1517 qe_tmp = read_fs (dev, FP_EA(fp->offset));
1518 fs_dprintk (FS_DEBUG_QUEUE, "link at %x\n", qe_tmp);
1519 if (qe_tmp) {
1520 qe = bus_to_virt ((long) qe_tmp);
1521 qe->next = virt_to_bus(ne);
1522 qe->flags &= ~FP_FLAGS_EPI;
1523 } else
1524 write_fs (dev, FP_SA(fp->offset), virt_to_bus(ne));
1525
1526 write_fs (dev, FP_EA(fp->offset), virt_to_bus (ne));
1527 fp->n++; /* XXX Atomic_inc? */
1528 write_fs (dev, FP_CTU(fp->offset), 1);
1529 }
1530
1531 fs_dprintk (FS_DEBUG_QUEUE, "Added %d entries. \n", n);
1532 }
1533
1534 static void __devexit free_queue (struct fs_dev *dev, struct queue *txq)
1535 {
1536 func_enter ();
1537
1538 write_fs (dev, Q_SA(txq->offset), 0);
1539 write_fs (dev, Q_EA(txq->offset), 0);
1540 write_fs (dev, Q_RP(txq->offset), 0);
1541 write_fs (dev, Q_WP(txq->offset), 0);
1542 /* Configuration ? */
1543
1544 fs_dprintk (FS_DEBUG_ALLOC, "Free queue: %p\n", txq->sa);
1545 kfree (txq->sa);
1546
1547 func_exit ();
1548 }
1549
1550 static void __devexit free_freepool (struct fs_dev *dev, struct freepool *fp)
1551 {
1552 func_enter ();
1553
1554 write_fs (dev, FP_CNF(fp->offset), 0);
1555 write_fs (dev, FP_SA (fp->offset), 0);
1556 write_fs (dev, FP_EA (fp->offset), 0);
1557 write_fs (dev, FP_CNT(fp->offset), 0);
1558 write_fs (dev, FP_CTU(fp->offset), 0);
1559
1560 func_exit ();
1561 }
1562
1563
1564
1565 static irqreturn_t fs_irq (int irq, void *dev_id)
1566 {
1567 int i;
1568 u32 status;
1569 struct fs_dev *dev = dev_id;
1570
1571 status = read_fs (dev, ISR);
1572 if (!status)
1573 return IRQ_NONE;
1574
1575 func_enter ();
1576
1577 #ifdef IRQ_RATE_LIMIT
1578 /* Aaargh! I'm ashamed. This costs more lines-of-code than the actual
1579 interrupt routine!. (Well, used to when I wrote that comment) -- REW */
1580 {
1581 static int lastjif;
1582 static int nintr=0;
1583
1584 if (lastjif == jiffies) {
1585 if (++nintr > IRQ_RATE_LIMIT) {
1586 free_irq (dev->irq, dev_id);
1587 printk (KERN_ERR "fs: Too many interrupts. Turning off interrupt %d.\n",
1588 dev->irq);
1589 }
1590 } else {
1591 lastjif = jiffies;
1592 nintr = 0;
1593 }
1594 }
1595 #endif
1596 fs_dprintk (FS_DEBUG_QUEUE, "in intr: txq %d txrq %d\n",
1597 read_fs (dev, Q_EA (dev->hp_txq.offset)) -
1598 read_fs (dev, Q_SA (dev->hp_txq.offset)),
1599 read_fs (dev, Q_EA (dev->tx_relq.offset)) -
1600 read_fs (dev, Q_SA (dev->tx_relq.offset)));
1601
1602 /* print the bits in the ISR register. */
1603 if (fs_debug & FS_DEBUG_IRQ) {
1604 /* The FS_DEBUG things are unnecessary here. But this way it is
1605 clear for grep that these are debug prints. */
1606 fs_dprintk (FS_DEBUG_IRQ, "IRQ status:");
1607 for (i=0;i<27;i++)
1608 if (status & (1 << i))
1609 fs_dprintk (FS_DEBUG_IRQ, " %s", irq_bitname[i]);
1610 fs_dprintk (FS_DEBUG_IRQ, "\n");
1611 }
1612
1613 if (status & ISR_RBRQ0_W) {
1614 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (0)!!!!\n");
1615 process_incoming (dev, &dev->rx_rq[0]);
1616 /* items mentioned on RBRQ0 are from FP 0 or 1. */
1617 top_off_fp (dev, &dev->rx_fp[0], GFP_ATOMIC);
1618 top_off_fp (dev, &dev->rx_fp[1], GFP_ATOMIC);
1619 }
1620
1621 if (status & ISR_RBRQ1_W) {
1622 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (1)!!!!\n");
1623 process_incoming (dev, &dev->rx_rq[1]);
1624 top_off_fp (dev, &dev->rx_fp[2], GFP_ATOMIC);
1625 top_off_fp (dev, &dev->rx_fp[3], GFP_ATOMIC);
1626 }
1627
1628 if (status & ISR_RBRQ2_W) {
1629 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (2)!!!!\n");
1630 process_incoming (dev, &dev->rx_rq[2]);
1631 top_off_fp (dev, &dev->rx_fp[4], GFP_ATOMIC);
1632 top_off_fp (dev, &dev->rx_fp[5], GFP_ATOMIC);
1633 }
1634
1635 if (status & ISR_RBRQ3_W) {
1636 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (3)!!!!\n");
1637 process_incoming (dev, &dev->rx_rq[3]);
1638 top_off_fp (dev, &dev->rx_fp[6], GFP_ATOMIC);
1639 top_off_fp (dev, &dev->rx_fp[7], GFP_ATOMIC);
1640 }
1641
1642 if (status & ISR_CSQ_W) {
1643 fs_dprintk (FS_DEBUG_IRQ, "Command executed ok!\n");
1644 process_return_queue (dev, &dev->st_q);
1645 }
1646
1647 if (status & ISR_TBRQ_W) {
1648 fs_dprintk (FS_DEBUG_IRQ, "Data tramsitted!\n");
1649 process_txdone_queue (dev, &dev->tx_relq);
1650 }
1651
1652 func_exit ();
1653 return IRQ_HANDLED;
1654 }
1655
1656
1657 #ifdef FS_POLL_FREQ
1658 static void fs_poll (unsigned long data)
1659 {
1660 struct fs_dev *dev = (struct fs_dev *) data;
1661
1662 fs_irq (0, dev);
1663 dev->timer.expires = jiffies + FS_POLL_FREQ;
1664 add_timer (&dev->timer);
1665 }
1666 #endif
1667
1668 static int __devinit fs_init (struct fs_dev *dev)
1669 {
1670 struct pci_dev *pci_dev;
1671 int isr, to;
1672 int i;
1673
1674 func_enter ();
1675 pci_dev = dev->pci_dev;
1676
1677 printk (KERN_INFO "found a FireStream %d card, base %16llx, irq%d.\n",
1678 IS_FS50(dev)?50:155,
1679 (unsigned long long)pci_resource_start(pci_dev, 0),
1680 dev->pci_dev->irq);
1681
1682 if (fs_debug & FS_DEBUG_INIT)
1683 my_hd ((unsigned char *) dev, sizeof (*dev));
1684
1685 undocumented_pci_fix (pci_dev);
1686
1687 dev->hw_base = pci_resource_start(pci_dev, 0);
1688
1689 dev->base = ioremap(dev->hw_base, 0x1000);
1690
1691 reset_chip (dev);
1692
1693 write_fs (dev, SARMODE0, 0
1694 | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */
1695 | (1 * SARMODE0_INTMODE_READCLEAR)
1696 | (1 * SARMODE0_CWRE)
1697 | IS_FS50(dev)?SARMODE0_PRPWT_FS50_5:
1698 SARMODE0_PRPWT_FS155_3
1699 | (1 * SARMODE0_CALSUP_1)
1700 | IS_FS50 (dev)?(0
1701 | SARMODE0_RXVCS_32
1702 | SARMODE0_ABRVCS_32
1703 | SARMODE0_TXVCS_32):
1704 (0
1705 | SARMODE0_RXVCS_1k
1706 | SARMODE0_ABRVCS_1k
1707 | SARMODE0_TXVCS_1k));
1708
1709 /* 10ms * 100 is 1 second. That should be enough, as AN3:9 says it takes
1710 1ms. */
1711 to = 100;
1712 while (--to) {
1713 isr = read_fs (dev, ISR);
1714
1715 /* This bit is documented as "RESERVED" */
1716 if (isr & ISR_INIT_ERR) {
1717 printk (KERN_ERR "Error initializing the FS... \n");
1718 goto unmap;
1719 }
1720 if (isr & ISR_INIT) {
1721 fs_dprintk (FS_DEBUG_INIT, "Ha! Initialized OK!\n");
1722 break;
1723 }
1724
1725 /* Try again after 10ms. */
1726 msleep(10);
1727 }
1728
1729 if (!to) {
1730 printk (KERN_ERR "timeout initializing the FS... \n");
1731 goto unmap;
1732 }
1733
1734 /* XXX fix for fs155 */
1735 dev->channel_mask = 0x1f;
1736 dev->channo = 0;
1737
1738 /* AN3: 10 */
1739 write_fs (dev, SARMODE1, 0
1740 | (fs_keystream * SARMODE1_DEFHEC) /* XXX PHY */
1741 | ((loopback == 1) * SARMODE1_TSTLP) /* XXX Loopback mode enable... */
1742 | (1 * SARMODE1_DCRM)
1743 | (1 * SARMODE1_DCOAM)
1744 | (0 * SARMODE1_OAMCRC)
1745 | (0 * SARMODE1_DUMPE)
1746 | (0 * SARMODE1_GPLEN)
1747 | (0 * SARMODE1_GNAM)
1748 | (0 * SARMODE1_GVAS)
1749 | (0 * SARMODE1_GPAS)
1750 | (1 * SARMODE1_GPRI)
1751 | (0 * SARMODE1_PMS)
1752 | (0 * SARMODE1_GFCR)
1753 | (1 * SARMODE1_HECM2)
1754 | (1 * SARMODE1_HECM1)
1755 | (1 * SARMODE1_HECM0)
1756 | (1 << 12) /* That's what hang's driver does. Program to 0 */
1757 | (0 * 0xff) /* XXX FS155 */);
1758
1759
1760 /* Cal prescale etc */
1761
1762 /* AN3: 11 */
1763 write_fs (dev, TMCONF, 0x0000000f);
1764 write_fs (dev, CALPRESCALE, 0x01010101 * num);
1765 write_fs (dev, 0x80, 0x000F00E4);
1766
1767 /* AN3: 12 */
1768 write_fs (dev, CELLOSCONF, 0
1769 | ( 0 * CELLOSCONF_CEN)
1770 | ( CELLOSCONF_SC1)
1771 | (0x80 * CELLOSCONF_COBS)
1772 | (num * CELLOSCONF_COPK) /* Changed from 0xff to 0x5a */
1773 | (num * CELLOSCONF_COST));/* after a hint from Hang.
1774 * performance jumped 50->70... */
1775
1776 /* Magic value by Hang */
1777 write_fs (dev, CELLOSCONF_COST, 0x0B809191);
1778
1779 if (IS_FS50 (dev)) {
1780 write_fs (dev, RAS0, RAS0_DCD_XHLT);
1781 dev->atm_dev->ci_range.vpi_bits = 12;
1782 dev->atm_dev->ci_range.vci_bits = 16;
1783 dev->nchannels = FS50_NR_CHANNELS;
1784 } else {
1785 write_fs (dev, RAS0, RAS0_DCD_XHLT
1786 | (((1 << FS155_VPI_BITS) - 1) * RAS0_VPSEL)
1787 | (((1 << FS155_VCI_BITS) - 1) * RAS0_VCSEL));
1788 /* We can chose the split arbitarily. We might be able to
1789 support more. Whatever. This should do for now. */
1790 dev->atm_dev->ci_range.vpi_bits = FS155_VPI_BITS;
1791 dev->atm_dev->ci_range.vci_bits = FS155_VCI_BITS;
1792
1793 /* Address bits we can't use should be compared to 0. */
1794 write_fs (dev, RAC, 0);
1795
1796 /* Manual (AN9, page 6) says ASF1=0 means compare Utopia address
1797 * too. I can't find ASF1 anywhere. Anyway, we AND with just the
1798 * other bits, then compare with 0, which is exactly what we
1799 * want. */
1800 write_fs (dev, RAM, (1 << (28 - FS155_VPI_BITS - FS155_VCI_BITS)) - 1);
1801 dev->nchannels = FS155_NR_CHANNELS;
1802 }
1803 dev->atm_vccs = kcalloc (dev->nchannels, sizeof (struct atm_vcc *),
1804 GFP_KERNEL);
1805 fs_dprintk (FS_DEBUG_ALLOC, "Alloc atmvccs: %p(%Zd)\n",
1806 dev->atm_vccs, dev->nchannels * sizeof (struct atm_vcc *));
1807
1808 if (!dev->atm_vccs) {
1809 printk (KERN_WARNING "Couldn't allocate memory for VCC buffers. Woops!\n");
1810 /* XXX Clean up..... */
1811 goto unmap;
1812 }
1813
1814 dev->tx_inuse = kzalloc (dev->nchannels / 8 /* bits/byte */ , GFP_KERNEL);
1815 fs_dprintk (FS_DEBUG_ALLOC, "Alloc tx_inuse: %p(%d)\n",
1816 dev->atm_vccs, dev->nchannels / 8);
1817
1818 if (!dev->tx_inuse) {
1819 printk (KERN_WARNING "Couldn't allocate memory for tx_inuse bits!\n");
1820 /* XXX Clean up..... */
1821 goto unmap;
1822 }
1823 /* -- RAS1 : FS155 and 50 differ. Default (0) should be OK for both */
1824 /* -- RAS2 : FS50 only: Default is OK. */
1825
1826 /* DMAMODE, default should be OK. -- REW */
1827 write_fs (dev, DMAMR, DMAMR_TX_MODE_FULL);
1828
1829 init_q (dev, &dev->hp_txq, TX_PQ(TXQ_HP), TXQ_NENTRIES, 0);
1830 init_q (dev, &dev->lp_txq, TX_PQ(TXQ_LP), TXQ_NENTRIES, 0);
1831 init_q (dev, &dev->tx_relq, TXB_RQ, TXQ_NENTRIES, 1);
1832 init_q (dev, &dev->st_q, ST_Q, TXQ_NENTRIES, 1);
1833
1834 for (i=0;i < FS_NR_FREE_POOLS;i++) {
1835 init_fp (dev, &dev->rx_fp[i], RXB_FP(i),
1836 rx_buf_sizes[i], rx_pool_sizes[i]);
1837 top_off_fp (dev, &dev->rx_fp[i], GFP_KERNEL);
1838 }
1839
1840
1841 for (i=0;i < FS_NR_RX_QUEUES;i++)
1842 init_q (dev, &dev->rx_rq[i], RXB_RQ(i), RXRQ_NENTRIES, 1);
1843
1844 dev->irq = pci_dev->irq;
1845 if (request_irq (dev->irq, fs_irq, IRQF_SHARED, "firestream", dev)) {
1846 printk (KERN_WARNING "couldn't get irq %d for firestream.\n", pci_dev->irq);
1847 /* XXX undo all previous stuff... */
1848 goto unmap;
1849 }
1850 fs_dprintk (FS_DEBUG_INIT, "Grabbed irq %d for dev at %p.\n", dev->irq, dev);
1851
1852 /* We want to be notified of most things. Just the statistics count
1853 overflows are not interesting */
1854 write_fs (dev, IMR, 0
1855 | ISR_RBRQ0_W
1856 | ISR_RBRQ1_W
1857 | ISR_RBRQ2_W
1858 | ISR_RBRQ3_W
1859 | ISR_TBRQ_W
1860 | ISR_CSQ_W);
1861
1862 write_fs (dev, SARMODE0, 0
1863 | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */
1864 | (1 * SARMODE0_GINT)
1865 | (1 * SARMODE0_INTMODE_READCLEAR)
1866 | (0 * SARMODE0_CWRE)
1867 | (IS_FS50(dev)?SARMODE0_PRPWT_FS50_5:
1868 SARMODE0_PRPWT_FS155_3)
1869 | (1 * SARMODE0_CALSUP_1)
1870 | (IS_FS50 (dev)?(0
1871 | SARMODE0_RXVCS_32
1872 | SARMODE0_ABRVCS_32
1873 | SARMODE0_TXVCS_32):
1874 (0
1875 | SARMODE0_RXVCS_1k
1876 | SARMODE0_ABRVCS_1k
1877 | SARMODE0_TXVCS_1k))
1878 | (1 * SARMODE0_RUN));
1879
1880 init_phy (dev, PHY_NTC_INIT);
1881
1882 if (loopback == 2) {
1883 write_phy (dev, 0x39, 0x000e);
1884 }
1885
1886 #ifdef FS_POLL_FREQ
1887 init_timer (&dev->timer);
1888 dev->timer.data = (unsigned long) dev;
1889 dev->timer.function = fs_poll;
1890 dev->timer.expires = jiffies + FS_POLL_FREQ;
1891 add_timer (&dev->timer);
1892 #endif
1893
1894 dev->atm_dev->dev_data = dev;
1895
1896 func_exit ();
1897 return 0;
1898 unmap:
1899 iounmap(dev->base);
1900 return 1;
1901 }
1902
1903 static int __devinit firestream_init_one (struct pci_dev *pci_dev,
1904 const struct pci_device_id *ent)
1905 {
1906 struct atm_dev *atm_dev;
1907 struct fs_dev *fs_dev;
1908
1909 if (pci_enable_device(pci_dev))
1910 goto err_out;
1911
1912 fs_dev = kzalloc (sizeof (struct fs_dev), GFP_KERNEL);
1913 fs_dprintk (FS_DEBUG_ALLOC, "Alloc fs-dev: %p(%Zd)\n",
1914 fs_dev, sizeof (struct fs_dev));
1915 if (!fs_dev)
1916 goto err_out;
1917 atm_dev = atm_dev_register("fs", &ops, -1, NULL);
1918 if (!atm_dev)
1919 goto err_out_free_fs_dev;
1920
1921 fs_dev->pci_dev = pci_dev;
1922 fs_dev->atm_dev = atm_dev;
1923 fs_dev->flags = ent->driver_data;
1924
1925 if (fs_init(fs_dev))
1926 goto err_out_free_atm_dev;
1927
1928 fs_dev->next = fs_boards;
1929 fs_boards = fs_dev;
1930 return 0;
1931
1932 err_out_free_atm_dev:
1933 atm_dev_deregister(atm_dev);
1934 err_out_free_fs_dev:
1935 kfree(fs_dev);
1936 err_out:
1937 return -ENODEV;
1938 }
1939
1940 static void __devexit firestream_remove_one (struct pci_dev *pdev)
1941 {
1942 int i;
1943 struct fs_dev *dev, *nxtdev;
1944 struct fs_vcc *vcc;
1945 struct FS_BPENTRY *fp, *nxt;
1946
1947 func_enter ();
1948
1949 #if 0
1950 printk ("hptxq:\n");
1951 for (i=0;i<60;i++) {
1952 printk ("%d: %08x %08x %08x %08x \n",
1953 i, pq[qp].cmd, pq[qp].p0, pq[qp].p1, pq[qp].p2);
1954 qp++;
1955 if (qp >= 60) qp = 0;
1956 }
1957
1958 printk ("descriptors:\n");
1959 for (i=0;i<60;i++) {
1960 printk ("%d: %p: %08x %08x %p %p\n",
1961 i, da[qd], dq[qd].flags, dq[qd].bsa, dq[qd].skb, dq[qd].dev);
1962 qd++;
1963 if (qd >= 60) qd = 0;
1964 }
1965 #endif
1966
1967 for (dev = fs_boards;dev != NULL;dev=nxtdev) {
1968 fs_dprintk (FS_DEBUG_CLEANUP, "Releasing resources for dev at %p.\n", dev);
1969
1970 /* XXX Hit all the tx channels too! */
1971
1972 for (i=0;i < dev->nchannels;i++) {
1973 if (dev->atm_vccs[i]) {
1974 vcc = FS_VCC (dev->atm_vccs[i]);
1975 submit_command (dev, &dev->hp_txq,
1976 QE_CMD_TX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1977 submit_command (dev, &dev->hp_txq,
1978 QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1979
1980 }
1981 }
1982
1983 /* XXX Wait a while for the chip to release all buffers. */
1984
1985 for (i=0;i < FS_NR_FREE_POOLS;i++) {
1986 for (fp=bus_to_virt (read_fs (dev, FP_SA(dev->rx_fp[i].offset)));
1987 !(fp->flags & FP_FLAGS_EPI);fp = nxt) {
1988 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb);
1989 dev_kfree_skb_any (fp->skb);
1990 nxt = bus_to_virt (fp->next);
1991 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp);
1992 kfree (fp);
1993 }
1994 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb);
1995 dev_kfree_skb_any (fp->skb);
1996 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp);
1997 kfree (fp);
1998 }
1999
2000 /* Hang the chip in "reset", prevent it clobbering memory that is
2001 no longer ours. */
2002 reset_chip (dev);
2003
2004 fs_dprintk (FS_DEBUG_CLEANUP, "Freeing irq%d.\n", dev->irq);
2005 free_irq (dev->irq, dev);
2006 del_timer (&dev->timer);
2007
2008 atm_dev_deregister(dev->atm_dev);
2009 free_queue (dev, &dev->hp_txq);
2010 free_queue (dev, &dev->lp_txq);
2011 free_queue (dev, &dev->tx_relq);
2012 free_queue (dev, &dev->st_q);
2013
2014 fs_dprintk (FS_DEBUG_ALLOC, "Free atmvccs: %p\n", dev->atm_vccs);
2015 kfree (dev->atm_vccs);
2016
2017 for (i=0;i< FS_NR_FREE_POOLS;i++)
2018 free_freepool (dev, &dev->rx_fp[i]);
2019
2020 for (i=0;i < FS_NR_RX_QUEUES;i++)
2021 free_queue (dev, &dev->rx_rq[i]);
2022
2023 iounmap(dev->base);
2024 fs_dprintk (FS_DEBUG_ALLOC, "Free fs-dev: %p\n", dev);
2025 nxtdev = dev->next;
2026 kfree (dev);
2027 }
2028
2029 func_exit ();
2030 }
2031
2032 static struct pci_device_id firestream_pci_tbl[] = {
2033 { PCI_VENDOR_ID_FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS50,
2034 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FS_IS50},
2035 { PCI_VENDOR_ID_FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS155,
2036 PCI_ANY_ID, PCI_ANY_ID, 0, 0, FS_IS155},
2037 { 0, }
2038 };
2039
2040 MODULE_DEVICE_TABLE(pci, firestream_pci_tbl);
2041
2042 static struct pci_driver firestream_driver = {
2043 .name = "firestream",
2044 .id_table = firestream_pci_tbl,
2045 .probe = firestream_init_one,
2046 .remove = __devexit_p(firestream_remove_one),
2047 };
2048
2049 static int __init firestream_init_module (void)
2050 {
2051 int error;
2052
2053 func_enter ();
2054 error = pci_register_driver(&firestream_driver);
2055 func_exit ();
2056 return error;
2057 }
2058
2059 static void __exit firestream_cleanup_module(void)
2060 {
2061 pci_unregister_driver(&firestream_driver);
2062 }
2063
2064 module_init(firestream_init_module);
2065 module_exit(firestream_cleanup_module);
2066
2067 MODULE_LICENSE("GPL");
2068
2069
2070
WRT350N Kernel Patches