drivers/ata/pata_hpt366.c

   1 /*
   2  * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
   3  *
   4  * This driver is heavily based upon:
   5  *
   6  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   7  *
   8  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   9  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
  10  * Portions Copyright (C) 2003          Red Hat Inc
  11  *
  12  *
  13  * TODO
  14  *      Maybe PLL mode
  15  *      Look into engine reset on timeout errors. Should not be
  16  *              required.
  17  */
  18
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/pci.h>
  23 #include <linux/init.h>
  24 #include <linux/blkdev.h>
  25 #include <linux/delay.h>
  26 #include <scsi/scsi_host.h>
  27 #include <linux/libata.h>
  28
  29 #define DRV_NAME        "pata_hpt366"
  30 <<<<<<< HEAD:drivers/ata/pata_hpt366.c
  31 #define DRV_VERSION     "0.6.1"
  32 =======
  33 #define DRV_VERSION     "0.6.2"
  34 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_hpt366.c
  35
  36 struct hpt_clock {
  37         u8      xfer_speed;
  38         u32     timing;
  39 };
  40
  41 /* key for bus clock timings
  42  * bit
  43  * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
  44  *        DMA. cycles = value + 1
  45  * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
  46  *        DMA. cycles = value + 1
  47  * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
  48  *        register access.
  49  * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
  50  *        register access.
  51  * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
  52  *        during task file register access.
  53  * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
  54  *        xfer.
  55  * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
  56  *        register access.
  57  * 28     UDMA enable
  58  * 29     DMA enable
  59  * 30     PIO_MST enable. if set, the chip is in bus master mode during
  60  *        PIO.
  61  * 31     FIFO enable.
  62  */
  63
  64 static const struct hpt_clock hpt366_40[] = {
  65         {       XFER_UDMA_4,    0x900fd943      },
  66         {       XFER_UDMA_3,    0x900ad943      },
  67         {       XFER_UDMA_2,    0x900bd943      },
  68         {       XFER_UDMA_1,    0x9008d943      },
  69         {       XFER_UDMA_0,    0x9008d943      },
  70
  71         {       XFER_MW_DMA_2,  0xa008d943      },
  72         {       XFER_MW_DMA_1,  0xa010d955      },
  73         {       XFER_MW_DMA_0,  0xa010d9fc      },
  74
  75         {       XFER_PIO_4,     0xc008d963      },
  76         {       XFER_PIO_3,     0xc010d974      },
  77         {       XFER_PIO_2,     0xc010d997      },
  78         {       XFER_PIO_1,     0xc010d9c7      },
  79         {       XFER_PIO_0,     0xc018d9d9      },
  80         {       0,              0x0120d9d9      }
  81 };
  82
  83 static const struct hpt_clock hpt366_33[] = {
  84         {       XFER_UDMA_4,    0x90c9a731      },
  85         {       XFER_UDMA_3,    0x90cfa731      },
  86         {       XFER_UDMA_2,    0x90caa731      },
  87         {       XFER_UDMA_1,    0x90cba731      },
  88         {       XFER_UDMA_0,    0x90c8a731      },
  89
  90         {       XFER_MW_DMA_2,  0xa0c8a731      },
  91         {       XFER_MW_DMA_1,  0xa0c8a732      },      /* 0xa0c8a733 */
  92         {       XFER_MW_DMA_0,  0xa0c8a797      },
  93
  94         {       XFER_PIO_4,     0xc0c8a731      },
  95         {       XFER_PIO_3,     0xc0c8a742      },
  96         {       XFER_PIO_2,     0xc0d0a753      },
  97         {       XFER_PIO_1,     0xc0d0a7a3      },      /* 0xc0d0a793 */
  98         {       XFER_PIO_0,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
  99         {       0,              0x0120a7a7      }
 100 };
 101
 102 static const struct hpt_clock hpt366_25[] = {
 103         {       XFER_UDMA_4,    0x90c98521      },
 104         {       XFER_UDMA_3,    0x90cf8521      },
 105         {       XFER_UDMA_2,    0x90cf8521      },
 106         {       XFER_UDMA_1,    0x90cb8521      },
 107         {       XFER_UDMA_0,    0x90cb8521      },
 108
 109         {       XFER_MW_DMA_2,  0xa0ca8521      },
 110         {       XFER_MW_DMA_1,  0xa0ca8532      },
 111         {       XFER_MW_DMA_0,  0xa0ca8575      },
 112
 113         {       XFER_PIO_4,     0xc0ca8521      },
 114         {       XFER_PIO_3,     0xc0ca8532      },
 115         {       XFER_PIO_2,     0xc0ca8542      },
 116         {       XFER_PIO_1,     0xc0d08572      },
 117         {       XFER_PIO_0,     0xc0d08585      },
 118         {       0,              0x01208585      }
 119 };
 120
 121 static const char *bad_ata33[] = {
 122         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 123         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 124         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 125         "Maxtor 90510D4",
 126         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 127         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 128         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 129         NULL
 130 };
 131
 132 static const char *bad_ata66_4[] = {
 133         "IBM-DTLA-307075",
 134         "IBM-DTLA-307060",
 135         "IBM-DTLA-307045",
 136         "IBM-DTLA-307030",
 137         "IBM-DTLA-307020",
 138         "IBM-DTLA-307015",
 139         "IBM-DTLA-305040",
 140         "IBM-DTLA-305030",
 141         "IBM-DTLA-305020",
 142         "IC35L010AVER07-0",
 143         "IC35L020AVER07-0",
 144         "IC35L030AVER07-0",
 145         "IC35L040AVER07-0",
 146         "IC35L060AVER07-0",
 147         "WDC AC310200R",
 148         NULL
 149 };
 150
 151 static const char *bad_ata66_3[] = {
 152         "WDC AC310200R",
 153         NULL
 154 };
 155
 156 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr, const char *list[])
 157 {
 158         unsigned char model_num[ATA_ID_PROD_LEN + 1];
 159         int i = 0;
 160
 161         ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
 162
 163         while (list[i] != NULL) {
 164                 if (!strcmp(list[i], model_num)) {
 165                         printk(KERN_WARNING DRV_NAME ": %s is not supported for %s.\n",
 166                                 modestr, list[i]);
 167                         return 1;
 168                 }
 169                 i++;
 170         }
 171         return 0;
 172 }
 173
 174 /**
 175  *      hpt366_filter   -       mode selection filter
 176  *      @adev: ATA device
 177  *
 178  *      Block UDMA on devices that cause trouble with this controller.
 179  */
 180
 181 static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
 182 {
 183         if (adev->class == ATA_DEV_ATA) {
 184                 if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
 185                         mask &= ~ATA_MASK_UDMA;
 186                 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
 187 <<<<<<< HEAD:drivers/ata/pata_hpt366.c
 188                         mask &= ~(0x07 << ATA_SHIFT_UDMA);
 189 =======
 190                         mask &= ~(0xF8 << ATA_SHIFT_UDMA);
 191 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_hpt366.c
 192                 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
 193 <<<<<<< HEAD:drivers/ata/pata_hpt366.c
 194                         mask &= ~(0x0F << ATA_SHIFT_UDMA);
 195 =======
 196                         mask &= ~(0xF0 << ATA_SHIFT_UDMA);
 197 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/ata/pata_hpt366.c
 198         }
 199         return ata_pci_default_filter(adev, mask);
 200 }
 201
 202 /**
 203  *      hpt36x_find_mode        -       reset the hpt36x bus
 204  *      @ap: ATA port
 205  *      @speed: transfer mode
 206  *
 207  *      Return the 32bit register programming information for this channel
 208  *      that matches the speed provided.
 209  */
 210
 211 static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
 212 {
 213         struct hpt_clock *clocks = ap->host->private_data;
 214
 215         while(clocks->xfer_speed) {
 216                 if (clocks->xfer_speed == speed)
 217                         return clocks->timing;
 218                 clocks++;
 219         }
 220         BUG();
 221         return 0xffffffffU;     /* silence compiler warning */
 222 }
 223
 224 static int hpt36x_cable_detect(struct ata_port *ap)
 225 {
 226         u8 ata66;
 227         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 228
 229         pci_read_config_byte(pdev, 0x5A, &ata66);
 230         if (ata66 & (1 << ap->port_no))
 231                 return ATA_CBL_PATA40;
 232         return ATA_CBL_PATA80;
 233 }
 234
 235 /**
 236  *      hpt366_set_piomode              -       PIO setup
 237  *      @ap: ATA interface
 238  *      @adev: device on the interface
 239  *
 240  *      Perform PIO mode setup.
 241  */
 242
 243 static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
 244 {
 245         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 246         u32 addr1, addr2;
 247         u32 reg;
 248         u32 mode;
 249         u8 fast;
 250
 251         addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 252         addr2 = 0x51 + 4 * ap->port_no;
 253
 254         /* Fast interrupt prediction disable, hold off interrupt disable */
 255         pci_read_config_byte(pdev, addr2, &fast);
 256         if (fast & 0x80) {
 257                 fast &= ~0x80;
 258                 pci_write_config_byte(pdev, addr2, fast);
 259         }
 260
 261         pci_read_config_dword(pdev, addr1, &reg);
 262         mode = hpt36x_find_mode(ap, adev->pio_mode);
 263         mode &= ~0x8000000;     /* No FIFO in PIO */
 264         mode &= ~0x30070000;    /* Leave config bits alone */
 265         reg &= 0x30070000;      /* Strip timing bits */
 266         pci_write_config_dword(pdev, addr1, reg | mode);
 267 }
 268
 269 /**
 270  *      hpt366_set_dmamode              -       DMA timing setup
 271  *      @ap: ATA interface
 272  *      @adev: Device being configured
 273  *
 274  *      Set up the channel for MWDMA or UDMA modes. Much the same as with
 275  *      PIO, load the mode number and then set MWDMA or UDMA flag.
 276  */
 277
 278 static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 279 {
 280         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 281         u32 addr1, addr2;
 282         u32 reg;
 283         u32 mode;
 284         u8 fast;
 285
 286         addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
 287         addr2 = 0x51 + 4 * ap->port_no;
 288
 289         /* Fast interrupt prediction disable, hold off interrupt disable */
 290         pci_read_config_byte(pdev, addr2, &fast);
 291         if (fast & 0x80) {
 292                 fast &= ~0x80;
 293                 pci_write_config_byte(pdev, addr2, fast);
 294         }
 295
 296         pci_read_config_dword(pdev, addr1, &reg);
 297         mode = hpt36x_find_mode(ap, adev->dma_mode);
 298         mode |= 0x8000000;      /* FIFO in MWDMA or UDMA */
 299         mode &= ~0xC0000000;    /* Leave config bits alone */
 300         reg &= 0xC0000000;      /* Strip timing bits */
 301         pci_write_config_dword(pdev, addr1, reg | mode);
 302 }
 303
 304 static struct scsi_host_template hpt36x_sht = {
 305         .module                 = THIS_MODULE,
 306         .name                   = DRV_NAME,
 307         .ioctl                  = ata_scsi_ioctl,
 308         .queuecommand           = ata_scsi_queuecmd,
 309         .can_queue              = ATA_DEF_QUEUE,
 310         .this_id                = ATA_SHT_THIS_ID,
 311         .sg_tablesize           = LIBATA_MAX_PRD,
 312         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 313         .emulated               = ATA_SHT_EMULATED,
 314         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 315         .proc_name              = DRV_NAME,
 316         .dma_boundary           = ATA_DMA_BOUNDARY,
 317         .slave_configure        = ata_scsi_slave_config,
 318         .slave_destroy          = ata_scsi_slave_destroy,
 319         .bios_param             = ata_std_bios_param,
 320 };
 321
 322 /*
 323  *      Configuration for HPT366/68
 324  */
 325
 326 static struct ata_port_operations hpt366_port_ops = {
 327         .set_piomode    = hpt366_set_piomode,
 328         .set_dmamode    = hpt366_set_dmamode,
 329         .mode_filter    = hpt366_filter,
 330
 331         .tf_load        = ata_tf_load,
 332         .tf_read        = ata_tf_read,
 333         .check_status   = ata_check_status,
 334         .exec_command   = ata_exec_command,
 335         .dev_select     = ata_std_dev_select,
 336
 337         .freeze         = ata_bmdma_freeze,
 338         .thaw           = ata_bmdma_thaw,
 339         .error_handler  = ata_bmdma_error_handler,
 340         .post_internal_cmd = ata_bmdma_post_internal_cmd,
 341         .cable_detect   = hpt36x_cable_detect,
 342
 343         .bmdma_setup    = ata_bmdma_setup,
 344         .bmdma_start    = ata_bmdma_start,
 345         .bmdma_stop     = ata_bmdma_stop,
 346         .bmdma_status   = ata_bmdma_status,
 347
 348         .qc_prep        = ata_qc_prep,
 349         .qc_issue       = ata_qc_issue_prot,
 350
 351         .data_xfer      = ata_data_xfer,
 352
 353         .irq_handler    = ata_interrupt,
 354         .irq_clear      = ata_bmdma_irq_clear,
 355         .irq_on         = ata_irq_on,
 356
 357         .port_start     = ata_sff_port_start,
 358 };
 359
 360 /**
 361  *      hpt36x_init_chipset     -       common chip setup
 362  *      @dev: PCI device
 363  *
 364  *      Perform the chip setup work that must be done at both init and
 365  *      resume time
 366  */
 367
 368 static void hpt36x_init_chipset(struct pci_dev *dev)
 369 {
 370         u8 drive_fast;
 371         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
 372         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
 373         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
 374         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
 375
 376         pci_read_config_byte(dev, 0x51, &drive_fast);
 377         if (drive_fast & 0x80)
 378                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
 379 }
 380
 381 /**
 382  *      hpt36x_init_one         -       Initialise an HPT366/368
 383  *      @dev: PCI device
 384  *      @id: Entry in match table
 385  *
 386  *      Initialise an HPT36x device. There are some interesting complications
 387  *      here. Firstly the chip may report 366 and be one of several variants.
 388  *      Secondly all the timings depend on the clock for the chip which we must
 389  *      detect and look up
 390  *
 391  *      This is the known chip mappings. It may be missing a couple of later
 392  *      releases.
 393  *
 394  *      Chip version            PCI             Rev     Notes
 395  *      HPT366                  4 (HPT366)      0       UDMA66
 396  *      HPT366                  4 (HPT366)      1       UDMA66
 397  *      HPT368                  4 (HPT366)      2       UDMA66
 398  *      HPT37x/30x              4 (HPT366)      3+      Other driver
 399  *
 400  */
 401
 402 static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 403 {
 404         static const struct ata_port_info info_hpt366 = {
 405                 .sht = &hpt36x_sht,
 406                 .flags = ATA_FLAG_SLAVE_POSS,
 407                 .pio_mask = 0x1f,
 408                 .mwdma_mask = 0x07,
 409                 .udma_mask = ATA_UDMA4,
 410                 .port_ops = &hpt366_port_ops
 411         };
 412         struct ata_port_info info = info_hpt366;
 413         const struct ata_port_info *ppi[] = { &info, NULL };
 414
 415         u32 class_rev;
 416         u32 reg1;
 417
 418         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 419         class_rev &= 0xFF;
 420
 421         /* May be a later chip in disguise. Check */
 422         /* Newer chips are not in the HPT36x driver. Ignore them */
 423         if (class_rev > 2)
 424                         return -ENODEV;
 425
 426         hpt36x_init_chipset(dev);
 427
 428         pci_read_config_dword(dev, 0x40,  &reg1);
 429
 430         /* PCI clocking determines the ATA timing values to use */
 431         /* info_hpt366 is safe against re-entry so we can scribble on it */
 432         switch((reg1 & 0x700) >> 8) {
 433                 case 5:
 434                         info.private_data = &hpt366_40;
 435                         break;
 436                 case 9:
 437                         info.private_data = &hpt366_25;
 438                         break;
 439                 default:
 440                         info.private_data = &hpt366_33;
 441                         break;
 442         }
 443         /* Now kick off ATA set up */
 444         return ata_pci_init_one(dev, ppi);
 445 }
 446
 447 #ifdef CONFIG_PM
 448 static int hpt36x_reinit_one(struct pci_dev *dev)
 449 {
 450         hpt36x_init_chipset(dev);
 451         return ata_pci_device_resume(dev);
 452 }
 453 #endif
 454
 455 static const struct pci_device_id hpt36x[] = {
 456         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
 457         { },
 458 };
 459
 460 static struct pci_driver hpt36x_pci_driver = {
 461         .name           = DRV_NAME,
 462         .id_table       = hpt36x,
 463         .probe          = hpt36x_init_one,
 464         .remove         = ata_pci_remove_one,
 465 #ifdef CONFIG_PM
 466         .suspend        = ata_pci_device_suspend,
 467         .resume         = hpt36x_reinit_one,
 468 #endif
 469 };
 470
 471 static int __init hpt36x_init(void)
 472 {
 473         return pci_register_driver(&hpt36x_pci_driver);
 474 }
 475
 476 static void __exit hpt36x_exit(void)
 477 {
 478         pci_unregister_driver(&hpt36x_pci_driver);
 479 }
 480
 481 MODULE_AUTHOR("Alan Cox");
 482 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
 483 MODULE_LICENSE("GPL");
 484 MODULE_DEVICE_TABLE(pci, hpt36x);
 485 MODULE_VERSION(DRV_VERSION);
 486
 487 module_init(hpt36x_init);
 488 module_exit(hpt36x_exit);