Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / arch / sh / kernel / cpu / sh3 / probe.c
blob769721af2707a5a294c365160879cc66c50ab3f2
1 /*
2 * arch/sh/kernel/cpu/sh3/probe.c
4 * CPU Subtype Probing for SH-3.
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2002 Paul Mundt
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
14 #include <linux/init.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
17 #include <asm/io.h>
19 int __uses_jump_to_uncached detect_cpu_and_cache_system(void)
21 unsigned long addr0, addr1, data0, data1, data2, data3;
23 jump_to_uncached();
25 * Check if the entry shadows or not.
26 * When shadowed, it's 128-entry system.
27 * Otherwise, it's 256-entry system.
29 addr0 = CACHE_OC_ADDRESS_ARRAY + (3 << 12);
30 addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
32 /* First, write back & invalidate */
33 data0 = ctrl_inl(addr0);
34 ctrl_outl(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
35 data1 = ctrl_inl(addr1);
36 ctrl_outl(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
38 /* Next, check if there's shadow or not */
39 data0 = ctrl_inl(addr0);
40 data0 ^= SH_CACHE_VALID;
41 ctrl_outl(data0, addr0);
42 data1 = ctrl_inl(addr1);
43 data2 = data1 ^ SH_CACHE_VALID;
44 ctrl_outl(data2, addr1);
45 data3 = ctrl_inl(addr0);
47 /* Lastly, invaliate them. */
48 ctrl_outl(data0&~SH_CACHE_VALID, addr0);
49 ctrl_outl(data2&~SH_CACHE_VALID, addr1);
51 back_to_cached();
53 boot_cpu_data.dcache.ways = 4;
54 boot_cpu_data.dcache.entry_shift = 4;
55 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
56 boot_cpu_data.dcache.flags = 0;
59 * 7709A/7729 has 16K cache (256-entry), while 7702 has only
60 * 2K(direct) 7702 is not supported (yet)
62 if (data0 == data1 && data2 == data3) { /* Shadow */
63 boot_cpu_data.dcache.way_incr = (1 << 11);
64 boot_cpu_data.dcache.entry_mask = 0x7f0;
65 boot_cpu_data.dcache.sets = 128;
66 boot_cpu_data.type = CPU_SH7708;
68 boot_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
69 } else { /* 7709A or 7729 */
70 boot_cpu_data.dcache.way_incr = (1 << 12);
71 boot_cpu_data.dcache.entry_mask = 0xff0;
72 boot_cpu_data.dcache.sets = 256;
73 boot_cpu_data.type = CPU_SH7729;
75 #if defined(CONFIG_CPU_SUBTYPE_SH7706)
76 boot_cpu_data.type = CPU_SH7706;
77 #endif
78 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
79 boot_cpu_data.type = CPU_SH7710;
80 #endif
81 #if defined(CONFIG_CPU_SUBTYPE_SH7712)
82 boot_cpu_data.type = CPU_SH7712;
83 #endif
84 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
85 boot_cpu_data.type = CPU_SH7720;
86 #endif
87 #if defined(CONFIG_CPU_SUBTYPE_SH7721)
88 boot_cpu_data.type = CPU_SH7721;
89 #endif
90 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
91 boot_cpu_data.type = CPU_SH7705;
93 #if defined(CONFIG_SH7705_CACHE_32KB)
94 boot_cpu_data.dcache.way_incr = (1 << 13);
95 boot_cpu_data.dcache.entry_mask = 0x1ff0;
96 boot_cpu_data.dcache.sets = 512;
97 <<<<<<< HEAD:arch/sh/kernel/cpu/sh3/probe.c
98 ctrl_outl(CCR_CACHE_32KB, CCR3);
99 =======
100 ctrl_outl(CCR_CACHE_32KB, CCR3_REG);
101 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/cpu/sh3/probe.c
102 #else
103 <<<<<<< HEAD:arch/sh/kernel/cpu/sh3/probe.c
104 ctrl_outl(CCR_CACHE_16KB, CCR3);
105 =======
106 ctrl_outl(CCR_CACHE_16KB, CCR3_REG);
107 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/cpu/sh3/probe.c
108 #endif
109 #endif
113 * SH-3 doesn't have separate caches
115 boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
116 boot_cpu_data.icache = boot_cpu_data.dcache;
118 return 0;