arch/sh/kernel/cpu/sh2a/clock-sh7203.c

   1 /*
   2  * arch/sh/kernel/cpu/sh2a/clock-sh7203.c
   3  *
   4  * SH7203 support for the clock framework
   5  *
   6  *  Copyright (C) 2007 Kieran Bingham (MPC-Data Ltd)
   7  *
   8  * Based on clock-sh7263.c
   9  *  Copyright (C) 2006  Yoshinori Sato
  10  *
  11  * Based on clock-sh4.c
  12  *  Copyright (C) 2005  Paul Mundt
  13  *
  14  * This file is subject to the terms and conditions of the GNU General Public
  15  * License.  See the file "COPYING" in the main directory of this archive
  16  * for more details.
  17  */
  18 #include <linux/init.h>
  19 #include <linux/kernel.h>
  20 #include <asm/clock.h>
  21 #include <asm/freq.h>
  22 #include <asm/io.h>
  23
  24 <<<<<<< HEAD:arch/sh/kernel/cpu/sh2a/clock-sh7203.c
  25 const static int pll1rate[]={8,12,16,0};
  26 const static int pfc_divisors[]={1,2,3,4,6,8,12};
  27 =======
  28 static const int pll1rate[]={8,12,16,0};
  29 static const int pfc_divisors[]={1,2,3,4,6,8,12};
  30 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/sh/kernel/cpu/sh2a/clock-sh7203.c
  31 #define ifc_divisors pfc_divisors
  32
  33 #if (CONFIG_SH_CLK_MD == 0)
  34 #define PLL2 (1)
  35 #elif (CONFIG_SH_CLK_MD == 1)
  36 #define PLL2 (2)
  37 #elif (CONFIG_SH_CLK_MD == 2)
  38 #define PLL2 (4)
  39 #elif (CONFIG_SH_CLK_MD == 3)
  40 #define PLL2 (4)
  41 #else
  42 #error "Illegal Clock Mode!"
  43 #endif
  44
  45 static void master_clk_init(struct clk *clk)
  46 {
  47         clk->rate *= pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0003] * PLL2 ;
  48 }
  49
  50 static struct clk_ops sh7203_master_clk_ops = {
  51         .init           = master_clk_init,
  52 };
  53
  54 static void module_clk_recalc(struct clk *clk)
  55 {
  56         int idx = (ctrl_inw(FREQCR) & 0x0007);
  57         clk->rate = clk->parent->rate / pfc_divisors[idx];
  58 }
  59
  60 static struct clk_ops sh7203_module_clk_ops = {
  61         .recalc         = module_clk_recalc,
  62 };
  63
  64 static void bus_clk_recalc(struct clk *clk)
  65 {
  66         int idx = (ctrl_inw(FREQCR) & 0x0007);
  67         clk->rate = clk->parent->rate / pfc_divisors[idx-2];
  68 }
  69
  70 static struct clk_ops sh7203_bus_clk_ops = {
  71         .recalc         = bus_clk_recalc,
  72 };
  73
  74 static void cpu_clk_recalc(struct clk *clk)
  75 {
  76         clk->rate = clk->parent->rate;
  77 }
  78
  79 static struct clk_ops sh7203_cpu_clk_ops = {
  80         .recalc         = cpu_clk_recalc,
  81 };
  82
  83 static struct clk_ops *sh7203_clk_ops[] = {
  84         &sh7203_master_clk_ops,
  85         &sh7203_module_clk_ops,
  86         &sh7203_bus_clk_ops,
  87         &sh7203_cpu_clk_ops,
  88 };
  89
  90 void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
  91 {
  92         if (idx < ARRAY_SIZE(sh7203_clk_ops))
  93                 *ops = sh7203_clk_ops[idx];
  94 }