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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / arch / blackfin / mach-common / ints-priority.c
blob93fb0694e0b4dd2229a213b1a72beabcbc9ecfbf
1 /*
2 * File: arch/blackfin/mach-common/ints-priority.c
3 * Based on:
4 * Author:
5 *
6 * Created: ?
7 * Description: Set up the interrupt priorities
8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2008 Analog Devices Inc.
17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/seq_file.h>
39 #include <linux/irq.h>
40 #ifdef CONFIG_KGDB
41 #include <linux/kgdb.h>
42 #endif
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
45 #include <asm/gpio.h>
46 #include <asm/irq_handler.h>
47
48 #ifdef BF537_FAMILY
49 # define BF537_GENERIC_ERROR_INT_DEMUX
50 #else
51 # undef BF537_GENERIC_ERROR_INT_DEMUX
52 #endif
53
54 /*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
61 /* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
66 */
67 unsigned long irq_flags = 0x1f;
68
69 /* The number of spurious interrupts */
70 atomic_t num_spurious;
71
72 #ifdef CONFIG_PM
73 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
74 #endif
75
76 struct ivgx {
77 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
78 /* irq number for request_irq, available in mach-bf533/irq.h */
79 =======
80 /* irq number for request_irq, available in mach-bf5xx/irq.h */
81 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
82 unsigned int irqno;
83 /* corresponding bit in the SIC_ISR register */
84 unsigned int isrflag;
85 } ivg_table[NR_PERI_INTS];
86
87 struct ivg_slice {
88 /* position of first irq in ivg_table for given ivg */
89 struct ivgx *ifirst;
90 struct ivgx *istop;
91 } ivg7_13[IVG13 - IVG7 + 1];
92
93 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
94 static void search_IAR(void);
95 =======
96 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
97
98 /*
99 * Search SIC_IAR and fill tables with the irqvalues
100 * and their positions in the SIC_ISR register.
101 */
102 static void __init search_IAR(void)
103 {
104 unsigned ivg, irq_pos = 0;
105 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
106 int irqn;
107
108 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
109
110 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
111 int iar_shift = (irqn & 7) * 4;
112 if (ivg == (0xf &
113 #ifndef CONFIG_BF52x
114 bfin_read32((unsigned long *)SIC_IAR0 +
115 (irqn >> 3)) >> iar_shift)) {
116 #else
117 bfin_read32((unsigned long *)SIC_IAR0 +
118 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
119 #endif
120 ivg_table[irq_pos].irqno = IVG7 + irqn;
121 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
122 ivg7_13[ivg].istop++;
123 irq_pos++;
124 }
125 }
126 }
127 }
128
129 /*
130 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
131 * This is for BF533 internal IRQs
132 =======
133 * This is for core internal IRQs
134 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
135 */
136
137 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
138 static void ack_noop(unsigned int irq)
139 =======
140 static void bfin_ack_noop(unsigned int irq)
141 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
142 {
143 /* Dummy function. */
144 }
145
146 static void bfin_core_mask_irq(unsigned int irq)
147 {
148 irq_flags &= ~(1 << irq);
149 if (!irqs_disabled())
150 local_irq_enable();
151 }
152
153 static void bfin_core_unmask_irq(unsigned int irq)
154 {
155 irq_flags |= 1 << irq;
156 /*
157 * If interrupts are enabled, IMASK must contain the same value
158 * as irq_flags. Make sure that invariant holds. If interrupts
159 * are currently disabled we need not do anything; one of the
160 * callers will take care of setting IMASK to the proper value
161 * when reenabling interrupts.
162 * local_irq_enable just does "STI irq_flags", so it's exactly
163 * what we need.
164 */
165 if (!irqs_disabled())
166 local_irq_enable();
167 return;
168 }
169
170 static void bfin_internal_mask_irq(unsigned int irq)
171 {
172 #ifdef CONFIG_BF53x
173 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
174 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
175 ~(1 << (irq - (IRQ_CORETMR + 1))));
176 =======
177 ~(1 << SIC_SYSIRQ(irq)));
178 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
179 #else
180 unsigned mask_bank, mask_bit;
181 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
182 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
183 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
184 =======
185 mask_bank = SIC_SYSIRQ(irq) / 32;
186 mask_bit = SIC_SYSIRQ(irq) % 32;
187 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
188 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
189 ~(1 << mask_bit));
190 #endif
191 SSYNC();
192 }
193
194 static void bfin_internal_unmask_irq(unsigned int irq)
195 {
196 #ifdef CONFIG_BF53x
197 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
198 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
199 (1 << (irq - (IRQ_CORETMR + 1))));
200 =======
201 (1 << SIC_SYSIRQ(irq)));
202 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
203 #else
204 unsigned mask_bank, mask_bit;
205 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
206 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
207 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
208 =======
209 mask_bank = SIC_SYSIRQ(irq) / 32;
210 mask_bit = SIC_SYSIRQ(irq) % 32;
211 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
212 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
213 (1 << mask_bit));
214 #endif
215 SSYNC();
216 }
217
218 #ifdef CONFIG_PM
219 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
220 {
221 unsigned bank, bit;
222 unsigned long flags;
223 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
224 bank = (irq - (IRQ_CORETMR + 1)) / 32;
225 bit = (irq - (IRQ_CORETMR + 1)) % 32;
226 =======
227 bank = SIC_SYSIRQ(irq) / 32;
228 bit = SIC_SYSIRQ(irq) % 32;
229 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
230
231 local_irq_save(flags);
232
233 if (state)
234 bfin_sic_iwr[bank] |= (1 << bit);
235 else
236 bfin_sic_iwr[bank] &= ~(1 << bit);
237
238 local_irq_restore(flags);
239
240 return 0;
241 }
242 #endif
243
244 static struct irq_chip bfin_core_irqchip = {
245 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
246 .ack = ack_noop,
247 =======
248 .ack = bfin_ack_noop,
249 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
250 .mask = bfin_core_mask_irq,
251 .unmask = bfin_core_unmask_irq,
252 };
253
254 static struct irq_chip bfin_internal_irqchip = {
255 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
256 .ack = ack_noop,
257 =======
258 .ack = bfin_ack_noop,
259 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
260 .mask = bfin_internal_mask_irq,
261 .unmask = bfin_internal_unmask_irq,
262 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
263 =======
264 .mask_ack = bfin_internal_mask_irq,
265 .disable = bfin_internal_mask_irq,
266 .enable = bfin_internal_unmask_irq,
267 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
268 #ifdef CONFIG_PM
269 .set_wake = bfin_internal_set_wake,
270 #endif
271 };
272
273 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
274 static int error_int_mask;
275
276 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
277 static void bfin_generic_error_ack_irq(unsigned int irq)
278 {
279
280 }
281
282 =======
283 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
284 static void bfin_generic_error_mask_irq(unsigned int irq)
285 {
286 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
287
288 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
289 if (!error_int_mask) {
290 local_irq_disable();
291 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
292 ~(1 << (IRQ_GENERIC_ERROR -
293 (IRQ_CORETMR + 1))));
294 SSYNC();
295 local_irq_enable();
296 }
297 =======
298 if (!error_int_mask)
299 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
300 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
301 }
302
303 static void bfin_generic_error_unmask_irq(unsigned int irq)
304 {
305 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
306 local_irq_disable();
307 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
308 (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
309 SSYNC();
310 local_irq_enable();
311
312 =======
313 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
314 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
315 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
316 }
317
318 static struct irq_chip bfin_generic_error_irqchip = {
319 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
320 .ack = bfin_generic_error_ack_irq,
321 =======
322 .ack = bfin_ack_noop,
323 .mask_ack = bfin_generic_error_mask_irq,
324 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
325 .mask = bfin_generic_error_mask_irq,
326 .unmask = bfin_generic_error_unmask_irq,
327 };
328
329 static void bfin_demux_error_irq(unsigned int int_err_irq,
330 struct irq_desc *inta_desc)
331 {
332 int irq = 0;
333
334 SSYNC();
335
336 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
337 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
338 irq = IRQ_MAC_ERROR;
339 else
340 #endif
341 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
342 irq = IRQ_SPORT0_ERROR;
343 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
344 irq = IRQ_SPORT1_ERROR;
345 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
346 irq = IRQ_PPI_ERROR;
347 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
348 irq = IRQ_CAN_ERROR;
349 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
350 irq = IRQ_SPI_ERROR;
351 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
352 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
353 irq = IRQ_UART0_ERROR;
354 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
355 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
356 irq = IRQ_UART1_ERROR;
357
358 if (irq) {
359 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
360 struct irq_desc *desc = irq_desc + irq;
361 desc->handle_irq(irq, desc);
362 } else {
363
364 switch (irq) {
365 case IRQ_PPI_ERROR:
366 bfin_write_PPI_STATUS(PPI_ERR_MASK);
367 break;
368 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
369 case IRQ_MAC_ERROR:
370 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
371 break;
372 #endif
373 case IRQ_SPORT0_ERROR:
374 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
375 break;
376
377 case IRQ_SPORT1_ERROR:
378 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
379 break;
380
381 case IRQ_CAN_ERROR:
382 bfin_write_CAN_GIS(CAN_ERR_MASK);
383 break;
384
385 case IRQ_SPI_ERROR:
386 bfin_write_SPI_STAT(SPI_ERR_MASK);
387 break;
388
389 default:
390 break;
391 }
392
393 pr_debug("IRQ %d:"
394 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
395 irq);
396 }
397 } else
398 printk(KERN_ERR
399 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
400 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
401 __FUNCTION__, __FILE__, __LINE__);
402
403 }
404 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
405
406 #if !defined(CONFIG_BF54x)
407
408 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
409 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
410
411
412 static void bfin_gpio_ack_irq(unsigned int irq)
413 {
414 u16 gpionr = irq - IRQ_PF0;
415
416 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
417 set_gpio_data(gpionr, 0);
418 SSYNC();
419 }
420 }
421
422 static void bfin_gpio_mask_ack_irq(unsigned int irq)
423 {
424 u16 gpionr = irq - IRQ_PF0;
425
426 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
427 set_gpio_data(gpionr, 0);
428 SSYNC();
429 }
430
431 set_gpio_maska(gpionr, 0);
432 SSYNC();
433 }
434
435 static void bfin_gpio_mask_irq(unsigned int irq)
436 {
437 set_gpio_maska(irq - IRQ_PF0, 0);
438 SSYNC();
439 }
440
441 static void bfin_gpio_unmask_irq(unsigned int irq)
442 {
443 set_gpio_maska(irq - IRQ_PF0, 1);
444 SSYNC();
445 }
446
447 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
448 {
449 unsigned int ret;
450 u16 gpionr = irq - IRQ_PF0;
451 char buf[8];
452
453 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
454 snprintf(buf, sizeof buf, "IRQ %d", irq);
455 ret = gpio_request(gpionr, buf);
456 if (ret)
457 return ret;
458 }
459
460 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
461 bfin_gpio_unmask_irq(irq);
462
463 return ret;
464 }
465
466 static void bfin_gpio_irq_shutdown(unsigned int irq)
467 {
468 bfin_gpio_mask_irq(irq);
469 gpio_free(irq - IRQ_PF0);
470 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
471 }
472
473 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
474 {
475
476 unsigned int ret;
477 char buf[8];
478 u16 gpionr = irq - IRQ_PF0;
479
480 if (type == IRQ_TYPE_PROBE) {
481 /* only probe unenabled GPIO interrupt lines */
482 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
483 return 0;
484 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
485 }
486
487 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
488 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
489 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
490 snprintf(buf, sizeof buf, "IRQ %d", irq);
491 ret = gpio_request(gpionr, buf);
492 if (ret)
493 return ret;
494 }
495
496 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
497 } else {
498 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
499 return 0;
500 }
501
502 set_gpio_inen(gpionr, 0);
503 set_gpio_dir(gpionr, 0);
504
505 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
506 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
507 set_gpio_both(gpionr, 1);
508 else
509 set_gpio_both(gpionr, 0);
510
511 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
512 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
513 else
514 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
515
516 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
517 set_gpio_edge(gpionr, 1);
518 set_gpio_inen(gpionr, 1);
519 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
520 set_gpio_data(gpionr, 0);
521
522 } else {
523 set_gpio_edge(gpionr, 0);
524 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
525 set_gpio_inen(gpionr, 1);
526 }
527
528 SSYNC();
529
530 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
531 set_irq_handler(irq, handle_edge_irq);
532 else
533 set_irq_handler(irq, handle_level_irq);
534
535 return 0;
536 }
537
538 #ifdef CONFIG_PM
539 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
540 {
541 unsigned gpio = irq_to_gpio(irq);
542
543 if (state)
544 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
545 else
546 gpio_pm_wakeup_free(gpio);
547
548 return 0;
549 }
550 #endif
551
552 static struct irq_chip bfin_gpio_irqchip = {
553 .ack = bfin_gpio_ack_irq,
554 .mask = bfin_gpio_mask_irq,
555 .mask_ack = bfin_gpio_mask_ack_irq,
556 .unmask = bfin_gpio_unmask_irq,
557 .set_type = bfin_gpio_irq_type,
558 .startup = bfin_gpio_irq_startup,
559 .shutdown = bfin_gpio_irq_shutdown,
560 #ifdef CONFIG_PM
561 .set_wake = bfin_gpio_set_wake,
562 #endif
563 };
564
565 static void bfin_demux_gpio_irq(unsigned int inta_irq,
566 struct irq_desc *desc)
567 {
568 unsigned int i, gpio, mask, irq, search = 0;
569
570 switch (inta_irq) {
571 #if defined(CONFIG_BF53x)
572 case IRQ_PROG_INTA:
573 irq = IRQ_PF0;
574 search = 1;
575 break;
576 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
577 case IRQ_MAC_RX:
578 irq = IRQ_PH0;
579 break;
580 # endif
581 #elif defined(CONFIG_BF52x)
582 case IRQ_PORTF_INTA:
583 irq = IRQ_PF0;
584 break;
585 case IRQ_PORTG_INTA:
586 irq = IRQ_PG0;
587 break;
588 case IRQ_PORTH_INTA:
589 irq = IRQ_PH0;
590 break;
591 #elif defined(CONFIG_BF561)
592 case IRQ_PROG0_INTA:
593 irq = IRQ_PF0;
594 break;
595 case IRQ_PROG1_INTA:
596 irq = IRQ_PF16;
597 break;
598 case IRQ_PROG2_INTA:
599 irq = IRQ_PF32;
600 break;
601 #endif
602 default:
603 BUG();
604 return;
605 }
606
607 if (search) {
608 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
609 irq += i;
610
611 mask = get_gpiop_data(i) &
612 (gpio_enabled[gpio_bank(i)] &
613 get_gpiop_maska(i));
614
615 while (mask) {
616 if (mask & 1) {
617 desc = irq_desc + irq;
618 desc->handle_irq(irq, desc);
619 }
620 irq++;
621 mask >>= 1;
622 }
623 }
624 } else {
625 gpio = irq_to_gpio(irq);
626 mask = get_gpiop_data(gpio) &
627 (gpio_enabled[gpio_bank(gpio)] &
628 get_gpiop_maska(gpio));
629
630 do {
631 if (mask & 1) {
632 desc = irq_desc + irq;
633 desc->handle_irq(irq, desc);
634 }
635 irq++;
636 mask >>= 1;
637 } while (mask);
638 }
639
640 }
641
642 #else /* CONFIG_BF54x */
643
644 #define NR_PINT_SYS_IRQS 4
645 #define NR_PINT_BITS 32
646 #define NR_PINTS 160
647 #define IRQ_NOT_AVAIL 0xFF
648
649 #define PINT_2_BANK(x) ((x) >> 5)
650 #define PINT_2_BIT(x) ((x) & 0x1F)
651 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
652
653 static unsigned char irq2pint_lut[NR_PINTS];
654 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
655
656 static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
657 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
658
659
660 struct pin_int_t {
661 unsigned int mask_set;
662 unsigned int mask_clear;
663 unsigned int request;
664 unsigned int assign;
665 unsigned int edge_set;
666 unsigned int edge_clear;
667 unsigned int invert_set;
668 unsigned int invert_clear;
669 unsigned int pinstate;
670 unsigned int latch;
671 };
672
673 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
674 (struct pin_int_t *)PINT0_MASK_SET,
675 (struct pin_int_t *)PINT1_MASK_SET,
676 (struct pin_int_t *)PINT2_MASK_SET,
677 (struct pin_int_t *)PINT3_MASK_SET,
678 };
679
680 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
681 unsigned short get_irq_base(u8 bank, u8 bmap)
682 =======
683 inline unsigned short get_irq_base(u8 bank, u8 bmap)
684 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
685 {
686
687 u16 irq_base;
688
689 if (bank < 2) { /*PA-PB */
690 irq_base = IRQ_PA0 + bmap * 16;
691 } else { /*PC-PJ */
692 irq_base = IRQ_PC0 + bmap * 16;
693 }
694
695 return irq_base;
696
697 }
698
699 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
700 void init_pint_lut(void)
701 {
702 u16 bank, bit, irq_base, bit_pos;
703 u32 pint_assign;
704 u8 bmap;
705
706 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
707
708 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
709
710 pint_assign = pint[bank]->assign;
711
712 for (bit = 0; bit < NR_PINT_BITS; bit++) {
713
714 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
715
716 irq_base = get_irq_base(bank, bmap);
717
718 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
719 bit_pos = bit + bank * NR_PINT_BITS;
720
721 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
722 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
723
724 }
725
726 }
727
728 }
729
730 static void bfin_gpio_ack_irq(unsigned int irq)
731 {
732 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
733 u32 pintbit = PINT_BIT(pint_val);
734 u8 bank = PINT_2_BANK(pint_val);
735
736 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
737 if (pint[bank]->invert_set & pintbit)
738 pint[bank]->invert_clear = pintbit;
739 else
740 pint[bank]->invert_set = pintbit;
741 }
742 pint[bank]->request = pintbit;
743
744 SSYNC();
745 }
746
747 static void bfin_gpio_mask_ack_irq(unsigned int irq)
748 {
749 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
750 u32 pintbit = PINT_BIT(pint_val);
751 u8 bank = PINT_2_BANK(pint_val);
752
753 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
754 if (pint[bank]->invert_set & pintbit)
755 pint[bank]->invert_clear = pintbit;
756 else
757 pint[bank]->invert_set = pintbit;
758 }
759
760 pint[bank]->request = pintbit;
761 pint[bank]->mask_clear = pintbit;
762 SSYNC();
763 }
764
765 static void bfin_gpio_mask_irq(unsigned int irq)
766 {
767 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
768
769 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
770 SSYNC();
771 }
772
773 static void bfin_gpio_unmask_irq(unsigned int irq)
774 {
775 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
776 u32 pintbit = PINT_BIT(pint_val);
777 u8 bank = PINT_2_BANK(pint_val);
778
779 pint[bank]->request = pintbit;
780 pint[bank]->mask_set = pintbit;
781 SSYNC();
782 }
783
784 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
785 {
786 unsigned int ret;
787 char buf[8];
788 u16 gpionr = irq_to_gpio(irq);
789 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
790
791 if (pint_val == IRQ_NOT_AVAIL) {
792 printk(KERN_ERR
793 "GPIO IRQ %d :Not in PINT Assign table "
794 "Reconfigure Interrupt to Port Assignemt\n", irq);
795 return -ENODEV;
796 }
797
798 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
799 snprintf(buf, sizeof buf, "IRQ %d", irq);
800 ret = gpio_request(gpionr, buf);
801 if (ret)
802 return ret;
803 }
804
805 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
806 bfin_gpio_unmask_irq(irq);
807
808 return ret;
809 }
810
811 static void bfin_gpio_irq_shutdown(unsigned int irq)
812 {
813 u16 gpionr = irq_to_gpio(irq);
814
815 bfin_gpio_mask_irq(irq);
816 gpio_free(gpionr);
817 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
818 }
819
820 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
821 {
822
823 unsigned int ret;
824 char buf[8];
825 u16 gpionr = irq_to_gpio(irq);
826 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
827 u32 pintbit = PINT_BIT(pint_val);
828 u8 bank = PINT_2_BANK(pint_val);
829
830 if (pint_val == IRQ_NOT_AVAIL)
831 return -ENODEV;
832
833 if (type == IRQ_TYPE_PROBE) {
834 /* only probe unenabled GPIO interrupt lines */
835 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
836 return 0;
837 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
838 }
839
840 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
841 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
842 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
843 snprintf(buf, sizeof buf, "IRQ %d", irq);
844 ret = gpio_request(gpionr, buf);
845 if (ret)
846 return ret;
847 }
848
849 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
850 } else {
851 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
852 return 0;
853 }
854
855 gpio_direction_input(gpionr);
856
857 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
858 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
859 else
860 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
861
862 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
863 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
864
865 gpio_both_edge_triggered[bank] |= pintbit;
866
867 if (gpio_get_value(gpionr))
868 pint[bank]->invert_set = pintbit;
869 else
870 pint[bank]->invert_clear = pintbit;
871 } else {
872 gpio_both_edge_triggered[bank] &= ~pintbit;
873 }
874
875 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
876 pint[bank]->edge_set = pintbit;
877 set_irq_handler(irq, handle_edge_irq);
878 } else {
879 pint[bank]->edge_clear = pintbit;
880 set_irq_handler(irq, handle_level_irq);
881 }
882
883 SSYNC();
884
885 return 0;
886 }
887
888 #ifdef CONFIG_PM
889 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
890 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
891
892 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
893 {
894 u32 pint_irq;
895 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
896 u32 bank = PINT_2_BANK(pint_val);
897 u32 pintbit = PINT_BIT(pint_val);
898
899 switch (bank) {
900 case 0:
901 pint_irq = IRQ_PINT0;
902 break;
903 case 2:
904 pint_irq = IRQ_PINT2;
905 break;
906 case 3:
907 pint_irq = IRQ_PINT3;
908 break;
909 case 1:
910 pint_irq = IRQ_PINT1;
911 break;
912 default:
913 return -EINVAL;
914 }
915
916 bfin_internal_set_wake(pint_irq, state);
917
918 if (state)
919 pint_wakeup_masks[bank] |= pintbit;
920 else
921 pint_wakeup_masks[bank] &= ~pintbit;
922
923 return 0;
924 }
925
926 u32 bfin_pm_setup(void)
927 {
928 u32 val, i;
929
930 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
931 val = pint[i]->mask_clear;
932 pint_saved_masks[i] = val;
933 if (val ^ pint_wakeup_masks[i]) {
934 pint[i]->mask_clear = val;
935 pint[i]->mask_set = pint_wakeup_masks[i];
936 }
937 }
938
939 return 0;
940 }
941
942 void bfin_pm_restore(void)
943 {
944 u32 i, val;
945
946 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
947 val = pint_saved_masks[i];
948 if (val ^ pint_wakeup_masks[i]) {
949 pint[i]->mask_clear = pint[i]->mask_clear;
950 pint[i]->mask_set = val;
951 }
952 }
953 }
954 #endif
955
956 static struct irq_chip bfin_gpio_irqchip = {
957 .ack = bfin_gpio_ack_irq,
958 .mask = bfin_gpio_mask_irq,
959 .mask_ack = bfin_gpio_mask_ack_irq,
960 .unmask = bfin_gpio_unmask_irq,
961 .set_type = bfin_gpio_irq_type,
962 .startup = bfin_gpio_irq_startup,
963 .shutdown = bfin_gpio_irq_shutdown,
964 #ifdef CONFIG_PM
965 .set_wake = bfin_gpio_set_wake,
966 #endif
967 };
968
969 static void bfin_demux_gpio_irq(unsigned int inta_irq,
970 struct irq_desc *desc)
971 {
972 u8 bank, pint_val;
973 u32 request, irq;
974
975 switch (inta_irq) {
976 case IRQ_PINT0:
977 bank = 0;
978 break;
979 case IRQ_PINT2:
980 bank = 2;
981 break;
982 case IRQ_PINT3:
983 bank = 3;
984 break;
985 case IRQ_PINT1:
986 bank = 1;
987 break;
988 default:
989 return;
990 }
991
992 pint_val = bank * NR_PINT_BITS;
993
994 request = pint[bank]->request;
995
996 while (request) {
997 if (request & 1) {
998 irq = pint2irq_lut[pint_val] + SYS_IRQS;
999 desc = irq_desc + irq;
1000 desc->handle_irq(irq, desc);
1001 }
1002 pint_val++;
1003 request >>= 1;
1004 }
1005
1006 }
1007 #endif
1008
1009 void __init init_exception_vectors(void)
1010 {
1011 SSYNC();
1012
1013 /* cannot program in software:
1014 * evt0 - emulation (jtag)
1015 * evt1 - reset
1016 */
1017 bfin_write_EVT2(evt_nmi);
1018 bfin_write_EVT3(trap);
1019 bfin_write_EVT5(evt_ivhw);
1020 bfin_write_EVT6(evt_timer);
1021 bfin_write_EVT7(evt_evt7);
1022 bfin_write_EVT8(evt_evt8);
1023 bfin_write_EVT9(evt_evt9);
1024 bfin_write_EVT10(evt_evt10);
1025 bfin_write_EVT11(evt_evt11);
1026 bfin_write_EVT12(evt_evt12);
1027 bfin_write_EVT13(evt_evt13);
1028 bfin_write_EVT14(evt14_softirq);
1029 bfin_write_EVT15(evt_system_call);
1030 CSYNC();
1031 }
1032
1033 /*
1034 * This function should be called during kernel startup to initialize
1035 * the BFin IRQ handling routines.
1036 */
1037 int __init init_arch_irq(void)
1038 {
1039 int irq;
1040 unsigned long ilat = 0;
1041 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
1042 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1043 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1044 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1045 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1046 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
1047 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
1048 =======
1049 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1050 # ifdef CONFIG_BF54x
1051 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1052 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1053 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
1054 =======
1055 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1056 # endif
1057 #else
1058 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1059 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1060 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
1061 =======
1062 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1063 #endif
1064 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1065 SSYNC();
1066 =======
1067 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1068
1069 local_irq_disable();
1070
1071 init_exception_buff();
1072
1073 #ifdef CONFIG_BF54x
1074 # ifdef CONFIG_PINTx_REASSIGN
1075 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1076 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1077 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1078 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1079 # endif
1080 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1081 init_pint_lut();
1082 #endif
1083
1084 for (irq = 0; irq <= SYS_IRQS; irq++) {
1085 if (irq <= IRQ_CORETMR)
1086 set_irq_chip(irq, &bfin_core_irqchip);
1087 else
1088 set_irq_chip(irq, &bfin_internal_irqchip);
1089 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1090 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1091 if (irq != IRQ_GENERIC_ERROR) {
1092 #endif
1093 =======
1094 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1095
1096 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1097 switch (irq) {
1098 =======
1099 switch (irq) {
1100 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1101 #if defined(CONFIG_BF53x)
1102 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1103 case IRQ_PROG_INTA:
1104 set_irq_chained_handler(irq,
1105 bfin_demux_gpio_irq);
1106 break;
1107 =======
1108 case IRQ_PROG_INTA:
1109 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1110 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1111 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1112 case IRQ_MAC_RX:
1113 set_irq_chained_handler(irq,
1114 bfin_demux_gpio_irq);
1115 break;
1116 =======
1117 case IRQ_MAC_RX:
1118 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1119 # endif
1120 #elif defined(CONFIG_BF54x)
1121 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1122 case IRQ_PINT0:
1123 set_irq_chained_handler(irq,
1124 bfin_demux_gpio_irq);
1125 break;
1126 case IRQ_PINT1:
1127 set_irq_chained_handler(irq,
1128 bfin_demux_gpio_irq);
1129 break;
1130 case IRQ_PINT2:
1131 set_irq_chained_handler(irq,
1132 bfin_demux_gpio_irq);
1133 break;
1134 case IRQ_PINT3:
1135 set_irq_chained_handler(irq,
1136 bfin_demux_gpio_irq);
1137 break;
1138 =======
1139 case IRQ_PINT0:
1140 case IRQ_PINT1:
1141 case IRQ_PINT2:
1142 case IRQ_PINT3:
1143 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1144 #elif defined(CONFIG_BF52x)
1145 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1146 case IRQ_PORTF_INTA:
1147 set_irq_chained_handler(irq,
1148 bfin_demux_gpio_irq);
1149 break;
1150 case IRQ_PORTG_INTA:
1151 set_irq_chained_handler(irq,
1152 bfin_demux_gpio_irq);
1153 break;
1154 case IRQ_PORTH_INTA:
1155 set_irq_chained_handler(irq,
1156 bfin_demux_gpio_irq);
1157 break;
1158 =======
1159 case IRQ_PORTF_INTA:
1160 case IRQ_PORTG_INTA:
1161 case IRQ_PORTH_INTA:
1162 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1163 #elif defined(CONFIG_BF561)
1164 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1165 case IRQ_PROG0_INTA:
1166 set_irq_chained_handler(irq,
1167 bfin_demux_gpio_irq);
1168 break;
1169 case IRQ_PROG1_INTA:
1170 set_irq_chained_handler(irq,
1171 bfin_demux_gpio_irq);
1172 break;
1173 case IRQ_PROG2_INTA:
1174 set_irq_chained_handler(irq,
1175 bfin_demux_gpio_irq);
1176 break;
1177 =======
1178 case IRQ_PROG0_INTA:
1179 case IRQ_PROG1_INTA:
1180 case IRQ_PROG2_INTA:
1181 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1182 #endif
1183 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1184 default:
1185 set_irq_handler(irq, handle_simple_irq);
1186 break;
1187 }
1188
1189 =======
1190 set_irq_chained_handler(irq,
1191 bfin_demux_gpio_irq);
1192 break;
1193 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1194 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1195 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1196 } else {
1197 =======
1198 case IRQ_GENERIC_ERROR:
1199 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1200 set_irq_handler(irq, bfin_demux_error_irq);
1201 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1202 }
1203 =======
1204
1205 break;
1206 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1207 #endif
1208 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1209 =======
1210 default:
1211 set_irq_handler(irq, handle_simple_irq);
1212 break;
1213 }
1214 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1215 }
1216 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1217 =======
1218
1219 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1220 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1221 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1222 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) {
1223 set_irq_chip(irq, &bfin_generic_error_irqchip);
1224 set_irq_handler(irq, handle_level_irq);
1225 }
1226 =======
1227 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1228 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1229 handle_level_irq);
1230 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1231 #endif
1232
1233 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1234 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) {
1235 =======
1236 /* if configured as edge, then will be changed to do_edge_IRQ */
1237 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1238 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1239 handle_level_irq);
1240 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1241
1242 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1243 set_irq_chip(irq, &bfin_gpio_irqchip);
1244 /* if configured as edge, then will be changed to do_edge_IRQ */
1245 set_irq_handler(irq, handle_level_irq);
1246 }
1247 =======
1248 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1249
1250 bfin_write_IMASK(0);
1251 CSYNC();
1252 ilat = bfin_read_ILAT();
1253 CSYNC();
1254 bfin_write_ILAT(ilat);
1255 CSYNC();
1256
1257 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1258 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1259 * local_irq_enable()
1260 */
1261 program_IAR();
1262 /* Therefore it's better to setup IARs before interrupts enabled */
1263 search_IAR();
1264
1265 /* Enable interrupts IVG7-15 */
1266 irq_flags = irq_flags | IMASK_IVG15 |
1267 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1268 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1269
1270 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1271 =======
1272 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1273 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
1274 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
1275 # ifdef CONFIG_BF54x
1276 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
1277 # endif
1278 #else
1279 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
1280 #endif
1281
1282 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1283 return 0;
1284 }
1285
1286 #ifdef CONFIG_DO_IRQ_L1
1287 __attribute__((l1_text))
1288 #endif
1289 void do_irq(int vec, struct pt_regs *fp)
1290 {
1291 if (vec == EVT_IVTMR_P) {
1292 vec = IRQ_CORETMR;
1293 } else {
1294 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1295 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1296 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1297 unsigned long sic_status[3];
1298
1299 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1300 SSYNC();
1301 =======
1302 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1303 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1304 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1305 #ifdef CONFIG_BF54x
1306 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1307 #endif
1308 for (;; ivg++) {
1309 if (ivg >= ivg_stop) {
1310 atomic_inc(&num_spurious);
1311 return;
1312 }
1313 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1314 break;
1315 }
1316 #else
1317 unsigned long sic_status;
1318 <<<<<<< HEAD:arch/blackfin/mach-common/ints-priority.c
1319 SSYNC();
1320 =======
1321
1322 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/blackfin/mach-common/ints-priority.c
1323 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1324
1325 for (;; ivg++) {
1326 if (ivg >= ivg_stop) {
1327 atomic_inc(&num_spurious);
1328 return;
1329 } else if (sic_status & ivg->isrflag)
1330 break;
1331 }
1332 #endif
1333 vec = ivg->irqno;
1334 }
1335 asm_do_IRQ(vec, fp);
1336
1337 #ifdef CONFIG_KGDB
1338 kgdb_process_breakpoint();
1339 #endif
1340 }
WRT350N Kernel Patches