2 * interlocked functions
4 * Copyright 1996 Alexandre Julliard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #include "wine/port.h"
28 __ASM_GLOBAL_FUNC(interlocked_cmpxchg
,
29 "movl 12(%esp),%eax\n\t"
30 "movl 8(%esp),%ecx\n\t"
31 "movl 4(%esp),%edx\n\t"
32 "lock; cmpxchgl %ecx,(%edx)\n\t"
34 __ASM_GLOBAL_FUNC(interlocked_cmpxchg_ptr
,
35 "movl 12(%esp),%eax\n\t"
36 "movl 8(%esp),%ecx\n\t"
37 "movl 4(%esp),%edx\n\t"
38 "lock; cmpxchgl %ecx,(%edx)\n\t"
40 __ASM_GLOBAL_FUNC(interlocked_xchg
,
41 "movl 8(%esp),%eax\n\t"
42 "movl 4(%esp),%edx\n\t"
43 "lock; xchgl %eax,(%edx)\n\t"
45 __ASM_GLOBAL_FUNC(interlocked_xchg_ptr
,
46 "movl 8(%esp),%eax\n\t"
47 "movl 4(%esp),%edx\n\t"
48 "lock; xchgl %eax,(%edx)\n\t"
50 __ASM_GLOBAL_FUNC(interlocked_xchg_add
,
51 "movl 8(%esp),%eax\n\t"
52 "movl 4(%esp),%edx\n\t"
53 "lock; xaddl %eax,(%edx)\n\t"
56 #elif defined(_MSC_VER)
58 __declspec(naked
) long interlocked_cmpxchg( long *dest
, long xchg
, long compare
)
60 __asm mov eax
, 12[esp
];
61 __asm mov ecx
, 8[esp
];
62 __asm mov edx
, 4[esp
];
63 __asm lock cmpxchg
[edx
], ecx
;
67 __declspec(naked
) void *interlocked_cmpxchg_ptr( void **dest
, void *xchg
, void *compare
)
69 __asm mov eax
, 12[esp
];
70 __asm mov ecx
, 8[esp
];
71 __asm mov edx
, 4[esp
];
72 __asm lock cmpxchg
[edx
], ecx
;
76 __declspec(naked
) long interlocked_xchg( long *dest
, long val
)
78 __asm mov eax
, 8[esp
];
79 __asm mov edx
, 4[esp
];
80 __asm lock xchg
[edx
], eax
;
84 __declspec(naked
) void *interlocked_xchg_ptr( void **dest
, void *val
)
86 __asm mov eax
, 8[esp
];
87 __asm mov edx
, 4[esp
];
88 __asm lock xchg
[edx
], eax
;
92 __declspec(naked
) long interlocked_xchg_add( long *dest
, long incr
)
94 __asm mov eax
, 8[esp
];
95 __asm mov edx
, 4[esp
];
96 __asm lock xadd
[edx
], eax
;
101 # error You must implement the interlocked* functions for your compiler
104 #elif defined(__x86_64__)
108 __ASM_GLOBAL_FUNC(interlocked_cmpxchg
,
110 "lock cmpxchgl %esi,(%rdi)\n\t"
112 __ASM_GLOBAL_FUNC(interlocked_cmpxchg_ptr
,
114 "lock cmpxchgq %rsi,(%rdi)\n\t"
116 __ASM_GLOBAL_FUNC(interlocked_xchg
,
118 "lock xchgl %eax, (%rdi)\n\t"
120 __ASM_GLOBAL_FUNC(interlocked_xchg_ptr
,
122 "lock xchgq %rax,(%rdi)\n\t"
124 __ASM_GLOBAL_FUNC(interlocked_xchg_add
,
126 "lock xaddl %eax, (%rdi)\n\t"
130 # error You must implement the interlocked* functions for your compiler
133 #elif defined(__powerpc__)
134 void* interlocked_cmpxchg_ptr( void **dest
, void* xchg
, void* compare
)
138 __asm__
__volatile__(
146 : "=&r"(ret
), "=&r"(scratch
)
147 : "r"(dest
), "r"(xchg
), "r"(compare
)
152 long interlocked_cmpxchg( long *dest
, long xchg
, long compare
)
156 __asm__
__volatile__(
164 : "=&r"(ret
), "=&r"(scratch
)
165 : "r"(dest
), "r"(xchg
), "r"(compare
)
166 : "cr0","memory","r0");
170 long interlocked_xchg_add( long *dest
, long incr
)
174 __asm__
__volatile__(
175 "0: lwarx %0, %3, %1\n"
177 " stwcx. %0, %3, %1\n"
181 : "r"(dest
), "r"(incr
), "r"(zero
)
182 : "cr0", "memory", "r0"
187 long interlocked_xchg( long* dest
, long val
)
190 __asm__
__volatile__(
196 : "r"(dest
), "r"(val
)
197 : "cr0","memory","r0");
201 void* interlocked_xchg_ptr( void** dest
, void* val
)
204 __asm__
__volatile__(
210 : "r"(dest
), "r"(val
)
211 : "cr0","memory","r0");
215 #elif defined(__sparc__) && defined(__sun__)
218 * As the earlier Sparc processors lack necessary atomic instructions,
219 * I'm simply falling back to the library-provided _lwp_mutex routines
220 * to ensure mutual exclusion in a way appropriate for the current
223 * FIXME: If we have the compare-and-swap instruction (Sparc v9 and above)
224 * we could use this to speed up the Interlocked operations ...
227 static lwp_mutex_t interlocked_mutex
= DEFAULTMUTEX
;
229 long interlocked_cmpxchg( long *dest
, long xchg
, long compare
)
231 _lwp_mutex_lock( &interlocked_mutex
);
232 if (*dest
== compare
) *dest
= xchg
;
233 else compare
= *dest
;
234 _lwp_mutex_unlock( &interlocked_mutex
);
238 void *interlocked_cmpxchg_ptr( void **dest
, void *xchg
, void *compare
)
240 _lwp_mutex_lock( &interlocked_mutex
);
241 if (*dest
== compare
) *dest
= xchg
;
242 else compare
= *dest
;
243 _lwp_mutex_unlock( &interlocked_mutex
);
247 long interlocked_xchg( long *dest
, long val
)
250 _lwp_mutex_lock( &interlocked_mutex
);
253 _lwp_mutex_unlock( &interlocked_mutex
);
257 void *interlocked_xchg_ptr( void **dest
, void *val
)
260 _lwp_mutex_lock( &interlocked_mutex
);
263 _lwp_mutex_unlock( &interlocked_mutex
);
267 long interlocked_xchg_add( long *dest
, long incr
)
270 _lwp_mutex_lock( &interlocked_mutex
);
273 _lwp_mutex_unlock( &interlocked_mutex
);
277 #elif defined(__ALPHA__) && defined(__GNUC__)
279 __ASM_GLOBAL_FUNC(interlocked_cmpxchg
,
281 "ldl_l $0,0($16)\n\t"
282 "cmpeq $0,$18,$1\n\t"
283 "beq $1,L1cmpxchg\n\t"
285 "stl_c $0,0($16)\n\t"
286 "beq $0,L0cmpxchg\n\t"
291 __ASM_GLOBAL_FUNC(interlocked_cmpxchg_ptr
,
293 "ldq_l $0,0($16)\n\t"
294 "cmpeq $0,$18,$1\n\t"
295 "beq $1,L1cmpxchg_ptr\n\t"
297 "stq_c $0,0($16)\n\t"
298 "beq $0,L0cmpxchg_ptr\n\t"
303 __ASM_GLOBAL_FUNC(interlocked_xchg
,
305 "ldl_l $0,0($16)\n\t"
307 "stl_c $1,0($16)\n\t"
311 __ASM_GLOBAL_FUNC(interlocked_xchg_ptr
,
313 "ldq_l $0,0($16)\n\t"
315 "stq_c $1,0($16)\n\t"
316 "beq $1,L0xchg_ptr\n\t"
319 __ASM_GLOBAL_FUNC(interlocked_xchg_add
,
321 "ldl_l $0,0($16)\n\t"
323 "stl_c $1,0($16)\n\t"
324 "beq $1,L0xchg_add\n\t"
328 # error You must implement the interlocked* functions for your CPU