programs/winedbg/be_x86_64.c

   1 /*
   2  * Debugger x86_64 specific functions
   3  *
   4  * Copyright 2004 Vincent Béron
   5  * Copyright 2009 Eric Pouech
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
  20  */
  21
  22 #include "debugger.h"
  23 #include "wine/debug.h"
  24
  25 WINE_DEFAULT_DEBUG_CHANNEL(winedbg);
  26
  27 #if defined(__x86_64__)
  28
  29 #define STEP_FLAG 0x00000100 /* single step flag */
  30
  31 static unsigned be_x86_64_get_addr(HANDLE hThread, const CONTEXT* ctx,
  32                                  enum be_cpu_addr bca, ADDRESS64* addr)
  33 {
  34     addr->Mode = AddrModeFlat;
  35     switch (bca)
  36     {
  37     case be_cpu_addr_pc:
  38         addr->Segment = ctx->SegCs;
  39         addr->Offset = ctx->Rip;
  40         return TRUE;
  41     case be_cpu_addr_stack:
  42         addr->Segment = ctx->SegSs;
  43         addr->Offset = ctx->Rsp;
  44         return TRUE;
  45     case be_cpu_addr_frame:
  46         addr->Segment = ctx->SegSs;
  47         addr->Offset = ctx->Rbp;
  48         return TRUE;
  49     default:
  50         addr->Mode = -1;
  51         return FALSE;
  52     }
  53 }
  54
  55 static unsigned be_x86_64_get_register_info(int regno, enum be_cpu_addr* kind)
  56 {
  57     /* this is true when running in 32bit mode... and wrong in 64 :-/ */
  58     switch (regno)
  59     {
  60     case CV_AMD64_RIP: *kind = be_cpu_addr_pc; return TRUE;
  61     case CV_AMD64_EBP: *kind = be_cpu_addr_frame; return TRUE;
  62     case CV_AMD64_ESP: *kind = be_cpu_addr_stack; return TRUE;
  63     }
  64     return FALSE;
  65 }
  66
  67 static void be_x86_64_single_step(CONTEXT* ctx, unsigned enable)
  68 {
  69     if (enable) ctx->EFlags |= STEP_FLAG;
  70     else ctx->EFlags &= ~STEP_FLAG;
  71 }
  72
  73 static void be_x86_64_print_context(HANDLE hThread, const CONTEXT* ctx,
  74                                     int all_regs)
  75 {
  76     static const char flags[] = "aVR-N--ODITSZ-A-P-C";
  77     char buf[33];
  78     int i;
  79
  80     strcpy(buf, flags);
  81     for (i = 0; buf[i]; i++)
  82         if (buf[i] != '-' && !(ctx->EFlags & (1 << (sizeof(flags) - 2 - i))))
  83             buf[i] = ' ';
  84
  85     dbg_printf("Register dump:\n");
  86     dbg_printf(" rip:%016lx rsp:%016lx rbp:%016lx eflags:%08x (%s)\n",
  87                ctx->Rip, ctx->Rsp, ctx->Rbp, ctx->EFlags, buf);
  88     dbg_printf(" rax:%016lx rbx:%016lx rcx:%016lx rdx:%016lx\n",
  89                ctx->Rax, ctx->Rbx, ctx->Rcx, ctx->Rdx);
  90     dbg_printf(" rsi:%016lx rdi:%016lx  r8:%016lx  r9:%016lx r10:%016lx\n",
  91                ctx->Rsi, ctx->Rdi, ctx->R8, ctx->R9, ctx->R10 );
  92     dbg_printf(" r11:%016lx r12:%016lx r13:%016lx r14:%016lx r15:%016lx\n",
  93                ctx->R11, ctx->R12, ctx->R13, ctx->R14, ctx->R15 );
  94
  95     if (all_regs) dbg_printf( "Floating point x86_64 dump not implemented\n" );
  96 }
  97
  98 static void be_x86_64_print_segment_info(HANDLE hThread, const CONTEXT* ctx)
  99 {
 100 }
 101
 102 static struct dbg_internal_var be_x86_64_ctx[] =
 103 {
 104     {CV_AMD64_AL,       "AL",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax),     dbg_itype_unsigned_char_int},
 105     {CV_AMD64_BL,       "BL",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx),     dbg_itype_unsigned_char_int},
 106     {CV_AMD64_CL,       "CL",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx),     dbg_itype_unsigned_char_int},
 107     {CV_AMD64_DL,       "DL",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx),     dbg_itype_unsigned_char_int},
 108     {CV_AMD64_AH,       "AH",           (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rax)+1), dbg_itype_unsigned_char_int},
 109     {CV_AMD64_BH,       "BH",           (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rbx)+1), dbg_itype_unsigned_char_int},
 110     {CV_AMD64_CH,       "CH",           (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rcx)+1), dbg_itype_unsigned_char_int},
 111     {CV_AMD64_DH,       "DH",           (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rdx)+1), dbg_itype_unsigned_char_int},
 112     {CV_AMD64_AX,       "AX",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax),     dbg_itype_unsigned_short_int},
 113     {CV_AMD64_BX,       "BX",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx),     dbg_itype_unsigned_short_int},
 114     {CV_AMD64_CX,       "CX",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx),     dbg_itype_unsigned_short_int},
 115     {CV_AMD64_DX,       "DX",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx),     dbg_itype_unsigned_short_int},
 116     {CV_AMD64_SP,       "SP",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp),     dbg_itype_unsigned_short_int},
 117     {CV_AMD64_BP,       "BP",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp),     dbg_itype_unsigned_short_int},
 118     {CV_AMD64_SI,       "SI",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi),     dbg_itype_unsigned_short_int},
 119     {CV_AMD64_DI,       "DI",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi),     dbg_itype_unsigned_short_int},
 120     {CV_AMD64_EAX,      "EAX",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax),     dbg_itype_unsigned_int},
 121     {CV_AMD64_EBX,      "EBX",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx),     dbg_itype_unsigned_int},
 122     {CV_AMD64_ECX,      "ECX",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx),     dbg_itype_unsigned_int},
 123     {CV_AMD64_EDX,      "EDX",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx),     dbg_itype_unsigned_int},
 124     {CV_AMD64_ESP,      "ESP",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp),     dbg_itype_unsigned_int},
 125     {CV_AMD64_EBP,      "EBP",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp),     dbg_itype_unsigned_int},
 126     {CV_AMD64_ESI,      "ESI",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi),     dbg_itype_unsigned_int},
 127     {CV_AMD64_EDI,      "EDI",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi),     dbg_itype_unsigned_int},
 128     {CV_AMD64_ES,       "ES",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegEs),   dbg_itype_unsigned_short_int},
 129     {CV_AMD64_CS,       "CS",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegCs),   dbg_itype_unsigned_short_int},
 130     {CV_AMD64_SS,       "SS",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegSs),   dbg_itype_unsigned_short_int},
 131     {CV_AMD64_DS,       "DS",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegDs),   dbg_itype_unsigned_short_int},
 132     {CV_AMD64_FS,       "FS",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegFs),   dbg_itype_unsigned_short_int},
 133     {CV_AMD64_GS,       "GS",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegGs),   dbg_itype_unsigned_short_int},
 134     {CV_AMD64_FLAGS,    "FLAGS",        (DWORD_PTR*)FIELD_OFFSET(CONTEXT, EFlags),  dbg_itype_unsigned_short_int},
 135     {CV_AMD64_EFLAGS,   "EFLAGS",       (DWORD_PTR*)FIELD_OFFSET(CONTEXT, EFlags),  dbg_itype_unsigned_int},
 136     {CV_AMD64_RIP,      "RIP",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rip),     dbg_itype_unsigned_int},
 137     {CV_AMD64_RAX,      "RAX",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax),     dbg_itype_unsigned_long_int},
 138     {CV_AMD64_RBX,      "RBX",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx),     dbg_itype_unsigned_long_int},
 139     {CV_AMD64_RCX,      "RCX",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx),     dbg_itype_unsigned_long_int},
 140     {CV_AMD64_RDX,      "RDX",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx),     dbg_itype_unsigned_long_int},
 141     {CV_AMD64_RSP,      "RSP",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp),     dbg_itype_unsigned_long_int},
 142     {CV_AMD64_RBP,      "RBP",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp),     dbg_itype_unsigned_long_int},
 143     {CV_AMD64_RSI,      "RSI",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi),     dbg_itype_unsigned_long_int},
 144     {CV_AMD64_RDI,      "RDI",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi),     dbg_itype_unsigned_long_int},
 145     {CV_AMD64_R8,       "R8",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R8),      dbg_itype_unsigned_long_int},
 146     {CV_AMD64_R9,       "R9",           (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R9),      dbg_itype_unsigned_long_int},
 147     {CV_AMD64_R10,      "R10",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R10),     dbg_itype_unsigned_long_int},
 148     {CV_AMD64_R11,      "R11",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R11),     dbg_itype_unsigned_long_int},
 149     {CV_AMD64_R12,      "R12",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R12),     dbg_itype_unsigned_long_int},
 150     {CV_AMD64_R13,      "R13",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R13),     dbg_itype_unsigned_long_int},
 151     {CV_AMD64_R14,      "R14",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R14),     dbg_itype_unsigned_long_int},
 152     {CV_AMD64_R15,      "R15",          (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R15),     dbg_itype_unsigned_long_int},
 153     {0,                 NULL,           0,                                      dbg_itype_none}
 154 };
 155
 156 static const struct dbg_internal_var* be_x86_64_init_registers(CONTEXT* ctx)
 157 {
 158     struct dbg_internal_var*    div;
 159
 160     for (div = be_x86_64_ctx; div->name; div++)
 161         div->pval = (DWORD_PTR*)((char*)ctx + (DWORD_PTR)div->pval);
 162     return be_x86_64_ctx;
 163 }
 164
 165 static unsigned be_x86_64_is_step_over_insn(const void* insn)
 166 {
 167     dbg_printf("not done step_over_insn\n");
 168     return FALSE;
 169 }
 170
 171 static unsigned be_x86_64_is_function_return(const void* insn)
 172 {
 173     dbg_printf("not done is_function_return\n");
 174     return FALSE;
 175 }
 176
 177 static unsigned be_x86_64_is_break_insn(const void* insn)
 178 {
 179     dbg_printf("not done is_break_insn\n");
 180     return FALSE;
 181 }
 182
 183 static unsigned be_x86_64_is_func_call(const void* insn, ADDRESS64* callee)
 184 {
 185     dbg_printf("not done is_func_call\n");
 186     return FALSE;
 187 }
 188
 189 static void be_x86_64_disasm_one_insn(ADDRESS64* addr, int display)
 190 {
 191     dbg_printf("Disasm NIY\n");
 192 }
 193
 194 #define DR7_CONTROL_SHIFT       16
 195 #define DR7_CONTROL_SIZE        4
 196
 197 #define DR7_RW_EXECUTE          (0x0)
 198 #define DR7_RW_WRITE            (0x1)
 199 #define DR7_RW_READ             (0x3)
 200
 201 #define DR7_LEN_1               (0x0)
 202 #define DR7_LEN_2               (0x4)
 203 #define DR7_LEN_4               (0xC)
 204
 205 #define DR7_LOCAL_ENABLE_SHIFT  0
 206 #define DR7_GLOBAL_ENABLE_SHIFT 1
 207 #define DR7_ENABLE_SIZE         2
 208
 209 #define DR7_LOCAL_ENABLE_MASK   (0x55)
 210 #define DR7_GLOBAL_ENABLE_MASK  (0xAA)
 211
 212 #define DR7_CONTROL_RESERVED    (0xFC00)
 213 #define DR7_LOCAL_SLOWDOWN      (0x100)
 214 #define DR7_GLOBAL_SLOWDOWN     (0x200)
 215
 216 #define DR7_ENABLE_MASK(dr)     (1<<(DR7_LOCAL_ENABLE_SHIFT+DR7_ENABLE_SIZE*(dr)))
 217 #define IS_DR7_SET(ctrl,dr)     ((ctrl)&DR7_ENABLE_MASK(dr))
 218
 219 static inline int be_x86_64_get_unused_DR(CONTEXT* ctx, DWORD64** r)
 220 {
 221     if (!IS_DR7_SET(ctx->Dr7, 0))
 222     {
 223         *r = &ctx->Dr0;
 224         return 0;
 225     }
 226     if (!IS_DR7_SET(ctx->Dr7, 1))
 227     {
 228         *r = &ctx->Dr1;
 229         return 1;
 230     }
 231     if (!IS_DR7_SET(ctx->Dr7, 2))
 232     {
 233         *r = &ctx->Dr2;
 234         return 2;
 235     }
 236     if (!IS_DR7_SET(ctx->Dr7, 3))
 237     {
 238         *r = &ctx->Dr3;
 239         return 3;
 240     }
 241     dbg_printf("All hardware registers have been used\n");
 242
 243     return -1;
 244 }
 245
 246 static unsigned be_x86_64_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
 247                                        CONTEXT* ctx, enum be_xpoint_type type,
 248                                        void* addr, unsigned long* val, unsigned size)
 249 {
 250     unsigned char       ch;
 251     SIZE_T              sz;
 252     DWORD64            *pr;
 253     int                 reg;
 254     unsigned long       bits;
 255
 256     switch (type)
 257     {
 258     case be_xpoint_break:
 259         if (size != 0) return 0;
 260         if (!pio->read(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
 261         *val = ch;
 262         ch = 0xcc;
 263         if (!pio->write(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
 264         break;
 265     case be_xpoint_watch_exec:
 266         bits = DR7_RW_EXECUTE;
 267         goto hw_bp;
 268     case be_xpoint_watch_read:
 269         bits = DR7_RW_READ;
 270         goto hw_bp;
 271     case be_xpoint_watch_write:
 272         bits = DR7_RW_WRITE;
 273     hw_bp:
 274         if ((reg = be_x86_64_get_unused_DR(ctx, &pr)) == -1) return 0;
 275         *pr = (DWORD64)addr;
 276         if (type != be_xpoint_watch_exec) switch (size)
 277         {
 278         case 4: bits |= DR7_LEN_4; break;
 279         case 2: bits |= DR7_LEN_2; break;
 280         case 1: bits |= DR7_LEN_1; break;
 281         default: return 0;
 282         }
 283         *val = reg;
 284         /* clear old values */
 285         ctx->Dr7 &= ~(0x0F << (DR7_CONTROL_SHIFT + DR7_CONTROL_SIZE * reg));
 286         /* set the correct ones */
 287         ctx->Dr7 |= bits << (DR7_CONTROL_SHIFT + DR7_CONTROL_SIZE * reg);
 288         ctx->Dr7 |= DR7_ENABLE_MASK(reg) | DR7_LOCAL_SLOWDOWN;
 289         break;
 290     default:
 291         dbg_printf("Unknown bp type %c\n", type);
 292         return 0;
 293     }
 294     return 1;
 295 }
 296
 297 static unsigned be_x86_64_remove_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
 298                                        CONTEXT* ctx, enum be_xpoint_type type,
 299                                        void* addr, unsigned long val, unsigned size)
 300 {
 301     SIZE_T              sz;
 302     unsigned char       ch;
 303
 304     switch (type)
 305     {
 306     case be_xpoint_break:
 307         if (size != 0) return 0;
 308         if (!pio->read(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
 309         if (ch != (unsigned char)0xCC)
 310             WINE_FIXME("Cannot get back %02x instead of 0xCC at %08lx\n",
 311                        ch, (unsigned long)addr);
 312         ch = (unsigned char)val;
 313         if (!pio->write(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
 314         break;
 315     case be_xpoint_watch_exec:
 316     case be_xpoint_watch_read:
 317     case be_xpoint_watch_write:
 318         /* simply disable the entry */
 319         ctx->Dr7 &= ~DR7_ENABLE_MASK(val);
 320         break;
 321     default:
 322         dbg_printf("Unknown bp type %c\n", type);
 323         return 0;
 324     }
 325     return 1;
 326 }
 327
 328 static unsigned be_x86_64_is_watchpoint_set(const CONTEXT* ctx, unsigned idx)
 329 {
 330     return ctx->Dr6 & (1 << idx);
 331 }
 332
 333 static void be_x86_64_clear_watchpoint(CONTEXT* ctx, unsigned idx)
 334 {
 335     ctx->Dr6 &= ~(1 << idx);
 336 }
 337
 338 static int be_x86_64_adjust_pc_for_break(CONTEXT* ctx, BOOL way)
 339 {
 340     if (way)
 341     {
 342         ctx->Rip--;
 343         return -1;
 344     }
 345     ctx->Rip++;
 346     return 1;
 347 }
 348
 349 static int be_x86_64_fetch_integer(const struct dbg_lvalue* lvalue, unsigned size,
 350                                    unsigned ext_sign, LONGLONG* ret)
 351 {
 352     if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16)
 353         return FALSE;
 354
 355     memset(ret, 0, sizeof(*ret)); /* clear unread bytes */
 356     /* FIXME: this assumes that debuggee and debugger use the same
 357      * integral representation
 358      */
 359     if (!memory_read_value(lvalue, size, ret)) return FALSE;
 360
 361     /* propagate sign information */
 362     if (ext_sign && size < 16 && (*ret >> (size * 8 - 1)) != 0)
 363     {
 364         ULONGLONG neg = -1;
 365         *ret |= neg << (size * 8);
 366     }
 367     return TRUE;
 368 }
 369
 370 static int be_x86_64_fetch_float(const struct dbg_lvalue* lvalue, unsigned size,
 371                                 long double* ret)
 372 {
 373     dbg_printf("not done fetch_float\n");
 374     return FALSE;
 375 }
 376
 377 struct backend_cpu be_x86_64 =
 378 {
 379     IMAGE_FILE_MACHINE_AMD64,
 380     be_cpu_linearize,
 381     be_cpu_build_addr,
 382     be_x86_64_get_addr,
 383     be_x86_64_get_register_info,
 384     be_x86_64_single_step,
 385     be_x86_64_print_context,
 386     be_x86_64_print_segment_info,
 387     be_x86_64_init_registers,
 388     be_x86_64_is_step_over_insn,
 389     be_x86_64_is_function_return,
 390     be_x86_64_is_break_insn,
 391     be_x86_64_is_func_call,
 392     be_x86_64_disasm_one_insn,
 393     be_x86_64_insert_Xpoint,
 394     be_x86_64_remove_Xpoint,
 395     be_x86_64_is_watchpoint_set,
 396     be_x86_64_clear_watchpoint,
 397     be_x86_64_adjust_pc_for_break,
 398     be_x86_64_fetch_integer,
 399     be_x86_64_fetch_float,
 400 };
 401 #endif