?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
comctl32/tests: Prevent a possible nullptr dereference.
[wine.git] / programs / winedbg / be_x86_64.c
blob280cdec2f3f6b147deab5943455b4f0d6f7f3bb7
1 /*
2 * Debugger x86_64 specific functions
3 *
4 * Copyright 2004 Vincent Béron
5 * Copyright 2009 Eric Pouech
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
20 */
21
22 #define NONAMELESSSTRUCT
23 #define NONAMELESSUNION
24
25 #include "debugger.h"
26 #include "wine/debug.h"
27
28 #if defined(__x86_64__)
29
30 WINE_DEFAULT_DEBUG_CHANNEL(winedbg);
31
32 #define STEP_FLAG 0x00000100 /* single step flag */
33
34 static BOOL be_x86_64_get_addr(HANDLE hThread, const CONTEXT* ctx,
35 enum be_cpu_addr bca, ADDRESS64* addr)
36 {
37 addr->Mode = AddrModeFlat;
38 switch (bca)
39 {
40 case be_cpu_addr_pc:
41 addr->Segment = ctx->SegCs;
42 addr->Offset = ctx->Rip;
43 return TRUE;
44 case be_cpu_addr_stack:
45 addr->Segment = ctx->SegSs;
46 addr->Offset = ctx->Rsp;
47 return TRUE;
48 case be_cpu_addr_frame:
49 addr->Segment = ctx->SegSs;
50 addr->Offset = ctx->Rbp;
51 return TRUE;
52 default:
53 addr->Mode = -1;
54 return FALSE;
55 }
56 }
57
58 static BOOL be_x86_64_get_register_info(int regno, enum be_cpu_addr* kind)
59 {
60 /* this is true when running in 32bit mode... and wrong in 64 :-/ */
61 switch (regno)
62 {
63 case CV_AMD64_RIP: *kind = be_cpu_addr_pc; return TRUE;
64 case CV_AMD64_EBP: *kind = be_cpu_addr_frame; return TRUE;
65 case CV_AMD64_ESP: *kind = be_cpu_addr_stack; return TRUE;
66 }
67 return FALSE;
68 }
69
70 static void be_x86_64_single_step(CONTEXT* ctx, BOOL enable)
71 {
72 if (enable) ctx->EFlags |= STEP_FLAG;
73 else ctx->EFlags &= ~STEP_FLAG;
74 }
75
76 static inline long double m128a_to_longdouble(const M128A m)
77 {
78 /* gcc uses the same IEEE-754 representation as M128A for long double
79 * but 16 byte aligned (hence only the first 10 bytes out of the 16 are used)
80 */
81 return *(long double*)&m;
82 }
83
84 static void be_x86_64_print_context(HANDLE hThread, const CONTEXT* ctx,
85 int all_regs)
86 {
87 static const char mxcsr_flags[16][4] = { "IE", "DE", "ZE", "OE", "UE", "PE", "DAZ", "IM",
88 "DM", "ZM", "OM", "UM", "PM", "R-", "R+", "FZ" };
89 static const char flags[] = "aVR-N--ODITSZ-A-P-C";
90 char buf[33];
91 int i;
92
93 strcpy(buf, flags);
94 for (i = 0; buf[i]; i++)
95 if (buf[i] != '-' && !(ctx->EFlags & (1 << (sizeof(flags) - 2 - i))))
96 buf[i] = ' ';
97
98 dbg_printf("Register dump:\n");
99 dbg_printf(" rip:%016lx rsp:%016lx rbp:%016lx eflags:%08x (%s)\n",
100 ctx->Rip, ctx->Rsp, ctx->Rbp, ctx->EFlags, buf);
101 dbg_printf(" rax:%016lx rbx:%016lx rcx:%016lx rdx:%016lx\n",
102 ctx->Rax, ctx->Rbx, ctx->Rcx, ctx->Rdx);
103 dbg_printf(" rsi:%016lx rdi:%016lx r8:%016lx r9:%016lx r10:%016lx\n",
104 ctx->Rsi, ctx->Rdi, ctx->R8, ctx->R9, ctx->R10 );
105 dbg_printf(" r11:%016lx r12:%016lx r13:%016lx r14:%016lx r15:%016lx\n",
106 ctx->R11, ctx->R12, ctx->R13, ctx->R14, ctx->R15 );
107
108 if (!all_regs) return;
109
110 dbg_printf(" cs:%04x ds:%04x es:%04x fs:%04x gs:%04x ss:%04x\n",
111 ctx->SegCs, ctx->SegDs, ctx->SegEs, ctx->SegFs, ctx->SegGs, ctx->SegSs );
112
113 dbg_printf("Debug:\n");
114 dbg_printf(" dr0:%016lx dr1:%016lx dr2:%016lx dr3:%016lx\n",
115 ctx->Dr0, ctx->Dr1, ctx->Dr2, ctx->Dr3 );
116 dbg_printf(" dr6:%016lx dr7:%016lx\n", ctx->Dr6, ctx->Dr7 );
117
118 dbg_printf("Floating point:\n");
119 dbg_printf(" flcw:%04x ", LOWORD(ctx->u.FltSave.ControlWord));
120 dbg_printf(" fltw:%04x ", LOWORD(ctx->u.FltSave.TagWord));
121 dbg_printf(" flsw:%04x", LOWORD(ctx->u.FltSave.StatusWord));
122
123 dbg_printf("(cc:%d%d%d%d", (ctx->u.FltSave.StatusWord & 0x00004000) >> 14,
124 (ctx->u.FltSave.StatusWord & 0x00000400) >> 10,
125 (ctx->u.FltSave.StatusWord & 0x00000200) >> 9,
126 (ctx->u.FltSave.StatusWord & 0x00000100) >> 8);
127
128 dbg_printf(" top:%01x", (unsigned int) (ctx->u.FltSave.StatusWord & 0x00003800) >> 11);
129
130 if (ctx->u.FltSave.StatusWord & 0x00000001) /* Invalid Fl OP */
131 {
132 if (ctx->u.FltSave.StatusWord & 0x00000040) /* Stack Fault */
133 {
134 if (ctx->u.FltSave.StatusWord & 0x00000200) /* C1 says Overflow */
135 dbg_printf(" #IE(Stack Overflow)");
136 else
137 dbg_printf(" #IE(Stack Underflow)"); /* Underflow */
138 }
139 else dbg_printf(" #IE(Arithmetic error)"); /* Invalid Fl OP */
140 }
141 if (ctx->u.FltSave.StatusWord & 0x00000002) dbg_printf(" #DE"); /* Denormalised OP */
142 if (ctx->u.FltSave.StatusWord & 0x00000004) dbg_printf(" #ZE"); /* Zero Divide */
143 if (ctx->u.FltSave.StatusWord & 0x00000008) dbg_printf(" #OE"); /* Overflow */
144 if (ctx->u.FltSave.StatusWord & 0x00000010) dbg_printf(" #UE"); /* Underflow */
145 if (ctx->u.FltSave.StatusWord & 0x00000020) dbg_printf(" #PE"); /* Precision error */
146 if (ctx->u.FltSave.StatusWord & 0x00000040)
147 if (!(ctx->u.FltSave.StatusWord & 0x00000001))
148 dbg_printf(" #SE"); /* Stack Fault (don't think this can occur) */
149 if (ctx->u.FltSave.StatusWord & 0x00000080) dbg_printf(" #ES"); /* Error Summary */
150 if (ctx->u.FltSave.StatusWord & 0x00008000) dbg_printf(" #FB"); /* FPU Busy */
151 dbg_printf(")\n");
152 dbg_printf(" flerr:%04x:%08x fldata:%04x:%08x\n",
153 ctx->u.FltSave.ErrorSelector, ctx->u.FltSave.ErrorOffset,
154 ctx->u.FltSave.DataSelector, ctx->u.FltSave.DataOffset );
155
156 for (i = 0; i < 4; i++)
157 {
158 dbg_printf(" st%u:%-16Lg ", i, m128a_to_longdouble(ctx->u.FltSave.FloatRegisters[i]));
159 }
160 dbg_printf("\n");
161 for (i = 4; i < 8; i++)
162 {
163 dbg_printf(" st%u:%-16Lg ", i, m128a_to_longdouble(ctx->u.FltSave.FloatRegisters[i]));
164 }
165 dbg_printf("\n");
166
167 dbg_printf(" mxcsr: %04x (", ctx->u.FltSave.MxCsr );
168 for (i = 0; i < 16; i++)
169 if (ctx->u.FltSave.MxCsr & (1 << i)) dbg_printf( " %s", mxcsr_flags[i] );
170 dbg_printf(" )\n");
171
172 for (i = 0; i < 16; i++)
173 {
174 dbg_printf( " %sxmm%u: uint=%016lx%016lx", (i > 9) ? "" : " ", i,
175 ctx->u.FltSave.XmmRegisters[i].High, ctx->u.FltSave.XmmRegisters[i].Low );
176 dbg_printf( " double={%g; %g}", *(double *)&ctx->u.FltSave.XmmRegisters[i].Low,
177 *(double *)&ctx->u.FltSave.XmmRegisters[i].High );
178 dbg_printf( " float={%g; %g; %g; %g}\n",
179 (double)*((float *)&ctx->u.FltSave.XmmRegisters[i] + 0),
180 (double)*((float *)&ctx->u.FltSave.XmmRegisters[i] + 1),
181 (double)*((float *)&ctx->u.FltSave.XmmRegisters[i] + 2),
182 (double)*((float *)&ctx->u.FltSave.XmmRegisters[i] + 3) );
183 }
184 }
185
186 static void be_x86_64_print_segment_info(HANDLE hThread, const CONTEXT* ctx)
187 {
188 }
189
190 static struct dbg_internal_var be_x86_64_ctx[] =
191 {
192 {CV_AMD64_AL, "AL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_char_int},
193 {CV_AMD64_BL, "BL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_char_int},
194 {CV_AMD64_CL, "CL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_char_int},
195 {CV_AMD64_DL, "DL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_char_int},
196 {CV_AMD64_AH, "AH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rax)+1), dbg_itype_unsigned_char_int},
197 {CV_AMD64_BH, "BH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rbx)+1), dbg_itype_unsigned_char_int},
198 {CV_AMD64_CH, "CH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rcx)+1), dbg_itype_unsigned_char_int},
199 {CV_AMD64_DH, "DH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rdx)+1), dbg_itype_unsigned_char_int},
200 {CV_AMD64_AX, "AX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_short_int},
201 {CV_AMD64_BX, "BX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_short_int},
202 {CV_AMD64_CX, "CX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_short_int},
203 {CV_AMD64_DX, "DX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_short_int},
204 {CV_AMD64_SP, "SP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_short_int},
205 {CV_AMD64_BP, "BP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_short_int},
206 {CV_AMD64_SI, "SI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_short_int},
207 {CV_AMD64_DI, "DI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_short_int},
208 {CV_AMD64_EAX, "EAX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_int},
209 {CV_AMD64_EBX, "EBX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_int},
210 {CV_AMD64_ECX, "ECX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_int},
211 {CV_AMD64_EDX, "EDX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_int},
212 {CV_AMD64_ESP, "ESP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_int},
213 {CV_AMD64_EBP, "EBP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_int},
214 {CV_AMD64_ESI, "ESI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_int},
215 {CV_AMD64_EDI, "EDI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_int},
216 {CV_AMD64_ES, "ES", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegEs), dbg_itype_unsigned_short_int},
217 {CV_AMD64_CS, "CS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegCs), dbg_itype_unsigned_short_int},
218 {CV_AMD64_SS, "SS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegSs), dbg_itype_unsigned_short_int},
219 {CV_AMD64_DS, "DS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegDs), dbg_itype_unsigned_short_int},
220 {CV_AMD64_FS, "FS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegFs), dbg_itype_unsigned_short_int},
221 {CV_AMD64_GS, "GS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegGs), dbg_itype_unsigned_short_int},
222 {CV_AMD64_FLAGS, "FLAGS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, EFlags), dbg_itype_unsigned_short_int},
223 {CV_AMD64_EFLAGS, "EFLAGS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, EFlags), dbg_itype_unsigned_int},
224 {CV_AMD64_RIP, "RIP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rip), dbg_itype_unsigned_long_int},
225 {CV_AMD64_RAX, "RAX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_long_int},
226 {CV_AMD64_RBX, "RBX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_long_int},
227 {CV_AMD64_RCX, "RCX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_long_int},
228 {CV_AMD64_RDX, "RDX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_long_int},
229 {CV_AMD64_RSP, "RSP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_long_int},
230 {CV_AMD64_RBP, "RBP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_long_int},
231 {CV_AMD64_RSI, "RSI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_long_int},
232 {CV_AMD64_RDI, "RDI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_long_int},
233 {CV_AMD64_R8, "R8", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R8), dbg_itype_unsigned_long_int},
234 {CV_AMD64_R9, "R9", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R9), dbg_itype_unsigned_long_int},
235 {CV_AMD64_R10, "R10", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R10), dbg_itype_unsigned_long_int},
236 {CV_AMD64_R11, "R11", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R11), dbg_itype_unsigned_long_int},
237 {CV_AMD64_R12, "R12", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R12), dbg_itype_unsigned_long_int},
238 {CV_AMD64_R13, "R13", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R13), dbg_itype_unsigned_long_int},
239 {CV_AMD64_R14, "R14", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R14), dbg_itype_unsigned_long_int},
240 {CV_AMD64_R15, "R15", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R15), dbg_itype_unsigned_long_int},
241 {CV_AMD64_ST0, "ST0", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[0]), dbg_itype_long_real},
242 {CV_AMD64_ST0+1, "ST1", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[1]), dbg_itype_long_real},
243 {CV_AMD64_ST0+2, "ST2", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[2]), dbg_itype_long_real},
244 {CV_AMD64_ST0+3, "ST3", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[3]), dbg_itype_long_real},
245 {CV_AMD64_ST0+4, "ST4", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[4]), dbg_itype_long_real},
246 {CV_AMD64_ST0+5, "ST5", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[5]), dbg_itype_long_real},
247 {CV_AMD64_ST0+6, "ST6", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[6]), dbg_itype_long_real},
248 {CV_AMD64_ST0+7, "ST7", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.FltSave.FloatRegisters[7]), dbg_itype_long_real},
249 {CV_AMD64_XMM0, "XMM0", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm0), dbg_itype_m128a},
250 {CV_AMD64_XMM0+1, "XMM1", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm1), dbg_itype_m128a},
251 {CV_AMD64_XMM0+2, "XMM2", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm2), dbg_itype_m128a},
252 {CV_AMD64_XMM0+3, "XMM3", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm3), dbg_itype_m128a},
253 {CV_AMD64_XMM0+4, "XMM4", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm4), dbg_itype_m128a},
254 {CV_AMD64_XMM0+5, "XMM5", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm5), dbg_itype_m128a},
255 {CV_AMD64_XMM0+6, "XMM6", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm6), dbg_itype_m128a},
256 {CV_AMD64_XMM0+7, "XMM7", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm7), dbg_itype_m128a},
257 {CV_AMD64_XMM8, "XMM8", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm8), dbg_itype_m128a},
258 {CV_AMD64_XMM8+1, "XMM9", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm9), dbg_itype_m128a},
259 {CV_AMD64_XMM8+2, "XMM10", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm10), dbg_itype_m128a},
260 {CV_AMD64_XMM8+3, "XMM11", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm11), dbg_itype_m128a},
261 {CV_AMD64_XMM8+4, "XMM12", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm12), dbg_itype_m128a},
262 {CV_AMD64_XMM8+5, "XMM13", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm13), dbg_itype_m128a},
263 {CV_AMD64_XMM8+6, "XMM14", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm14), dbg_itype_m128a},
264 {CV_AMD64_XMM8+7, "XMM15", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, u.s.Xmm15), dbg_itype_m128a},
265 {0, NULL, 0, dbg_itype_none}
266 };
267
268 #define f_mod(b) ((b)>>6)
269 #define f_reg(b) (((b)>>3)&0x7)
270 #define f_rm(b) ((b)&0x7)
271
272 static BOOL be_x86_64_is_step_over_insn(const void* insn)
273 {
274 BYTE ch;
275
276 for (;;)
277 {
278 if (!dbg_read_memory(insn, &ch, sizeof(ch))) return FALSE;
279
280 switch (ch)
281 {
282 /* Skip all prefixes */
283 case 0x2e: /* cs: */
284 case 0x36: /* ss: */
285 case 0x3e: /* ds: */
286 case 0x26: /* es: */
287 case 0x64: /* fs: */
288 case 0x65: /* gs: */
289 case 0x66: /* opcode size prefix */
290 case 0x67: /* addr size prefix */
291 case 0xf0: /* lock */
292 case 0xf2: /* repne */
293 case 0xf3: /* repe */
294 insn = (const char*)insn + 1;
295 continue;
296
297 /* Handle call instructions */
298 case 0xcd: /* int <intno> */
299 case 0xe8: /* call <offset> */
300 case 0x9a: /* lcall <seg>:<off> */
301 return TRUE;
302
303 case 0xff: /* call <regmodrm> */
304 if (!dbg_read_memory((const char*)insn + 1, &ch, sizeof(ch)))
305 return FALSE;
306 return (((ch & 0x38) == 0x10) || ((ch & 0x38) == 0x18));
307
308 /* Handle string instructions */
309 case 0x6c: /* insb */
310 case 0x6d: /* insw */
311 case 0x6e: /* outsb */
312 case 0x6f: /* outsw */
313 case 0xa4: /* movsb */
314 case 0xa5: /* movsw */
315 case 0xa6: /* cmpsb */
316 case 0xa7: /* cmpsw */
317 case 0xaa: /* stosb */
318 case 0xab: /* stosw */
319 case 0xac: /* lodsb */
320 case 0xad: /* lodsw */
321 case 0xae: /* scasb */
322 case 0xaf: /* scasw */
323 return TRUE;
324
325 default:
326 return FALSE;
327 }
328 }
329 }
330
331 static BOOL be_x86_64_is_function_return(const void* insn)
332 {
333 BYTE c;
334
335 /* sigh... amd64 for prefetch optimization requires 'rep ret' in some cases */
336 if (!dbg_read_memory(insn, &c, sizeof(c))) return FALSE;
337 if (c == 0xF3) /* REP */
338 {
339 insn = (const char*)insn + 1;
340 if (!dbg_read_memory(insn, &c, sizeof(c))) return FALSE;
341 }
342 return c == 0xC2 /* ret */ || c == 0xC3 /* ret NN */;
343 }
344
345 static BOOL be_x86_64_is_break_insn(const void* insn)
346 {
347 BYTE c;
348 return dbg_read_memory(insn, &c, sizeof(c)) && c == 0xCC;
349 }
350
351 static BOOL fetch_value(const char* addr, unsigned sz, int* value)
352 {
353 char value8;
354 short value16;
355
356 switch (sz)
357 {
358 case 8:
359 if (!dbg_read_memory(addr, &value8, sizeof(value8))) return FALSE;
360 *value = value8;
361 break;
362 case 16:
363 if (!dbg_read_memory(addr, &value16, sizeof(value16))) return FALSE;
364 *value = value16;
365 case 32:
366 if (!dbg_read_memory(addr, value, sizeof(*value))) return FALSE;
367 break;
368 default: return FALSE;
369 }
370 return TRUE;
371 }
372
373 static BOOL be_x86_64_is_func_call(const void* insn, ADDRESS64* callee)
374 {
375 BYTE ch;
376 LONG delta;
377 unsigned op_size = 32, rex = 0;
378 DWORD64 dst;
379
380 /* we assume 64bit mode all over the place */
381 for (;;)
382 {
383 if (!dbg_read_memory(insn, &ch, sizeof(ch))) return FALSE;
384 if (ch == 0x66) op_size = 16;
385 else if (ch == 0x67) WINE_FIXME("prefix not supported %x\n", ch);
386 else if (ch >= 0x40 && ch <= 0x4f) rex = ch & 0xf;
387 else break;
388 insn = (const char*)insn + 1;
389 } while (0);
390
391 /* that's the only mode we support anyway */
392 callee->Mode = AddrModeFlat;
393 callee->Segment = dbg_context.SegCs;
394
395 switch (ch)
396 {
397 case 0xe8: /* relative near call */
398 assert(op_size == 32);
399 if (!fetch_value((const char*)insn + 1, sizeof(delta), &delta))
400 return FALSE;
401 callee->Offset = (DWORD_PTR)insn + 1 + 4 + delta;
402 return TRUE;
403
404 case 0xff:
405 if (!dbg_read_memory((const char*)insn + 1, &ch, sizeof(ch)))
406 return FALSE;
407 WINE_TRACE("Got 0xFF %x (&C7=%x) with rex=%x\n", ch, ch & 0xC7, rex);
408 /* keep only the CALL and LCALL insn:s */
409 switch (f_reg(ch))
410 {
411 case 0x02:
412 break;
413 default: return FALSE;
414 }
415 if (rex == 0) switch (ch & 0xC7) /* keep Mod R/M only (skip reg) */
416 {
417 case 0x04:
418 case 0x44:
419 case 0x84:
420 WINE_FIXME("Unsupported yet call insn (0xFF 0x%02x) (SIB bytes) at %p\n", ch, insn);
421 return FALSE;
422 case 0x05: /* addr32 */
423 if (f_reg(ch) == 0x2)
424 {
425 /* rip-relative to next insn */
426 if (!dbg_read_memory((const char*)insn + 2, &delta, sizeof(delta)) ||
427 !dbg_read_memory((const char*)insn + 6 + delta, &dst, sizeof(dst)))
428 return FALSE;
429
430 callee->Offset = dst;
431 return TRUE;
432 }
433 WINE_FIXME("Unsupported yet call insn (0xFF 0x%02x) at %p\n", ch, insn);
434 return FALSE;
435 default:
436 switch (f_rm(ch))
437 {
438 case 0x00: dst = dbg_context.Rax; break;
439 case 0x01: dst = dbg_context.Rcx; break;
440 case 0x02: dst = dbg_context.Rdx; break;
441 case 0x03: dst = dbg_context.Rbx; break;
442 case 0x04: dst = dbg_context.Rsp; break;
443 case 0x05: dst = dbg_context.Rbp; break;
444 case 0x06: dst = dbg_context.Rsi; break;
445 case 0x07: dst = dbg_context.Rdi; break;
446 }
447 if (f_mod(ch) != 0x03)
448 WINE_FIXME("Unsupported yet call insn (0xFF 0x%02x) at %p\n", ch, insn);
449 else
450 {
451 callee->Offset = dst;
452 }
453 break;
454 }
455 else
456 WINE_FIXME("Unsupported yet call insn (rex=0x%02x 0xFF 0x%02x) at %p\n", rex, ch, insn);
457 return FALSE;
458
459 default:
460 return FALSE;
461 }
462 }
463
464 static BOOL be_x86_64_is_jump(const void* insn, ADDRESS64* jumpee)
465 {
466 return FALSE;
467 }
468
469 extern void be_x86_64_disasm_one_insn(ADDRESS64* addr, int display);
470
471 #define DR7_CONTROL_SHIFT 16
472 #define DR7_CONTROL_SIZE 4
473
474 #define DR7_RW_EXECUTE (0x0)
475 #define DR7_RW_WRITE (0x1)
476 #define DR7_RW_READ (0x3)
477
478 #define DR7_LEN_1 (0x0)
479 #define DR7_LEN_2 (0x4)
480 #define DR7_LEN_4 (0xC)
481 #define DR7_LEN_8 (0x8)
482
483 #define DR7_LOCAL_ENABLE_SHIFT 0
484 #define DR7_GLOBAL_ENABLE_SHIFT 1
485 #define DR7_ENABLE_SIZE 2
486
487 #define DR7_LOCAL_ENABLE_MASK (0x55)
488 #define DR7_GLOBAL_ENABLE_MASK (0xAA)
489
490 #define DR7_CONTROL_RESERVED (0xFC00)
491 #define DR7_LOCAL_SLOWDOWN (0x100)
492 #define DR7_GLOBAL_SLOWDOWN (0x200)
493
494 #define DR7_ENABLE_MASK(dr) (1<<(DR7_LOCAL_ENABLE_SHIFT+DR7_ENABLE_SIZE*(dr)))
495 #define IS_DR7_SET(ctrl,dr) ((ctrl)&DR7_ENABLE_MASK(dr))
496
497 static inline int be_x86_64_get_unused_DR(CONTEXT* ctx, DWORD64** r)
498 {
499 if (!IS_DR7_SET(ctx->Dr7, 0))
500 {
501 *r = &ctx->Dr0;
502 return 0;
503 }
504 if (!IS_DR7_SET(ctx->Dr7, 1))
505 {
506 *r = &ctx->Dr1;
507 return 1;
508 }
509 if (!IS_DR7_SET(ctx->Dr7, 2))
510 {
511 *r = &ctx->Dr2;
512 return 2;
513 }
514 if (!IS_DR7_SET(ctx->Dr7, 3))
515 {
516 *r = &ctx->Dr3;
517 return 3;
518 }
519 dbg_printf("All hardware registers have been used\n");
520
521 return -1;
522 }
523
524 static BOOL be_x86_64_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
525 CONTEXT* ctx, enum be_xpoint_type type,
526 void* addr, unsigned long* val, unsigned size)
527 {
528 unsigned char ch;
529 SIZE_T sz;
530 DWORD64 *pr;
531 int reg;
532 unsigned long bits;
533
534 switch (type)
535 {
536 case be_xpoint_break:
537 if (size != 0) return FALSE;
538 if (!pio->read(hProcess, addr, &ch, 1, &sz) || sz != 1) return FALSE;
539 *val = ch;
540 ch = 0xcc;
541 if (!pio->write(hProcess, addr, &ch, 1, &sz) || sz != 1) return FALSE;
542 break;
543 case be_xpoint_watch_exec:
544 bits = DR7_RW_EXECUTE;
545 goto hw_bp;
546 case be_xpoint_watch_read:
547 bits = DR7_RW_READ;
548 goto hw_bp;
549 case be_xpoint_watch_write:
550 bits = DR7_RW_WRITE;
551 hw_bp:
552 if ((reg = be_x86_64_get_unused_DR(ctx, &pr)) == -1) return FALSE;
553 *pr = (DWORD64)addr;
554 if (type != be_xpoint_watch_exec) switch (size)
555 {
556 case 8: bits |= DR7_LEN_8; break;
557 case 4: bits |= DR7_LEN_4; break;
558 case 2: bits |= DR7_LEN_2; break;
559 case 1: bits |= DR7_LEN_1; break;
560 default: WINE_FIXME("Unsupported xpoint_watch of size %d\n", size); return FALSE;
561 }
562 *val = reg;
563 /* clear old values */
564 ctx->Dr7 &= ~(0x0F << (DR7_CONTROL_SHIFT + DR7_CONTROL_SIZE * reg));
565 /* set the correct ones */
566 ctx->Dr7 |= bits << (DR7_CONTROL_SHIFT + DR7_CONTROL_SIZE * reg);
567 ctx->Dr7 |= DR7_ENABLE_MASK(reg) | DR7_LOCAL_SLOWDOWN;
568 break;
569 default:
570 dbg_printf("Unknown bp type %c\n", type);
571 return FALSE;
572 }
573 return TRUE;
574 }
575
576 static BOOL be_x86_64_remove_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
577 CONTEXT* ctx, enum be_xpoint_type type,
578 void* addr, unsigned long val, unsigned size)
579 {
580 SIZE_T sz;
581 unsigned char ch;
582
583 switch (type)
584 {
585 case be_xpoint_break:
586 if (size != 0) return FALSE;
587 if (!pio->read(hProcess, addr, &ch, 1, &sz) || sz != 1) return FALSE;
588 if (ch != (unsigned char)0xCC)
589 WINE_FIXME("Cannot get back %02x instead of 0xCC at %p\n", ch, addr);
590 ch = (unsigned char)val;
591 if (!pio->write(hProcess, addr, &ch, 1, &sz) || sz != 1) return FALSE;
592 break;
593 case be_xpoint_watch_exec:
594 case be_xpoint_watch_read:
595 case be_xpoint_watch_write:
596 /* simply disable the entry */
597 ctx->Dr7 &= ~DR7_ENABLE_MASK(val);
598 break;
599 default:
600 dbg_printf("Unknown bp type %c\n", type);
601 return FALSE;
602 }
603 return TRUE;
604 }
605
606 static BOOL be_x86_64_is_watchpoint_set(const CONTEXT* ctx, unsigned idx)
607 {
608 return ctx->Dr6 & (1 << idx);
609 }
610
611 static void be_x86_64_clear_watchpoint(CONTEXT* ctx, unsigned idx)
612 {
613 ctx->Dr6 &= ~(1 << idx);
614 }
615
616 static int be_x86_64_adjust_pc_for_break(CONTEXT* ctx, BOOL way)
617 {
618 if (way)
619 {
620 ctx->Rip--;
621 return -1;
622 }
623 ctx->Rip++;
624 return 1;
625 }
626
627 static BOOL be_x86_64_fetch_integer(const struct dbg_lvalue* lvalue, unsigned size,
628 BOOL is_signed, LONGLONG* ret)
629 {
630 if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16)
631 return FALSE;
632
633 memset(ret, 0, sizeof(*ret)); /* clear unread bytes */
634 /* FIXME: this assumes that debuggee and debugger use the same
635 * integral representation
636 */
637 if (!memory_read_value(lvalue, size, ret)) return FALSE;
638
639 /* propagate sign information */
640 if (is_signed && size < 16 && (*ret >> (size * 8 - 1)) != 0)
641 {
642 ULONGLONG neg = -1;
643 *ret |= neg << (size * 8);
644 }
645 return TRUE;
646 }
647
648 static BOOL be_x86_64_fetch_float(const struct dbg_lvalue* lvalue, unsigned size,
649 long double* ret)
650 {
651 char tmp[sizeof(long double)];
652
653 /* FIXME: this assumes that debuggee and debugger use the same
654 * representation for reals
655 */
656 if (!memory_read_value(lvalue, size, tmp)) return FALSE;
657
658 /* float & double types have to be promoted to a long double */
659 if (size == 4) *ret = *(float*)tmp;
660 else if (size == 8) *ret = *(double*)tmp;
661 else if (size == 10) *ret = *(long double*)tmp;
662 else return FALSE;
663
664 return TRUE;
665 }
666
667 static BOOL be_x86_64_store_integer(const struct dbg_lvalue* lvalue, unsigned size,
668 BOOL is_signed, LONGLONG val)
669 {
670 /* this is simple as we're on a little endian CPU */
671 return memory_write_value(lvalue, size, &val);
672 }
673
674 struct backend_cpu be_x86_64 =
675 {
676 IMAGE_FILE_MACHINE_AMD64,
677 8,
678 be_cpu_linearize,
679 be_cpu_build_addr,
680 be_x86_64_get_addr,
681 be_x86_64_get_register_info,
682 be_x86_64_single_step,
683 be_x86_64_print_context,
684 be_x86_64_print_segment_info,
685 be_x86_64_ctx,
686 be_x86_64_is_step_over_insn,
687 be_x86_64_is_function_return,
688 be_x86_64_is_break_insn,
689 be_x86_64_is_func_call,
690 be_x86_64_is_jump,
691 be_x86_64_disasm_one_insn,
692 be_x86_64_insert_Xpoint,
693 be_x86_64_remove_Xpoint,
694 be_x86_64_is_watchpoint_set,
695 be_x86_64_clear_watchpoint,
696 be_x86_64_adjust_pc_for_break,
697 be_x86_64_fetch_integer,
698 be_x86_64_fetch_float,
699 be_x86_64_store_integer,
700 };
701 #endif
Windows API implementation