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comctl32/tests: Flush events before testing edit control IME messages.
[wine.git] / dlls / d3dcompiler_43 / asmshader.y
blobcdc75c18a3edef53e40b034d75ccfd48d3f6539e
1 /*
2 * Direct3D shader assembler
3 *
4 * Copyright 2008 Stefan Dösinger
5 * Copyright 2009 Matteo Bruni
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
20 */
21
22 %{
23 #include "wine/debug.h"
24
25 #include "d3dcompiler_private.h"
26
27 WINE_DEFAULT_DEBUG_CHANNEL(asmshader);
28
29 struct asm_parser asm_ctx;
30
31 void WINAPIV asmparser_message(struct asm_parser *ctx, const char *fmt, ...)
32 {
33 va_list args;
34
35 va_start(args, fmt);
36 compilation_message(&ctx->messages, fmt, args);
37 va_end(args);
38 }
39
40 static void asmshader_error(char const *s) {
41 asmparser_message(&asm_ctx, "Line %u: Error \"%s\" from bison\n", asm_ctx.line_no, s);
42 set_parse_status(&asm_ctx.status, PARSE_ERR);
43 }
44
45 static void set_rel_reg(struct shader_reg *reg, struct rel_reg *rel) {
46 /* We can have an additional offset without true relative addressing
47 * ex. c2[ 4 ] */
48 reg->regnum += rel->additional_offset;
49 if(!rel->has_rel_reg) {
50 reg->rel_reg = NULL;
51 } else {
52 reg->rel_reg = d3dcompiler_alloc(sizeof(*reg->rel_reg));
53 if(!reg->rel_reg) {
54 return;
55 }
56 reg->rel_reg->type = rel->type;
57 reg->rel_reg->swizzle = rel->swizzle;
58 reg->rel_reg->regnum = rel->rel_regnum;
59 }
60 }
61
62 /* Needed lexer functions declarations */
63 int asmshader_lex(void);
64
65
66 %}
67
68 %define api.prefix {asmshader_}
69
70 %union {
71 struct {
72 float val;
73 BOOL integer;
74 } immval;
75 BOOL immbool;
76 unsigned int regnum;
77 struct shader_reg reg;
78 uint32_t srcmod;
79 uint32_t writemask;
80 struct {
81 uint32_t writemask;
82 uint32_t idx;
83 uint32_t last;
84 } wm_components;
85 uint32_t swizzle;
86 struct {
87 uint32_t swizzle;
88 uint32_t idx;
89 } sw_components;
90 uint32_t component;
91 struct {
92 uint32_t mod;
93 uint32_t shift;
94 } modshift;
95 enum bwriter_comparison_type comptype;
96 struct {
97 uint32_t dclusage;
98 unsigned int regnum;
99 } declaration;
100 enum bwritersampler_texture_type samplertype;
101 struct rel_reg rel_reg;
102 struct src_regs sregs;
103 }
104
105 /* Common instructions between vertex and pixel shaders */
106 %token INSTR_ADD
107 %token INSTR_NOP
108 %token INSTR_MOV
109 %token INSTR_SUB
110 %token INSTR_MAD
111 %token INSTR_MUL
112 %token INSTR_RCP
113 %token INSTR_RSQ
114 %token INSTR_DP3
115 %token INSTR_DP4
116 %token INSTR_MIN
117 %token INSTR_MAX
118 %token INSTR_SLT
119 %token INSTR_SGE
120 %token INSTR_ABS
121 %token INSTR_EXP
122 %token INSTR_LOG
123 %token INSTR_EXPP
124 %token INSTR_LOGP
125 %token INSTR_DST
126 %token INSTR_LRP
127 %token INSTR_FRC
128 %token INSTR_POW
129 %token INSTR_CRS
130 %token INSTR_SGN
131 %token INSTR_NRM
132 %token INSTR_SINCOS
133 %token INSTR_M4x4
134 %token INSTR_M4x3
135 %token INSTR_M3x4
136 %token INSTR_M3x3
137 %token INSTR_M3x2
138 %token INSTR_DCL
139 %token INSTR_DEF
140 %token INSTR_DEFB
141 %token INSTR_DEFI
142 %token INSTR_REP
143 %token INSTR_ENDREP
144 %token INSTR_IF
145 %token INSTR_ELSE
146 %token INSTR_ENDIF
147 %token INSTR_BREAK
148 %token INSTR_BREAKP
149 %token INSTR_CALL
150 %token INSTR_CALLNZ
151 %token INSTR_LOOP
152 %token INSTR_RET
153 %token INSTR_ENDLOOP
154 %token INSTR_LABEL
155 %token INSTR_SETP
156 %token INSTR_TEXLDL
157
158 /* Vertex shader only instructions */
159 %token INSTR_LIT
160 %token INSTR_MOVA
161
162 /* Pixel shader only instructions */
163 %token INSTR_CND
164 %token INSTR_CMP
165 %token INSTR_DP2ADD
166 %token INSTR_TEXCOORD
167 %token INSTR_TEXCRD
168 %token INSTR_TEXKILL
169 %token INSTR_TEX
170 %token INSTR_TEXLD
171 %token INSTR_TEXBEM
172 %token INSTR_TEXBEML
173 %token INSTR_TEXREG2AR
174 %token INSTR_TEXREG2GB
175 %token INSTR_TEXREG2RGB
176 %token INSTR_TEXM3x2PAD
177 %token INSTR_TEXM3x2TEX
178 %token INSTR_TEXM3x3PAD
179 %token INSTR_TEXM3x3SPEC
180 %token INSTR_TEXM3x3VSPEC
181 %token INSTR_TEXM3x3TEX
182 %token INSTR_TEXDP3TEX
183 %token INSTR_TEXM3x2DEPTH
184 %token INSTR_TEXDP3
185 %token INSTR_TEXM3x3
186 %token INSTR_TEXDEPTH
187 %token INSTR_BEM
188 %token INSTR_DSX
189 %token INSTR_DSY
190 %token INSTR_TEXLDP
191 %token INSTR_TEXLDB
192 %token INSTR_TEXLDD
193 %token INSTR_PHASE
194
195 /* Registers */
196 %token <regnum> REG_TEMP
197 %token <regnum> REG_OUTPUT
198 %token <regnum> REG_INPUT
199 %token <regnum> REG_CONSTFLOAT
200 %token <regnum> REG_CONSTINT
201 %token <regnum> REG_CONSTBOOL
202 %token <regnum> REG_TEXTURE
203 %token <regnum> REG_SAMPLER
204 %token <regnum> REG_TEXCRDOUT
205 %token REG_OPOS
206 %token REG_OFOG
207 %token REG_OPTS
208 %token <regnum> REG_VERTEXCOLOR
209 %token <regnum> REG_FRAGCOLOR
210 %token REG_FRAGDEPTH
211 %token REG_VPOS
212 %token REG_VFACE
213 %token REG_ADDRESS
214 %token REG_LOOP
215 %token REG_PREDICATE
216 %token <regnum> REG_LABEL
217
218 /* Version tokens */
219 %token VER_VS10
220 %token VER_VS11
221 %token VER_VS20
222 %token VER_VS2X
223 %token VER_VS30
224
225 %token VER_PS10
226 %token VER_PS11
227 %token VER_PS12
228 %token VER_PS13
229 %token VER_PS14
230 %token VER_PS20
231 %token VER_PS2X
232 %token VER_PS30
233
234 /* Output modifiers */
235 %token SHIFT_X2
236 %token SHIFT_X4
237 %token SHIFT_X8
238 %token SHIFT_D2
239 %token SHIFT_D4
240 %token SHIFT_D8
241 %token MOD_SAT
242 %token MOD_PP
243 %token MOD_CENTROID
244
245 /* Compare tokens */
246 %token COMP_GT
247 %token COMP_LT
248 %token COMP_GE
249 %token COMP_LE
250 %token COMP_EQ
251 %token COMP_NE
252
253 /* Source register modifiers */
254 %token SMOD_BIAS
255 %token SMOD_SCALEBIAS
256 %token SMOD_DZ
257 %token SMOD_DW
258 %token SMOD_ABS
259 %token SMOD_NOT
260
261 /* Sampler types */
262 %token SAMPTYPE_1D
263 %token SAMPTYPE_2D
264 %token SAMPTYPE_CUBE
265 %token SAMPTYPE_VOLUME
266
267 /* Usage declaration tokens */
268 %token <regnum> USAGE_POSITION
269 %token <regnum> USAGE_BLENDWEIGHT
270 %token <regnum> USAGE_BLENDINDICES
271 %token <regnum> USAGE_NORMAL
272 %token <regnum> USAGE_PSIZE
273 %token <regnum> USAGE_TEXCOORD
274 %token <regnum> USAGE_TANGENT
275 %token <regnum> USAGE_BINORMAL
276 %token <regnum> USAGE_TESSFACTOR
277 %token <regnum> USAGE_POSITIONT
278 %token <regnum> USAGE_COLOR
279 %token <regnum> USAGE_FOG
280 %token <regnum> USAGE_DEPTH
281 %token <regnum> USAGE_SAMPLE
282
283 /* Misc stuff */
284 %token <component> COMPONENT
285 %token <immval> IMMVAL
286 %token <immbool> IMMBOOL
287
288 %type <reg> dreg_name
289 %type <reg> dreg
290 %type <reg> sreg_name
291 %type <reg> relreg_name
292 %type <reg> sreg
293 %type <srcmod> smod
294 %type <writemask> writemask
295 %type <wm_components> wm_components
296 %type <swizzle> swizzle
297 %type <sw_components> sw_components
298 %type <modshift> omods
299 %type <modshift> omodifier
300 %type <comptype> comp
301 %type <declaration> dclusage
302 %type <reg> dcl_inputreg
303 %type <samplertype> sampdcl
304 %type <rel_reg> rel_reg
305 %type <reg> predicate
306 %type <immval> immsum
307 %type <immval> signed_integer
308 %type <immval> signed_float
309 %type <sregs> sregs
310
311 %%
312
313 shader: version_marker instructions
314 {
315 asm_ctx.funcs->end(&asm_ctx);
316 }
317
318 version_marker: VER_VS10
319 {
320 TRACE("Vertex shader 1.0\n");
321 create_vs10_parser(&asm_ctx);
322 }
323 | VER_VS11
324 {
325 TRACE("Vertex shader 1.1\n");
326 create_vs11_parser(&asm_ctx);
327 }
328 | VER_VS20
329 {
330 TRACE("Vertex shader 2.0\n");
331 create_vs20_parser(&asm_ctx);
332 }
333 | VER_VS2X
334 {
335 TRACE("Vertex shader 2.x\n");
336 create_vs2x_parser(&asm_ctx);
337 }
338 | VER_VS30
339 {
340 TRACE("Vertex shader 3.0\n");
341 create_vs30_parser(&asm_ctx);
342 }
343 | VER_PS10
344 {
345 TRACE("Pixel shader 1.0\n");
346 create_ps10_parser(&asm_ctx);
347 }
348 | VER_PS11
349 {
350 TRACE("Pixel shader 1.1\n");
351 create_ps11_parser(&asm_ctx);
352 }
353 | VER_PS12
354 {
355 TRACE("Pixel shader 1.2\n");
356 create_ps12_parser(&asm_ctx);
357 }
358 | VER_PS13
359 {
360 TRACE("Pixel shader 1.3\n");
361 create_ps13_parser(&asm_ctx);
362 }
363 | VER_PS14
364 {
365 TRACE("Pixel shader 1.4\n");
366 create_ps14_parser(&asm_ctx);
367 }
368 | VER_PS20
369 {
370 TRACE("Pixel shader 2.0\n");
371 create_ps20_parser(&asm_ctx);
372 }
373 | VER_PS2X
374 {
375 TRACE("Pixel shader 2.x\n");
376 create_ps2x_parser(&asm_ctx);
377 }
378 | VER_PS30
379 {
380 TRACE("Pixel shader 3.0\n");
381 create_ps30_parser(&asm_ctx);
382 }
383
384 instructions: /* empty */
385 | instructions complexinstr
386 {
387 /* Nothing to do */
388 }
389
390 complexinstr: instruction
391 {
392
393 }
394 | predicate instruction
395 {
396 TRACE("predicate\n");
397 asm_ctx.funcs->predicate(&asm_ctx, &$1);
398 }
399 | '+' instruction
400 {
401 TRACE("coissue\n");
402 asm_ctx.funcs->coissue(&asm_ctx);
403 }
404
405 instruction: INSTR_ADD omods dreg ',' sregs
406 {
407 TRACE("ADD\n");
408 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ADD, $2.mod, $2.shift, 0, &$3, &$5, 2);
409 }
410 | INSTR_NOP
411 {
412 TRACE("NOP\n");
413 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_NOP, 0, 0, 0, 0, 0, 0);
414 }
415 | INSTR_MOV omods dreg ',' sregs
416 {
417 TRACE("MOV\n");
418 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MOV, $2.mod, $2.shift, 0, &$3, &$5, 1);
419 }
420 | INSTR_SUB omods dreg ',' sregs
421 {
422 TRACE("SUB\n");
423 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SUB, $2.mod, $2.shift, 0, &$3, &$5, 2);
424 }
425 | INSTR_MAD omods dreg ',' sregs
426 {
427 TRACE("MAD\n");
428 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MAD, $2.mod, $2.shift, 0, &$3, &$5, 3);
429 }
430 | INSTR_MUL omods dreg ',' sregs
431 {
432 TRACE("MUL\n");
433 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MUL, $2.mod, $2.shift, 0, &$3, &$5, 2);
434 }
435 | INSTR_RCP omods dreg ',' sregs
436 {
437 TRACE("RCP\n");
438 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RCP, $2.mod, $2.shift, 0, &$3, &$5, 1);
439 }
440 | INSTR_RSQ omods dreg ',' sregs
441 {
442 TRACE("RSQ\n");
443 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RSQ, $2.mod, $2.shift, 0, &$3, &$5, 1);
444 }
445 | INSTR_DP3 omods dreg ',' sregs
446 {
447 TRACE("DP3\n");
448 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP3, $2.mod, $2.shift, 0, &$3, &$5, 2);
449 }
450 | INSTR_DP4 omods dreg ',' sregs
451 {
452 TRACE("DP4\n");
453 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP4, $2.mod, $2.shift, 0, &$3, &$5, 2);
454 }
455 | INSTR_MIN omods dreg ',' sregs
456 {
457 TRACE("MIN\n");
458 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MIN, $2.mod, $2.shift, 0, &$3, &$5, 2);
459 }
460 | INSTR_MAX omods dreg ',' sregs
461 {
462 TRACE("MAX\n");
463 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MAX, $2.mod, $2.shift, 0, &$3, &$5, 2);
464 }
465 | INSTR_SLT omods dreg ',' sregs
466 {
467 TRACE("SLT\n");
468 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SLT, $2.mod, $2.shift, 0, &$3, &$5, 2);
469 }
470 | INSTR_SGE omods dreg ',' sregs
471 {
472 TRACE("SGE\n");
473 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SGE, $2.mod, $2.shift, 0, &$3, &$5, 2);
474 }
475 | INSTR_ABS omods dreg ',' sregs
476 {
477 TRACE("ABS\n");
478 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ABS, $2.mod, $2.shift, 0, &$3, &$5, 1);
479 }
480 | INSTR_EXP omods dreg ',' sregs
481 {
482 TRACE("EXP\n");
483 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_EXP, $2.mod, $2.shift, 0, &$3, &$5, 1);
484 }
485 | INSTR_LOG omods dreg ',' sregs
486 {
487 TRACE("LOG\n");
488 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOG, $2.mod, $2.shift, 0, &$3, &$5, 1);
489 }
490 | INSTR_LOGP omods dreg ',' sregs
491 {
492 TRACE("LOGP\n");
493 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOGP, $2.mod, $2.shift, 0, &$3, &$5, 1);
494 }
495 | INSTR_EXPP omods dreg ',' sregs
496 {
497 TRACE("EXPP\n");
498 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_EXPP, $2.mod, $2.shift, 0, &$3, &$5, 1);
499 }
500 | INSTR_DST omods dreg ',' sregs
501 {
502 TRACE("DST\n");
503 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DST, $2.mod, $2.shift, 0, &$3, &$5, 2);
504 }
505 | INSTR_LRP omods dreg ',' sregs
506 {
507 TRACE("LRP\n");
508 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LRP, $2.mod, $2.shift, 0, &$3, &$5, 3);
509 }
510 | INSTR_FRC omods dreg ',' sregs
511 {
512 TRACE("FRC\n");
513 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_FRC, $2.mod, $2.shift, 0, &$3, &$5, 1);
514 }
515 | INSTR_POW omods dreg ',' sregs
516 {
517 TRACE("POW\n");
518 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_POW, $2.mod, $2.shift, 0, &$3, &$5, 2);
519 }
520 | INSTR_CRS omods dreg ',' sregs
521 {
522 TRACE("CRS\n");
523 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CRS, $2.mod, $2.shift, 0, &$3, &$5, 2);
524 }
525 | INSTR_SGN omods dreg ',' sregs
526 {
527 TRACE("SGN\n");
528 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SGN, $2.mod, $2.shift, 0, &$3, &$5, 3);
529 }
530 | INSTR_NRM omods dreg ',' sregs
531 {
532 TRACE("NRM\n");
533 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_NRM, $2.mod, $2.shift, 0, &$3, &$5, 1);
534 }
535 | INSTR_SINCOS omods dreg ',' sregs
536 {
537 TRACE("SINCOS\n");
538 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SINCOS, $2.mod, $2.shift, 0, &$3, &$5, 1);
539 }
540 | INSTR_M4x4 omods dreg ',' sregs
541 {
542 TRACE("M4x4\n");
543 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M4x4, $2.mod, $2.shift, 0, &$3, &$5, 2);
544 }
545 | INSTR_M4x3 omods dreg ',' sregs
546 {
547 TRACE("M4x3\n");
548 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M4x3, $2.mod, $2.shift, 0, &$3, &$5, 2);
549 }
550 | INSTR_M3x4 omods dreg ',' sregs
551 {
552 TRACE("M3x4\n");
553 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x4, $2.mod, $2.shift, 0, &$3, &$5, 2);
554 }
555 | INSTR_M3x3 omods dreg ',' sregs
556 {
557 TRACE("M3x3\n");
558 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x3, $2.mod, $2.shift, 0, &$3, &$5, 2);
559 }
560 | INSTR_M3x2 omods dreg ',' sregs
561 {
562 TRACE("M3x2\n");
563 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_M3x2, $2.mod, $2.shift, 0, &$3, &$5, 2);
564 }
565 | INSTR_DCL dclusage REG_OUTPUT
566 {
567 struct shader_reg reg;
568 TRACE("Output reg declaration\n");
569 ZeroMemory(&reg, sizeof(reg));
570 reg.type = BWRITERSPR_OUTPUT;
571 reg.regnum = $3;
572 reg.rel_reg = NULL;
573 reg.srcmod = 0;
574 reg.writemask = BWRITERSP_WRITEMASK_ALL;
575 asm_ctx.funcs->dcl_output(&asm_ctx, $2.dclusage, $2.regnum, &reg);
576 }
577 | INSTR_DCL dclusage REG_OUTPUT writemask
578 {
579 struct shader_reg reg;
580 TRACE("Output reg declaration\n");
581 ZeroMemory(&reg, sizeof(reg));
582 reg.type = BWRITERSPR_OUTPUT;
583 reg.regnum = $3;
584 reg.rel_reg = NULL;
585 reg.srcmod = 0;
586 reg.writemask = $4;
587 asm_ctx.funcs->dcl_output(&asm_ctx, $2.dclusage, $2.regnum, &reg);
588 }
589 | INSTR_DCL dclusage omods dcl_inputreg
590 {
591 struct shader_reg reg;
592 TRACE("Input reg declaration\n");
593 if($3.shift != 0) {
594 asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
595 asm_ctx.line_no);
596 set_parse_status(&asm_ctx.status, PARSE_ERR);
597 }
598 if (asm_ctx.shader->type == ST_PIXEL && asm_ctx.shader->major_version == 2)
599 {
600 asmparser_message(&asm_ctx, "Line %u: Declaration not supported in PS 2\n",
601 asm_ctx.line_no);
602 set_parse_status(&asm_ctx.status, PARSE_ERR);
603 }
604 ZeroMemory(&reg, sizeof(reg));
605 reg.type = $4.type;
606 reg.regnum = $4.regnum;
607 reg.rel_reg = NULL;
608 reg.srcmod = 0;
609 reg.writemask = BWRITERSP_WRITEMASK_ALL;
610 asm_ctx.funcs->dcl_input(&asm_ctx, $2.dclusage, $2.regnum, $3.mod, &reg);
611 }
612 | INSTR_DCL dclusage omods dcl_inputreg writemask
613 {
614 struct shader_reg reg;
615 TRACE("Input reg declaration\n");
616 if($3.shift != 0) {
617 asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
618 asm_ctx.line_no);
619 set_parse_status(&asm_ctx.status, PARSE_ERR);
620 }
621 if (asm_ctx.shader->type == ST_PIXEL && asm_ctx.shader->major_version == 2)
622 {
623 asmparser_message(&asm_ctx, "Line %u: Declaration not supported in PS 2\n",
624 asm_ctx.line_no);
625 set_parse_status(&asm_ctx.status, PARSE_ERR);
626 }
627 ZeroMemory(&reg, sizeof(reg));
628 reg.type = $4.type;
629 reg.regnum = $4.regnum;
630 reg.rel_reg = NULL;
631 reg.srcmod = 0;
632 reg.writemask = $5;
633 asm_ctx.funcs->dcl_input(&asm_ctx, $2.dclusage, $2.regnum, $3.mod, &reg);
634 }
635 | INSTR_DCL omods dcl_inputreg
636 {
637 struct shader_reg reg;
638 TRACE("Input reg declaration\n");
639 if($2.shift != 0) {
640 asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
641 asm_ctx.line_no);
642 set_parse_status(&asm_ctx.status, PARSE_ERR);
643 }
644 if(asm_ctx.shader->type != ST_PIXEL) {
645 asmparser_message(&asm_ctx, "Line %u: Declaration needs a semantic\n",
646 asm_ctx.line_no);
647 set_parse_status(&asm_ctx.status, PARSE_ERR);
648 }
649 ZeroMemory(&reg, sizeof(reg));
650 reg.type = $3.type;
651 reg.regnum = $3.regnum;
652 reg.rel_reg = NULL;
653 reg.srcmod = 0;
654 reg.writemask = BWRITERSP_WRITEMASK_ALL;
655 asm_ctx.funcs->dcl_input(&asm_ctx, 0, 0, $2.mod, &reg);
656 }
657 | INSTR_DCL omods dcl_inputreg writemask
658 {
659 struct shader_reg reg;
660 TRACE("Input reg declaration\n");
661 if($2.shift != 0) {
662 asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
663 asm_ctx.line_no);
664 set_parse_status(&asm_ctx.status, PARSE_ERR);
665 }
666 if(asm_ctx.shader->type != ST_PIXEL) {
667 asmparser_message(&asm_ctx, "Line %u: Declaration needs a semantic\n",
668 asm_ctx.line_no);
669 set_parse_status(&asm_ctx.status, PARSE_ERR);
670 }
671 ZeroMemory(&reg, sizeof(reg));
672 reg.type = $3.type;
673 reg.regnum = $3.regnum;
674 reg.rel_reg = NULL;
675 reg.srcmod = 0;
676 reg.writemask = $4;
677 asm_ctx.funcs->dcl_input(&asm_ctx, 0, 0, $2.mod, &reg);
678 }
679 | INSTR_DCL sampdcl omods REG_SAMPLER
680 {
681 TRACE("Sampler declared\n");
682 if($3.shift != 0) {
683 asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
684 asm_ctx.line_no);
685 set_parse_status(&asm_ctx.status, PARSE_ERR);
686 }
687 asm_ctx.funcs->dcl_sampler(&asm_ctx, $2, $3.mod, $4, asm_ctx.line_no);
688 }
689 | INSTR_DCL omods REG_SAMPLER
690 {
691 TRACE("Sampler declared\n");
692 if($2.shift != 0) {
693 asmparser_message(&asm_ctx, "Line %u: Shift modifier not allowed here\n",
694 asm_ctx.line_no);
695 set_parse_status(&asm_ctx.status, PARSE_ERR);
696 }
697 if(asm_ctx.shader->type != ST_PIXEL) {
698 asmparser_message(&asm_ctx, "Line %u: Declaration needs a sampler type\n",
699 asm_ctx.line_no);
700 set_parse_status(&asm_ctx.status, PARSE_ERR);
701 }
702 asm_ctx.funcs->dcl_sampler(&asm_ctx, BWRITERSTT_UNKNOWN, $2.mod, $3, asm_ctx.line_no);
703 }
704 | INSTR_DCL sampdcl omods dcl_inputreg
705 {
706 TRACE("Error rule: sampler decl of input reg\n");
707 asmparser_message(&asm_ctx, "Line %u: Sampler declarations of input regs is not valid\n",
708 asm_ctx.line_no);
709 set_parse_status(&asm_ctx.status, PARSE_WARN);
710 }
711 | INSTR_DCL sampdcl omods REG_OUTPUT
712 {
713 TRACE("Error rule: sampler decl of output reg\n");
714 asmparser_message(&asm_ctx, "Line %u: Sampler declarations of output regs is not valid\n",
715 asm_ctx.line_no);
716 set_parse_status(&asm_ctx.status, PARSE_WARN);
717 }
718 | INSTR_DEF REG_CONSTFLOAT ',' signed_float ',' signed_float ',' signed_float ',' signed_float
719 {
720 asm_ctx.funcs->constF(&asm_ctx, $2, $4.val, $6.val, $8.val, $10.val);
721 }
722 | INSTR_DEFI REG_CONSTINT ',' signed_integer ',' signed_integer ',' signed_integer ',' signed_integer
723 {
724 asm_ctx.funcs->constI(&asm_ctx, $2, $4.val, $6.val, $8.val, $10.val);
725 }
726 | INSTR_DEFB REG_CONSTBOOL ',' IMMBOOL
727 {
728 asm_ctx.funcs->constB(&asm_ctx, $2, $4);
729 }
730 | INSTR_REP sregs
731 {
732 TRACE("REP\n");
733 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_REP, 0, 0, 0, 0, &$2, 1);
734 }
735 | INSTR_ENDREP
736 {
737 TRACE("ENDREP\n");
738 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ENDREP, 0, 0, 0, 0, 0, 0);
739 }
740 | INSTR_IF sregs
741 {
742 TRACE("IF\n");
743 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_IF, 0, 0, 0, 0, &$2, 1);
744 }
745 | INSTR_IF comp sregs
746 {
747 TRACE("IFC\n");
748 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_IFC, 0, 0, $2, 0, &$3, 2);
749 }
750 | INSTR_ELSE
751 {
752 TRACE("ELSE\n");
753 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ELSE, 0, 0, 0, 0, 0, 0);
754 }
755 | INSTR_ENDIF
756 {
757 TRACE("ENDIF\n");
758 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ENDIF, 0, 0, 0, 0, 0, 0);
759 }
760 | INSTR_BREAK
761 {
762 TRACE("BREAK\n");
763 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAK, 0, 0, 0, 0, 0, 0);
764 }
765 | INSTR_BREAK comp sregs
766 {
767 TRACE("BREAKC\n");
768 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAKC, 0, 0, $2, 0, &$3, 2);
769 }
770 | INSTR_BREAKP sregs
771 {
772 TRACE("BREAKP\n");
773 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BREAKP, 0, 0, 0, 0, &$2, 1);
774 }
775 | INSTR_CALL sregs
776 {
777 TRACE("CALL\n");
778 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CALL, 0, 0, 0, 0, &$2, 1);
779 }
780 | INSTR_CALLNZ sregs
781 {
782 TRACE("CALLNZ\n");
783 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CALLNZ, 0, 0, 0, 0, &$2, 2);
784 }
785 | INSTR_LOOP sregs
786 {
787 TRACE("LOOP\n");
788 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LOOP, 0, 0, 0, 0, &$2, 2);
789 }
790 | INSTR_RET
791 {
792 TRACE("RET\n");
793 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_RET, 0, 0, 0, 0, 0, 0);
794 }
795 | INSTR_ENDLOOP
796 {
797 TRACE("ENDLOOP\n");
798 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_ENDLOOP, 0, 0, 0, 0, 0, 0);
799 }
800 | INSTR_LABEL sregs
801 {
802 TRACE("LABEL\n");
803 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LABEL, 0, 0, 0, 0, &$2, 1);
804 }
805 | INSTR_SETP comp dreg ',' sregs
806 {
807 TRACE("SETP\n");
808 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_SETP, 0, 0, $2, &$3, &$5, 2);
809 }
810 | INSTR_TEXLDL omods dreg ',' sregs
811 {
812 TRACE("TEXLDL\n");
813 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDL, $2.mod, $2.shift, 0, &$3, &$5, 2);
814 }
815 | INSTR_LIT omods dreg ',' sregs
816 {
817 TRACE("LIT\n");
818 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_LIT, $2.mod, $2.shift, 0, &$3, &$5, 1);
819 }
820 | INSTR_MOVA omods dreg ',' sregs
821 {
822 TRACE("MOVA\n");
823 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_MOVA, $2.mod, $2.shift, 0, &$3, &$5, 1);
824 }
825 | INSTR_CND omods dreg ',' sregs
826 {
827 TRACE("CND\n");
828 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CND, $2.mod, $2.shift, 0, &$3, &$5, 3);
829 }
830 | INSTR_CMP omods dreg ',' sregs
831 {
832 TRACE("CMP\n");
833 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_CMP, $2.mod, $2.shift, 0, &$3, &$5, 3);
834 }
835 | INSTR_DP2ADD omods dreg ',' sregs
836 {
837 TRACE("DP2ADD\n");
838 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DP2ADD, $2.mod, $2.shift, 0, &$3, &$5, 3);
839 }
840 | INSTR_TEXCOORD omods dreg
841 {
842 TRACE("TEXCOORD\n");
843 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXCOORD, $2.mod, $2.shift, 0, &$3, 0, 0);
844 }
845 | INSTR_TEXCRD omods dreg ',' sregs
846 {
847 TRACE("TEXCRD\n");
848 /* texcoord and texcrd share the same opcode */
849 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXCOORD, $2.mod, $2.shift, 0, &$3, &$5, 1);
850 }
851 | INSTR_TEXKILL dreg
852 {
853 TRACE("TEXKILL\n");
854 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXKILL, 0, 0, 0, &$2, 0, 0);
855 }
856 | INSTR_TEX omods dreg
857 {
858 TRACE("TEX\n");
859 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEX, $2.mod, $2.shift, 0, &$3, 0, 0);
860 }
861 | INSTR_TEXDEPTH omods dreg
862 {
863 TRACE("TEXDEPTH\n");
864 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDEPTH, $2.mod, $2.shift, 0, &$3, 0, 0);
865 }
866 | INSTR_TEXLD omods dreg ',' sregs
867 {
868 TRACE("TEXLD\n");
869 /* There is more than one acceptable syntax for texld:
870 with 1 sreg (PS 1.4) or
871 with 2 sregs (PS 2.0+)
872 Moreover, texld shares the same opcode as the tex instruction,
873 so there are a total of 3 valid syntaxes
874 These variations are handled in asmparser.c */
875 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEX, $2.mod, $2.shift, 0, &$3, &$5, 2);
876 }
877 | INSTR_TEXLDP omods dreg ',' sregs
878 {
879 TRACE("TEXLDP\n");
880 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDP, $2.mod, $2.shift, 0, &$3, &$5, 2);
881 }
882 | INSTR_TEXLDB omods dreg ',' sregs
883 {
884 TRACE("TEXLDB\n");
885 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDB, $2.mod, $2.shift, 0, &$3, &$5, 2);
886 }
887 | INSTR_TEXBEM omods dreg ',' sregs
888 {
889 TRACE("TEXBEM\n");
890 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXBEM, $2.mod, $2.shift, 0, &$3, &$5, 1);
891 }
892 | INSTR_TEXBEML omods dreg ',' sregs
893 {
894 TRACE("TEXBEML\n");
895 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXBEML, $2.mod, $2.shift, 0, &$3, &$5, 1);
896 }
897 | INSTR_TEXREG2AR omods dreg ',' sregs
898 {
899 TRACE("TEXREG2AR\n");
900 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2AR, $2.mod, $2.shift, 0, &$3, &$5, 1);
901 }
902 | INSTR_TEXREG2GB omods dreg ',' sregs
903 {
904 TRACE("TEXREG2GB\n");
905 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2GB, $2.mod, $2.shift, 0, &$3, &$5, 1);
906 }
907 | INSTR_TEXREG2RGB omods dreg ',' sregs
908 {
909 TRACE("TEXREG2RGB\n");
910 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXREG2RGB, $2.mod, $2.shift, 0, &$3, &$5, 1);
911 }
912 | INSTR_TEXM3x2PAD omods dreg ',' sregs
913 {
914 TRACE("TEXM3x2PAD\n");
915 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2PAD, $2.mod, $2.shift, 0, &$3, &$5, 1);
916 }
917 | INSTR_TEXM3x3PAD omods dreg ',' sregs
918 {
919 TRACE("INSTR_TEXM3x3PAD\n");
920 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3PAD, $2.mod, $2.shift, 0, &$3, &$5, 1);
921 }
922 | INSTR_TEXM3x3SPEC omods dreg ',' sregs
923 {
924 TRACE("TEXM3x3SPEC\n");
925 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3SPEC, $2.mod, $2.shift, 0, &$3, &$5, 2);
926 }
927 | INSTR_TEXM3x3VSPEC omods dreg ',' sregs
928 {
929 TRACE("TEXM3x3VSPEC\n");
930 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3VSPEC, $2.mod, $2.shift, 0, &$3, &$5, 1);
931 }
932 | INSTR_TEXM3x3TEX omods dreg ',' sregs
933 {
934 TRACE("TEXM3x3TEX\n");
935 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
936 }
937 | INSTR_TEXDP3TEX omods dreg ',' sregs
938 {
939 TRACE("TEXDP3TEX\n");
940 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDP3TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
941 }
942 | INSTR_TEXM3x2DEPTH omods dreg ',' sregs
943 {
944 TRACE("TEXM3x2DEPTH\n");
945 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2DEPTH, $2.mod, $2.shift, 0, &$3, &$5, 1);
946 }
947 | INSTR_TEXM3x2TEX omods dreg ',' sregs
948 {
949 TRACE("TEXM3x2TEX\n");
950 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x2TEX, $2.mod, $2.shift, 0, &$3, &$5, 1);
951 }
952 | INSTR_TEXDP3 omods dreg ',' sregs
953 {
954 TRACE("TEXDP3\n");
955 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXDP3, $2.mod, $2.shift, 0, &$3, &$5, 1);
956 }
957 | INSTR_TEXM3x3 omods dreg ',' sregs
958 {
959 TRACE("TEXM3x3\n");
960 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXM3x3, $2.mod, $2.shift, 0, &$3, &$5, 1);
961 }
962 | INSTR_BEM omods dreg ',' sregs
963 {
964 TRACE("BEM\n");
965 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_BEM, $2.mod, $2.shift, 0, &$3, &$5, 2);
966 }
967 | INSTR_DSX omods dreg ',' sregs
968 {
969 TRACE("DSX\n");
970 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DSX, $2.mod, $2.shift, 0, &$3, &$5, 1);
971 }
972 | INSTR_DSY omods dreg ',' sregs
973 {
974 TRACE("DSY\n");
975 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_DSY, $2.mod, $2.shift, 0, &$3, &$5, 1);
976 }
977 | INSTR_TEXLDD omods dreg ',' sregs
978 {
979 TRACE("TEXLDD\n");
980 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_TEXLDD, $2.mod, $2.shift, 0, &$3, &$5, 4);
981 }
982 | INSTR_PHASE
983 {
984 TRACE("PHASE\n");
985 asm_ctx.funcs->instr(&asm_ctx, BWRITERSIO_PHASE, 0, 0, 0, 0, 0, 0);
986 }
987
988
989 dreg: dreg_name rel_reg
990 {
991 $$.regnum = $1.regnum;
992 $$.type = $1.type;
993 $$.writemask = BWRITERSP_WRITEMASK_ALL;
994 $$.srcmod = BWRITERSPSM_NONE;
995 set_rel_reg(&$$, &$2);
996 }
997 | dreg_name writemask
998 {
999 $$.regnum = $1.regnum;
1000 $$.type = $1.type;
1001 $$.writemask = $2;
1002 $$.srcmod = BWRITERSPSM_NONE;
1003 $$.rel_reg = NULL;
1004 }
1005
1006 dreg_name: REG_TEMP
1007 {
1008 $$.regnum = $1; $$.type = BWRITERSPR_TEMP;
1009 }
1010 | REG_OUTPUT
1011 {
1012 $$.regnum = $1; $$.type = BWRITERSPR_OUTPUT;
1013 }
1014 | REG_INPUT
1015 {
1016 $$.regnum = $1; $$.type = BWRITERSPR_INPUT;
1017 }
1018 | REG_CONSTFLOAT
1019 {
1020 asmparser_message(&asm_ctx, "Line %u: Register c%u is not a valid destination register\n",
1021 asm_ctx.line_no, $1);
1022 set_parse_status(&asm_ctx.status, PARSE_WARN);
1023 }
1024 | REG_CONSTINT
1025 {
1026 asmparser_message(&asm_ctx, "Line %u: Register i%u is not a valid destination register\n",
1027 asm_ctx.line_no, $1);
1028 set_parse_status(&asm_ctx.status, PARSE_WARN);
1029 }
1030 | REG_CONSTBOOL
1031 {
1032 asmparser_message(&asm_ctx, "Line %u: Register b%u is not a valid destination register\n",
1033 asm_ctx.line_no, $1);
1034 set_parse_status(&asm_ctx.status, PARSE_WARN);
1035 }
1036 | REG_TEXTURE
1037 {
1038 $$.regnum = $1; $$.type = BWRITERSPR_TEXTURE;
1039 }
1040 | REG_TEXCRDOUT
1041 {
1042 $$.regnum = $1; $$.type = BWRITERSPR_TEXCRDOUT;
1043 }
1044 | REG_SAMPLER
1045 {
1046 asmparser_message(&asm_ctx, "Line %u: Register s%u is not a valid destination register\n",
1047 asm_ctx.line_no, $1);
1048 set_parse_status(&asm_ctx.status, PARSE_WARN);
1049 }
1050 | REG_OPOS
1051 {
1052 $$.regnum = BWRITERSRO_POSITION; $$.type = BWRITERSPR_RASTOUT;
1053 }
1054 | REG_OPTS
1055 {
1056 $$.regnum = BWRITERSRO_POINT_SIZE; $$.type = BWRITERSPR_RASTOUT;
1057 }
1058 | REG_OFOG
1059 {
1060 $$.regnum = BWRITERSRO_FOG; $$.type = BWRITERSPR_RASTOUT;
1061 }
1062 | REG_VERTEXCOLOR
1063 {
1064 $$.regnum = $1; $$.type = BWRITERSPR_ATTROUT;
1065 }
1066 | REG_FRAGCOLOR
1067 {
1068 $$.regnum = $1; $$.type = BWRITERSPR_COLOROUT;
1069 }
1070 | REG_FRAGDEPTH
1071 {
1072 $$.regnum = 0; $$.type = BWRITERSPR_DEPTHOUT;
1073 }
1074 | REG_PREDICATE
1075 {
1076 $$.regnum = 0; $$.type = BWRITERSPR_PREDICATE;
1077 }
1078 | REG_VPOS
1079 {
1080 asmparser_message(&asm_ctx, "Line %u: Register vPos is not a valid destination register\n",
1081 asm_ctx.line_no);
1082 set_parse_status(&asm_ctx.status, PARSE_WARN);
1083 }
1084 | REG_VFACE
1085 {
1086 asmparser_message(&asm_ctx, "Line %u: Register vFace is not a valid destination register\n",
1087 asm_ctx.line_no);
1088 set_parse_status(&asm_ctx.status, PARSE_WARN);
1089 }
1090 | REG_ADDRESS
1091 {
1092 /* index 0 is hardcoded for the addr register */
1093 $$.regnum = 0; $$.type = BWRITERSPR_ADDR;
1094 }
1095 | REG_LOOP
1096 {
1097 asmparser_message(&asm_ctx, "Line %u: Register aL is not a valid destination register\n",
1098 asm_ctx.line_no);
1099 set_parse_status(&asm_ctx.status, PARSE_WARN);
1100 }
1101
1102 writemask: '.' wm_components
1103 {
1104 if($2.writemask == SWIZZLE_ERR) {
1105 asmparser_message(&asm_ctx, "Line %u: Invalid writemask specified\n",
1106 asm_ctx.line_no);
1107 set_parse_status(&asm_ctx.status, PARSE_ERR);
1108 /* Provide a correct writemask to prevent following complaints */
1109 $$ = BWRITERSP_WRITEMASK_ALL;
1110 }
1111 else {
1112 $$ = $2.writemask;
1113 TRACE("Writemask: %x\n", $$);
1114 }
1115 }
1116
1117 wm_components: COMPONENT
1118 {
1119 $$.writemask = 1 << $1;
1120 $$.last = $1;
1121 $$.idx = 1;
1122 }
1123 | wm_components COMPONENT
1124 {
1125 if($1.writemask == SWIZZLE_ERR || $1.idx == 4)
1126 /* Wrong writemask */
1127 $$.writemask = SWIZZLE_ERR;
1128 else {
1129 if($2 <= $1.last)
1130 $$.writemask = SWIZZLE_ERR;
1131 else {
1132 $$.writemask = $1.writemask | (1 << $2);
1133 $$.idx = $1.idx + 1;
1134 }
1135 }
1136 }
1137
1138 swizzle: /* empty */
1139 {
1140 $$ = BWRITERVS_NOSWIZZLE;
1141 TRACE("Default swizzle: %08x\n", $$);
1142 }
1143 | '.' sw_components
1144 {
1145 if($2.swizzle == SWIZZLE_ERR) {
1146 asmparser_message(&asm_ctx, "Line %u: Invalid swizzle\n",
1147 asm_ctx.line_no);
1148 set_parse_status(&asm_ctx.status, PARSE_ERR);
1149 /* Provide a correct swizzle to prevent following complaints */
1150 $$ = BWRITERVS_NOSWIZZLE;
1151 }
1152 else {
1153 uint32_t last, i;
1154
1155 $$ = $2.swizzle;
1156 /* Fill the swizzle by extending the last component */
1157 last = ($2.swizzle >> 2 * ($2.idx - 1)) & 0x03;
1158 for(i = $2.idx; i < 4; i++){
1159 $$ |= last << (2 * i);
1160 }
1161 TRACE("Got a swizzle: %08x\n", $$);
1162 }
1163 }
1164
1165 sw_components: COMPONENT
1166 {
1167 $$.swizzle = $1;
1168 $$.idx = 1;
1169 }
1170 | sw_components COMPONENT
1171 {
1172 if($1.idx == 4) {
1173 /* Too many sw_components */
1174 $$.swizzle = SWIZZLE_ERR;
1175 $$.idx = 4;
1176 }
1177 else {
1178 $$.swizzle = $1.swizzle | ($2 << 2 * $1.idx);
1179 $$.idx = $1.idx + 1;
1180 }
1181 }
1182
1183 omods: /* Empty */
1184 {
1185 $$.mod = 0;
1186 $$.shift = 0;
1187 }
1188 | omods omodifier
1189 {
1190 $$.mod = $1.mod | $2.mod;
1191 if($1.shift && $2.shift) {
1192 asmparser_message(&asm_ctx, "Line %u: More than one shift flag\n",
1193 asm_ctx.line_no);
1194 set_parse_status(&asm_ctx.status, PARSE_ERR);
1195 $$.shift = $1.shift;
1196 } else {
1197 $$.shift = $1.shift | $2.shift;
1198 }
1199 }
1200
1201 omodifier: SHIFT_X2
1202 {
1203 $$.mod = 0;
1204 $$.shift = 1;
1205 }
1206 | SHIFT_X4
1207 {
1208 $$.mod = 0;
1209 $$.shift = 2;
1210 }
1211 | SHIFT_X8
1212 {
1213 $$.mod = 0;
1214 $$.shift = 3;
1215 }
1216 | SHIFT_D2
1217 {
1218 $$.mod = 0;
1219 $$.shift = 15;
1220 }
1221 | SHIFT_D4
1222 {
1223 $$.mod = 0;
1224 $$.shift = 14;
1225 }
1226 | SHIFT_D8
1227 {
1228 $$.mod = 0;
1229 $$.shift = 13;
1230 }
1231 | MOD_SAT
1232 {
1233 $$.mod = BWRITERSPDM_SATURATE;
1234 $$.shift = 0;
1235 }
1236 | MOD_PP
1237 {
1238 $$.mod = BWRITERSPDM_PARTIALPRECISION;
1239 $$.shift = 0;
1240 }
1241 | MOD_CENTROID
1242 {
1243 $$.mod = BWRITERSPDM_MSAMPCENTROID;
1244 $$.shift = 0;
1245 }
1246
1247 sregs: sreg
1248 {
1249 $$.reg[0] = $1;
1250 $$.count = 1;
1251 }
1252 | sregs ',' sreg
1253 {
1254 if($$.count == MAX_SRC_REGS){
1255 asmparser_message(&asm_ctx, "Line %u: Too many source registers in this instruction\n",
1256 asm_ctx.line_no);
1257 set_parse_status(&asm_ctx.status, PARSE_ERR);
1258 }
1259 else
1260 $$.reg[$$.count++] = $3;
1261 }
1262
1263 sreg: sreg_name rel_reg swizzle
1264 {
1265 $$.type = $1.type;
1266 $$.regnum = $1.regnum;
1267 $$.swizzle = $3;
1268 $$.srcmod = BWRITERSPSM_NONE;
1269 set_rel_reg(&$$, &$2);
1270 }
1271 | sreg_name rel_reg smod swizzle
1272 {
1273 $$.type = $1.type;
1274 $$.regnum = $1.regnum;
1275 set_rel_reg(&$$, &$2);
1276 $$.srcmod = $3;
1277 $$.swizzle = $4;
1278 }
1279 | '-' sreg_name rel_reg swizzle
1280 {
1281 $$.type = $2.type;
1282 $$.regnum = $2.regnum;
1283 $$.srcmod = BWRITERSPSM_NEG;
1284 set_rel_reg(&$$, &$3);
1285 $$.swizzle = $4;
1286 }
1287 | '-' sreg_name rel_reg smod swizzle
1288 {
1289 $$.type = $2.type;
1290 $$.regnum = $2.regnum;
1291 set_rel_reg(&$$, &$3);
1292 switch($4) {
1293 case BWRITERSPSM_BIAS: $$.srcmod = BWRITERSPSM_BIASNEG; break;
1294 case BWRITERSPSM_X2: $$.srcmod = BWRITERSPSM_X2NEG; break;
1295 case BWRITERSPSM_SIGN: $$.srcmod = BWRITERSPSM_SIGNNEG; break;
1296 case BWRITERSPSM_ABS: $$.srcmod = BWRITERSPSM_ABSNEG; break;
1297 case BWRITERSPSM_DZ:
1298 asmparser_message(&asm_ctx, "Line %u: Incompatible source modifiers: NEG and DZ\n",
1299 asm_ctx.line_no);
1300 set_parse_status(&asm_ctx.status, PARSE_ERR);
1301 break;
1302 case BWRITERSPSM_DW:
1303 asmparser_message(&asm_ctx, "Line %u: Incompatible source modifiers: NEG and DW\n",
1304 asm_ctx.line_no);
1305 set_parse_status(&asm_ctx.status, PARSE_ERR);
1306 break;
1307 default:
1308 FIXME("Unhandled combination of NEGATE and %u\n", $4);
1309 }
1310 $$.swizzle = $5;
1311 }
1312 | IMMVAL '-' sreg_name rel_reg swizzle
1313 {
1314 if($1.val != 1.0 || (!$1.integer)) {
1315 asmparser_message(&asm_ctx, "Line %u: Only \"1 - reg\" is valid for D3DSPSM_COMP, "
1316 "%g - reg found\n", asm_ctx.line_no, $1.val);
1317 set_parse_status(&asm_ctx.status, PARSE_ERR);
1318 }
1319 /* Complement - not compatible with other source modifiers */
1320 $$.type = $3.type;
1321 $$.regnum = $3.regnum;
1322 $$.srcmod = BWRITERSPSM_COMP;
1323 set_rel_reg(&$$, &$4);
1324 $$.swizzle = $5;
1325 }
1326 | IMMVAL '-' sreg_name rel_reg smod swizzle
1327 {
1328 /* For nicer error reporting */
1329 if($1.val != 1.0 || (!$1.integer)) {
1330 asmparser_message(&asm_ctx, "Line %u: Only \"1 - reg\" is valid for D3DSPSM_COMP\n",
1331 asm_ctx.line_no);
1332 set_parse_status(&asm_ctx.status, PARSE_ERR);
1333 } else {
1334 asmparser_message(&asm_ctx, "Line %u: Incompatible source modifiers: D3DSPSM_COMP and %s\n",
1335 asm_ctx.line_no,
1336 debug_print_srcmod($5));
1337 set_parse_status(&asm_ctx.status, PARSE_ERR);
1338 }
1339 }
1340 | SMOD_NOT sreg_name swizzle
1341 {
1342 $$.type = $2.type;
1343 $$.regnum = $2.regnum;
1344 $$.rel_reg = NULL;
1345 $$.srcmod = BWRITERSPSM_NOT;
1346 $$.swizzle = $3;
1347 }
1348
1349 rel_reg: /* empty */
1350 {
1351 $$.has_rel_reg = FALSE;
1352 $$.additional_offset = 0;
1353 }
1354 | '[' immsum ']'
1355 {
1356 $$.has_rel_reg = FALSE;
1357 $$.additional_offset = $2.val;
1358 }
1359 | '[' relreg_name swizzle ']'
1360 {
1361 $$.has_rel_reg = TRUE;
1362 $$.type = $2.type;
1363 $$.additional_offset = 0;
1364 $$.rel_regnum = $2.regnum;
1365 $$.swizzle = $3;
1366 }
1367 | '[' immsum '+' relreg_name swizzle ']'
1368 {
1369 $$.has_rel_reg = TRUE;
1370 $$.type = $4.type;
1371 $$.additional_offset = $2.val;
1372 $$.rel_regnum = $4.regnum;
1373 $$.swizzle = $5;
1374 }
1375 | '[' relreg_name swizzle '+' immsum ']'
1376 {
1377 $$.has_rel_reg = TRUE;
1378 $$.type = $2.type;
1379 $$.additional_offset = $5.val;
1380 $$.rel_regnum = $2.regnum;
1381 $$.swizzle = $3;
1382 }
1383 | '[' immsum '+' relreg_name swizzle '+' immsum ']'
1384 {
1385 $$.has_rel_reg = TRUE;
1386 $$.type = $4.type;
1387 $$.additional_offset = $2.val + $7.val;
1388 $$.rel_regnum = $4.regnum;
1389 $$.swizzle = $5;
1390 }
1391
1392 immsum: signed_integer
1393 | immsum '+' signed_integer
1394 {
1395 $$.val = $1.val + $3.val;
1396 }
1397 | immsum '-' signed_integer
1398 {
1399 $$.val = $1.val - $3.val;
1400 }
1401
1402 signed_integer:
1403 IMMVAL
1404 {
1405 if (!$1.integer)
1406 {
1407 asmparser_message(&asm_ctx, "Line %u: Unexpected float %f\n",
1408 asm_ctx.line_no, $1.val);
1409 set_parse_status(&asm_ctx.status, PARSE_ERR);
1410 }
1411 $$.val = $1.val;
1412 }
1413 | '-' IMMVAL
1414 {
1415 if (!$2.integer)
1416 {
1417 asmparser_message(&asm_ctx, "Line %u: Unexpected float %f\n",
1418 asm_ctx.line_no, $2.val);
1419 set_parse_status(&asm_ctx.status, PARSE_ERR);
1420 }
1421 $$.val = -$2.val;
1422 }
1423
1424 signed_float:
1425 IMMVAL
1426 {
1427 $$.val = $1.val;
1428 }
1429 | '-' IMMVAL
1430 {
1431 $$.val = -$2.val;
1432 }
1433
1434 smod: SMOD_BIAS
1435 {
1436 $$ = BWRITERSPSM_BIAS;
1437 }
1438 | SHIFT_X2
1439 {
1440 $$ = BWRITERSPSM_X2;
1441 }
1442 | SMOD_SCALEBIAS
1443 {
1444 $$ = BWRITERSPSM_SIGN;
1445 }
1446 | SMOD_DZ
1447 {
1448 $$ = BWRITERSPSM_DZ;
1449 }
1450 | SMOD_DW
1451 {
1452 $$ = BWRITERSPSM_DW;
1453 }
1454 | SMOD_ABS
1455 {
1456 $$ = BWRITERSPSM_ABS;
1457 }
1458
1459 relreg_name: REG_ADDRESS
1460 {
1461 $$.regnum = 0; $$.type = BWRITERSPR_ADDR;
1462 }
1463 | REG_LOOP
1464 {
1465 $$.regnum = 0; $$.type = BWRITERSPR_LOOP;
1466 }
1467
1468 sreg_name: REG_TEMP
1469 {
1470 $$.regnum = $1; $$.type = BWRITERSPR_TEMP;
1471 }
1472 | REG_OUTPUT
1473 {
1474 asmparser_message(&asm_ctx, "Line %u: Register o%u is not a valid source register\n",
1475 asm_ctx.line_no, $1);
1476 set_parse_status(&asm_ctx.status, PARSE_WARN);
1477 }
1478 | REG_INPUT
1479 {
1480 $$.regnum = $1; $$.type = BWRITERSPR_INPUT;
1481 }
1482 | REG_CONSTFLOAT
1483 {
1484 $$.regnum = $1; $$.type = BWRITERSPR_CONST;
1485 }
1486 | REG_CONSTINT
1487 {
1488 $$.regnum = $1; $$.type = BWRITERSPR_CONSTINT;
1489 }
1490 | REG_CONSTBOOL
1491 {
1492 $$.regnum = $1; $$.type = BWRITERSPR_CONSTBOOL;
1493 }
1494 | REG_TEXTURE
1495 {
1496 $$.regnum = $1; $$.type = BWRITERSPR_TEXTURE;
1497 }
1498 | REG_TEXCRDOUT
1499 {
1500 asmparser_message(&asm_ctx, "Line %u: Register oT%u is not a valid source register\n",
1501 asm_ctx.line_no, $1);
1502 set_parse_status(&asm_ctx.status, PARSE_WARN);
1503 }
1504 | REG_SAMPLER
1505 {
1506 $$.regnum = $1; $$.type = BWRITERSPR_SAMPLER;
1507 }
1508 | REG_OPOS
1509 {
1510 asmparser_message(&asm_ctx, "Line %u: Register oPos is not a valid source register\n",
1511 asm_ctx.line_no);
1512 set_parse_status(&asm_ctx.status, PARSE_WARN);
1513 }
1514 | REG_OFOG
1515 {
1516 asmparser_message(&asm_ctx, "Line %u: Register oFog is not a valid source register\n",
1517 asm_ctx.line_no);
1518 set_parse_status(&asm_ctx.status, PARSE_WARN);
1519 }
1520 | REG_VERTEXCOLOR
1521 {
1522 asmparser_message(&asm_ctx, "Line %u: Register oD%u is not a valid source register\n",
1523 asm_ctx.line_no, $1);
1524 set_parse_status(&asm_ctx.status, PARSE_WARN);
1525 }
1526 | REG_FRAGCOLOR
1527 {
1528 asmparser_message(&asm_ctx, "Line %u: Register oC%u is not a valid source register\n",
1529 asm_ctx.line_no, $1);
1530 set_parse_status(&asm_ctx.status, PARSE_WARN);
1531 }
1532 | REG_FRAGDEPTH
1533 {
1534 asmparser_message(&asm_ctx, "Line %u: Register oDepth is not a valid source register\n",
1535 asm_ctx.line_no);
1536 set_parse_status(&asm_ctx.status, PARSE_WARN);
1537 }
1538 | REG_PREDICATE
1539 {
1540 $$.regnum = 0; $$.type = BWRITERSPR_PREDICATE;
1541 }
1542 | REG_VPOS
1543 {
1544 $$.regnum = 0; $$.type = BWRITERSPR_MISCTYPE;
1545 }
1546 | REG_VFACE
1547 {
1548 $$.regnum = 1; $$.type = BWRITERSPR_MISCTYPE;
1549 }
1550 | REG_ADDRESS
1551 {
1552 $$.regnum = 0; $$.type = BWRITERSPR_ADDR;
1553 }
1554 | REG_LOOP
1555 {
1556 $$.regnum = 0; $$.type = BWRITERSPR_LOOP;
1557 }
1558 | REG_LABEL
1559 {
1560 $$.regnum = $1; $$.type = BWRITERSPR_LABEL;
1561 }
1562
1563 comp: COMP_GT { $$ = BWRITER_COMPARISON_GT; }
1564 | COMP_LT { $$ = BWRITER_COMPARISON_LT; }
1565 | COMP_GE { $$ = BWRITER_COMPARISON_GE; }
1566 | COMP_LE { $$ = BWRITER_COMPARISON_LE; }
1567 | COMP_EQ { $$ = BWRITER_COMPARISON_EQ; }
1568 | COMP_NE { $$ = BWRITER_COMPARISON_NE; }
1569
1570 dclusage: USAGE_POSITION
1571 {
1572 TRACE("dcl_position%u\n", $1);
1573 $$.regnum = $1;
1574 $$.dclusage = BWRITERDECLUSAGE_POSITION;
1575 }
1576 | USAGE_BLENDWEIGHT
1577 {
1578 TRACE("dcl_blendweight%u\n", $1);
1579 $$.regnum = $1;
1580 $$.dclusage = BWRITERDECLUSAGE_BLENDWEIGHT;
1581 }
1582 | USAGE_BLENDINDICES
1583 {
1584 TRACE("dcl_blendindices%u\n", $1);
1585 $$.regnum = $1;
1586 $$.dclusage = BWRITERDECLUSAGE_BLENDINDICES;
1587 }
1588 | USAGE_NORMAL
1589 {
1590 TRACE("dcl_normal%u\n", $1);
1591 $$.regnum = $1;
1592 $$.dclusage = BWRITERDECLUSAGE_NORMAL;
1593 }
1594 | USAGE_PSIZE
1595 {
1596 TRACE("dcl_psize%u\n", $1);
1597 $$.regnum = $1;
1598 $$.dclusage = BWRITERDECLUSAGE_PSIZE;
1599 }
1600 | USAGE_TEXCOORD
1601 {
1602 TRACE("dcl_texcoord%u\n", $1);
1603 $$.regnum = $1;
1604 $$.dclusage = BWRITERDECLUSAGE_TEXCOORD;
1605 }
1606 | USAGE_TANGENT
1607 {
1608 TRACE("dcl_tangent%u\n", $1);
1609 $$.regnum = $1;
1610 $$.dclusage = BWRITERDECLUSAGE_TANGENT;
1611 }
1612 | USAGE_BINORMAL
1613 {
1614 TRACE("dcl_binormal%u\n", $1);
1615 $$.regnum = $1;
1616 $$.dclusage = BWRITERDECLUSAGE_BINORMAL;
1617 }
1618 | USAGE_TESSFACTOR
1619 {
1620 TRACE("dcl_tessfactor%u\n", $1);
1621 $$.regnum = $1;
1622 $$.dclusage = BWRITERDECLUSAGE_TESSFACTOR;
1623 }
1624 | USAGE_POSITIONT
1625 {
1626 TRACE("dcl_positiont%u\n", $1);
1627 $$.regnum = $1;
1628 $$.dclusage = BWRITERDECLUSAGE_POSITIONT;
1629 }
1630 | USAGE_COLOR
1631 {
1632 TRACE("dcl_color%u\n", $1);
1633 $$.regnum = $1;
1634 $$.dclusage = BWRITERDECLUSAGE_COLOR;
1635 }
1636 | USAGE_FOG
1637 {
1638 TRACE("dcl_fog%u\n", $1);
1639 $$.regnum = $1;
1640 $$.dclusage = BWRITERDECLUSAGE_FOG;
1641 }
1642 | USAGE_DEPTH
1643 {
1644 TRACE("dcl_depth%u\n", $1);
1645 $$.regnum = $1;
1646 $$.dclusage = BWRITERDECLUSAGE_DEPTH;
1647 }
1648 | USAGE_SAMPLE
1649 {
1650 TRACE("dcl_sample%u\n", $1);
1651 $$.regnum = $1;
1652 $$.dclusage = BWRITERDECLUSAGE_SAMPLE;
1653 }
1654
1655 dcl_inputreg: REG_INPUT
1656 {
1657 $$.regnum = $1; $$.type = BWRITERSPR_INPUT;
1658 }
1659 | REG_TEXTURE
1660 {
1661 $$.regnum = $1; $$.type = BWRITERSPR_TEXTURE;
1662 }
1663
1664 sampdcl: SAMPTYPE_1D
1665 {
1666 $$ = BWRITERSTT_1D;
1667 }
1668 | SAMPTYPE_2D
1669 {
1670 $$ = BWRITERSTT_2D;
1671 }
1672 | SAMPTYPE_CUBE
1673 {
1674 $$ = BWRITERSTT_CUBE;
1675 }
1676 | SAMPTYPE_VOLUME
1677 {
1678 $$ = BWRITERSTT_VOLUME;
1679 }
1680
1681 predicate: '(' REG_PREDICATE swizzle ')'
1682 {
1683 $$.type = BWRITERSPR_PREDICATE;
1684 $$.regnum = 0;
1685 $$.rel_reg = NULL;
1686 $$.srcmod = BWRITERSPSM_NONE;
1687 $$.swizzle = $3;
1688 }
1689 | '(' SMOD_NOT REG_PREDICATE swizzle ')'
1690 {
1691 $$.type = BWRITERSPR_PREDICATE;
1692 $$.regnum = 0;
1693 $$.rel_reg = NULL;
1694 $$.srcmod = BWRITERSPSM_NOT;
1695 $$.swizzle = $4;
1696 }
1697
1698 %%
1699
1700 struct bwriter_shader *parse_asm_shader(char **messages)
1701 {
1702 struct bwriter_shader *ret = NULL;
1703
1704 asm_ctx.shader = NULL;
1705 asm_ctx.status = PARSE_SUCCESS;
1706 asm_ctx.messages.size = asm_ctx.messages.capacity = 0;
1707 asm_ctx.line_no = 1;
1708
1709 asmshader_parse();
1710
1711 if (asm_ctx.status != PARSE_ERR)
1712 ret = asm_ctx.shader;
1713 else if (asm_ctx.shader)
1714 SlDeleteShader(asm_ctx.shader);
1715
1716 if (messages)
1717 {
1718 if (asm_ctx.messages.size)
1719 {
1720 /* Shrink the buffer to the used size */
1721 *messages = d3dcompiler_realloc(asm_ctx.messages.string, asm_ctx.messages.size + 1);
1722 if (!*messages)
1723 {
1724 ERR("Out of memory, no messages reported\n");
1725 d3dcompiler_free(asm_ctx.messages.string);
1726 }
1727 }
1728 else
1729 {
1730 *messages = NULL;
1731 }
1732 }
1733 else
1734 {
1735 if (asm_ctx.messages.capacity)
1736 d3dcompiler_free(asm_ctx.messages.string);
1737 }
1738
1739 return ret;
1740 }
Windows API implementation