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winedbg: Add hint operators to Thumb2 disassembler.
[wine.git] / programs / winedbg / be_arm.c
blob37b3a5bd59131c84425140d7e8fbbdbb9bdf6164
1 /*
2 * Debugger ARM specific functions
3 *
4 * Copyright 2000-2003 Marcus Meissner
5 * 2004 Eric Pouech
6 * 2010-2012 André Hentschel
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2.1 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
21 */
22
23 #include "debugger.h"
24
25 #if defined(__arm__) && !defined(__ARMEB__)
26
27 /*
28 * Switch to disassemble Thumb code.
29 */
30 static BOOL db_disasm_thumb = FALSE;
31
32 /*
33 * Flag to indicate whether we need to display instruction,
34 * or whether we just need to know the address of the next
35 * instruction.
36 */
37 static BOOL db_display = FALSE;
38
39 #define ARM_INSN_SIZE 4
40 #define THUMB_INSN_SIZE 2
41 #define THUMB2_INSN_SIZE 4
42
43 #define ROR32(n, r) (((n) >> (r)) | ((n) << (32 - (r))))
44
45 #define get_cond(ins) tbl_cond[(ins >> 28) & 0x0f]
46 #define get_nibble(ins, num) ((ins >> (num * 4)) & 0x0f)
47
48 static char const tbl_regs[][4] = {
49 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
50 "fp", "ip", "sp", "lr", "pc", "cpsr"
51 };
52
53 static char const tbl_addrmode[][3] = {
54 "da", "ia", "db", "ib"
55 };
56
57 static char const tbl_cond[][3] = {
58 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "", ""
59 };
60
61 static char const tbl_dataops[][4] = {
62 "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", "tst", "teq", "cmp", "cmn", "orr",
63 "mov", "bic", "mvn"
64 };
65
66 static char const tbl_shifts[][4] = {
67 "lsl", "lsr", "asr", "ror"
68 };
69
70 static char const tbl_hiops_t[][4] = {
71 "add", "cmp", "mov", "bx"
72 };
73
74 static char const tbl_aluops_t[][4] = {
75 "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", "tst", "neg", "cmp", "cmn", "orr",
76 "mul", "bic", "mvn"
77 };
78
79 static char const tbl_immops_t[][4] = {
80 "mov", "cmp", "add", "sub"
81 };
82
83 static char const tbl_sregops_t[][5] = {
84 "strh", "ldsb", "ldrh", "ldsh"
85 };
86
87 static char const tbl_miscops_t2[][6] = {
88 "rev", "rev16", "rbit", "revsh"
89 };
90
91 static char const tbl_width_t2[][2] = {
92 "b", "h", "", "?"
93 };
94
95 static char const tbl_special_regs_t2[][12] = {
96 "apsr", "iapsr", "eapsr", "xpsr", "rsvd", "ipsr", "epsr", "iepsr", "msp", "psp", "rsvd", "rsvd",
97 "rsvd", "rsvd", "rsvd", "rsvd", "primask", "basepri", "basepri_max", "faultmask", "control"
98 };
99
100 static char const tbl_hints_t2[][6] = {
101 "nop", "yield", "wfe", "wfi", "sev"
102 };
103
104 static UINT db_get_inst(void* addr, int size)
105 {
106 UINT result = 0;
107 char buffer[4];
108
109 if (dbg_read_memory(addr, buffer, size))
110 {
111 switch (size)
112 {
113 case 4:
114 result = *(UINT*)buffer;
115 break;
116 case 2:
117 result = *(WORD*)buffer;
118 break;
119 }
120 }
121 return result;
122 }
123
124 static void db_printsym(unsigned int addr)
125 {
126 ADDRESS64 a;
127
128 a.Mode = AddrModeFlat;
129 a.Offset = addr;
130
131 print_address(&a, TRUE);
132 }
133
134 static UINT arm_disasm_branch(UINT inst, ADDRESS64 *addr)
135 {
136 short link = (inst >> 24) & 0x01;
137 int offset = (inst << 2) & 0x03ffffff;
138
139 if (offset & 0x02000000) offset |= 0xfc000000;
140 offset += 8;
141
142 dbg_printf("\n\tb%s%s\t", link ? "l" : "", get_cond(inst));
143 db_printsym(addr->Offset + offset);
144 return 0;
145 }
146
147 static UINT arm_disasm_mul(UINT inst, ADDRESS64 *addr)
148 {
149 short accu = (inst >> 21) & 0x01;
150 short condcodes = (inst >> 20) & 0x01;
151
152 if (accu)
153 dbg_printf("\n\tmla%s%s\t%s, %s, %s, %s", get_cond(inst), condcodes ? "s" : "",
154 tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
155 tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 3)]);
156 else
157 dbg_printf("\n\tmul%s%s\t%s, %s, %s", get_cond(inst), condcodes ? "s" : "",
158 tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
159 tbl_regs[get_nibble(inst, 2)]);
160 return 0;
161 }
162
163 static UINT arm_disasm_longmul(UINT inst, ADDRESS64 *addr)
164 {
165 short sign = (inst >> 22) & 0x01;
166 short accu = (inst >> 21) & 0x01;
167 short condcodes = (inst >> 20) & 0x01;
168
169 dbg_printf("\n\t%s%s%s%s\t%s, %s, %s, %s", sign ? "s" : "u", accu ? "mlal" : "mull",
170 get_cond(inst), condcodes ? "s" : "",
171 tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)],
172 tbl_regs[get_nibble(inst, 0)], tbl_regs[get_nibble(inst, 2)]);
173 return 0;
174 }
175
176 static UINT arm_disasm_swp(UINT inst, ADDRESS64 *addr)
177 {
178 short byte = (inst >> 22) & 0x01;
179
180 dbg_printf("\n\tswp%s%s\t%s, %s, [%s]", get_cond(inst), byte ? "b" : "",
181 tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 0)],
182 tbl_regs[get_nibble(inst, 4)]);
183 return 0;
184 }
185
186 static UINT arm_disasm_branchreg(UINT inst, ADDRESS64 *addr)
187 {
188 dbg_printf("\n\tb%s\t%s", get_cond(inst), tbl_regs[get_nibble(inst, 0)]);
189 return 0;
190 }
191
192 static UINT arm_disasm_branchxchg(UINT inst, ADDRESS64 *addr)
193 {
194 dbg_printf("\n\tbx%s\t%s", get_cond(inst), tbl_regs[get_nibble(inst, 0)]);
195 return 0;
196 }
197
198 static UINT arm_disasm_mrstrans(UINT inst, ADDRESS64 *addr)
199 {
200 short src = (inst >> 22) & 0x01;
201
202 dbg_printf("\n\tmrs%s\t%s, %s", get_cond(inst), tbl_regs[get_nibble(inst, 3)],
203 src ? "spsr" : "cpsr");
204 return 0;
205 }
206
207 static UINT arm_disasm_msrtrans(UINT inst, ADDRESS64 *addr)
208 {
209 short immediate = (inst >> 25) & 0x01;
210 short dst = (inst >> 22) & 0x01;
211 short simple = (inst >> 16) & 0x01;
212
213 if (simple || !immediate)
214 {
215 dbg_printf("\n\tmsr%s\t%s, %s", get_cond(inst), dst ? "spsr" : "cpsr",
216 tbl_regs[get_nibble(inst, 0)]);
217 return 0;
218 }
219
220 dbg_printf("\n\tmsr%s\t%s, #%u", get_cond(inst), dst ? "spsr" : "cpsr",
221 ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
222 return 0;
223 }
224
225 static UINT arm_disasm_wordmov(UINT inst, ADDRESS64 *addr)
226 {
227 short top = (inst >> 22) & 0x01;
228
229 dbg_printf("\n\tmov%s%s\t%s, #%u", top ? "t" : "w", get_cond(inst),
230 tbl_regs[get_nibble(inst, 3)], (get_nibble(inst, 4) << 12) | (inst & 0x0fff));
231 return 0;
232 }
233
234 static UINT arm_disasm_nop(UINT inst, ADDRESS64 *addr)
235 {
236 dbg_printf("\n\tnop%s", get_cond(inst));
237 return 0;
238 }
239
240 static UINT arm_disasm_dataprocessing(UINT inst, ADDRESS64 *addr)
241 {
242 short condcodes = (inst >> 20) & 0x01;
243 short opcode = (inst >> 21) & 0x0f;
244 short immediate = (inst >> 25) & 0x01;
245 short no_op1 = (opcode & 0x0d) == 0x0d;
246 short no_dst = (opcode & 0x0c) == 0x08;
247
248 dbg_printf("\n\t%s%s%s", tbl_dataops[opcode], condcodes ? "s" : "", get_cond(inst));
249 if (!no_dst) dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
250 else dbg_printf("\t");
251
252 if (no_op1)
253 {
254 if (immediate)
255 dbg_printf("#%u", ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
256 else
257 dbg_printf("%s", tbl_regs[get_nibble(inst, 0)]);
258 }
259 else
260 {
261 if (immediate)
262 dbg_printf("%s, #%u", tbl_regs[get_nibble(inst, 4)],
263 ROR32(inst & 0xff, 2 * get_nibble(inst, 2)));
264 else if (((inst >> 4) & 0xff) == 0x00) /* no shift */
265 dbg_printf("%s, %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
266 else if (((inst >> 4) & 0x09) == 0x01) /* register shift */
267 dbg_printf("%s, %s, %s %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
268 tbl_shifts[(inst >> 5) & 0x03], tbl_regs[(inst >> 8) & 0x0f]);
269 else if (((inst >> 4) & 0x01) == 0x00) /* immediate shift */
270 dbg_printf("%s, %s, %s #%d", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
271 tbl_shifts[(inst >> 5) & 0x03], (inst >> 7) & 0x1f);
272 else
273 return inst;
274 }
275 return 0;
276 }
277
278 static UINT arm_disasm_singletrans(UINT inst, ADDRESS64 *addr)
279 {
280 short load = (inst >> 20) & 0x01;
281 short writeback = (inst >> 21) & 0x01;
282 short byte = (inst >> 22) & 0x01;
283 short direction = (inst >> 23) & 0x01;
284 short indexing = (inst >> 24) & 0x01;
285 short immediate = !((inst >> 25) & 0x01);
286 short offset = inst & 0x0fff;
287
288 if (!direction) offset *= -1;
289
290 dbg_printf("\n\t%s%s%s%s", load ? "ldr" : "str", byte ? "b" : "", writeback ? "t" : "",
291 get_cond(inst));
292 dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
293 if (indexing)
294 {
295 if (immediate)
296 dbg_printf("[%s, #%d]", tbl_regs[get_nibble(inst, 4)], offset);
297 else if (((inst >> 4) & 0xff) == 0x00) /* no shift */
298 dbg_printf("[%s, %s]", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
299 else if (((inst >> 4) & 0x01) == 0x00) /* immediate shift (there's no register shift) */
300 dbg_printf("[%s, %s, %s #%d]", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
301 tbl_shifts[(inst >> 5) & 0x03], (inst >> 7) & 0x1f);
302 else
303 return inst;
304 }
305 else
306 {
307 if (immediate)
308 dbg_printf("[%s], #%d", tbl_regs[get_nibble(inst, 4)], offset);
309 else if (((inst >> 4) & 0xff) == 0x00) /* no shift */
310 dbg_printf("[%s], %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
311 else if (((inst >> 4) & 0x01) == 0x00) /* immediate shift (there's no register shift) */
312 dbg_printf("[%s], %s, %s #%d", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)],
313 tbl_shifts[(inst >> 5) & 0x03], (inst >> 7) & 0x1f);
314 else
315 return inst;
316 }
317 return 0;
318 }
319
320 static UINT arm_disasm_halfwordtrans(UINT inst, ADDRESS64 *addr)
321 {
322 short halfword = (inst >> 5) & 0x01;
323 short sign = (inst >> 6) & 0x01;
324 short load = (inst >> 20) & 0x01;
325 short writeback = (inst >> 21) & 0x01;
326 short immediate = (inst >> 22) & 0x01;
327 short direction = (inst >> 23) & 0x01;
328 short indexing = (inst >> 24) & 0x01;
329 short offset = ((inst >> 4) & 0xf0) + (inst & 0x0f);
330
331 if (!direction) offset *= -1;
332
333 dbg_printf("\n\t%s%s%s%s%s", load ? "ldr" : "str", sign ? "s" : "",
334 halfword ? "h" : (sign ? "b" : ""), writeback ? "t" : "", get_cond(inst));
335 dbg_printf("\t%s, ", tbl_regs[get_nibble(inst, 3)]);
336 if (indexing)
337 {
338 if (immediate)
339 dbg_printf("[%s, #%d]", tbl_regs[get_nibble(inst, 4)], offset);
340 else
341 dbg_printf("[%s, %s]", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
342 }
343 else
344 {
345 if (immediate)
346 dbg_printf("[%s], #%d", tbl_regs[get_nibble(inst, 4)], offset);
347 else
348 dbg_printf("[%s], %s", tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
349 }
350 return 0;
351 }
352
353 static UINT arm_disasm_blocktrans(UINT inst, ADDRESS64 *addr)
354 {
355 short load = (inst >> 20) & 0x01;
356 short writeback = (inst >> 21) & 0x01;
357 short psr = (inst >> 22) & 0x01;
358 short addrmode = (inst >> 23) & 0x03;
359 short i;
360 short last=15;
361 for (i=15;i>=0;i--)
362 if ((inst>>i) & 1)
363 {
364 last = i;
365 break;
366 }
367
368 dbg_printf("\n\t%s%s%s\t%s%s, {", load ? "ldm" : "stm", tbl_addrmode[addrmode], get_cond(inst),
369 tbl_regs[get_nibble(inst, 4)], writeback ? "!" : "");
370 for (i=0;i<=15;i++)
371 if ((inst>>i) & 1)
372 {
373 if (i == last) dbg_printf("%s", tbl_regs[i]);
374 else dbg_printf("%s, ", tbl_regs[i]);
375 }
376 dbg_printf("}%s", psr ? "^" : "");
377 return 0;
378 }
379
380 static UINT arm_disasm_swi(UINT inst, ADDRESS64 *addr)
381 {
382 UINT comment = inst & 0x00ffffff;
383 dbg_printf("\n\tswi%s\t#%d", get_cond(inst), comment);
384 return 0;
385 }
386
387 static UINT arm_disasm_coproctrans(UINT inst, ADDRESS64 *addr)
388 {
389 WORD CRm = inst & 0x0f;
390 WORD CP = (inst >> 5) & 0x07;
391 WORD CPnum = (inst >> 8) & 0x0f;
392 WORD CRn = (inst >> 16) & 0x0f;
393 WORD load = (inst >> 20) & 0x01;
394 WORD CP_Opc = (inst >> 21) & 0x07;
395
396 dbg_printf("\n\t%s%s\t%u, %u, %s, cr%u, cr%u, {%u}", load ? "mrc" : "mcr", get_cond(inst), CPnum,
397 CP, tbl_regs[get_nibble(inst, 3)], CRn, CRm, CP_Opc);
398 return 0;
399 }
400
401 static UINT arm_disasm_coprocdataop(UINT inst, ADDRESS64 *addr)
402 {
403 WORD CRm = inst & 0x0f;
404 WORD CP = (inst >> 5) & 0x07;
405 WORD CPnum = (inst >> 8) & 0x0f;
406 WORD CRd = (inst >> 12) & 0x0f;
407 WORD CRn = (inst >> 16) & 0x0f;
408 WORD CP_Opc = (inst >> 20) & 0x0f;
409
410 dbg_printf("\n\tcdp%s\t%u, %u, cr%u, cr%u, cr%u, {%u}", get_cond(inst),
411 CPnum, CP, CRd, CRn, CRm, CP_Opc);
412 return 0;
413 }
414
415 static UINT arm_disasm_coprocdatatrans(UINT inst, ADDRESS64 *addr)
416 {
417 WORD CPnum = (inst >> 8) & 0x0f;
418 WORD CRd = (inst >> 12) & 0x0f;
419 WORD load = (inst >> 20) & 0x01;
420 WORD writeback = (inst >> 21) & 0x01;
421 WORD translen = (inst >> 22) & 0x01;
422 WORD direction = (inst >> 23) & 0x01;
423 WORD indexing = (inst >> 24) & 0x01;
424 short offset = (inst & 0xff) << 2;
425
426 if (!direction) offset *= -1;
427
428 dbg_printf("\n\t%s%s%s", load ? "ldc" : "stc", translen ? "l" : "", get_cond(inst));
429 if (indexing)
430 dbg_printf("\t%u, cr%u, [%s, #%d]%s", CPnum, CRd, tbl_regs[get_nibble(inst, 4)], offset, writeback?"!":"");
431 else
432 dbg_printf("\t%u, cr%u, [%s], #%d", CPnum, CRd, tbl_regs[get_nibble(inst, 4)], offset);
433 return 0;
434 }
435
436 static WORD thumb_disasm_hireg(WORD inst, ADDRESS64 *addr)
437 {
438 short dst = inst & 0x07;
439 short src = (inst >> 3) & 0x07;
440 short h2 = (inst >> 6) & 0x01;
441 short h1 = (inst >> 7) & 0x01;
442 short op = (inst >> 8) & 0x03;
443
444 if (h1) dst += 8;
445 if (h2) src += 8;
446
447 if (op == 2 && dst == src) /* mov rx, rx */
448 {
449 dbg_printf("\n\tnop");
450 return 0;
451 }
452
453 if (op == 3)
454 dbg_printf("\n\tb%sx\t%s", h1?"l":"", tbl_regs[src]);
455 else
456 dbg_printf("\n\t%s\t%s, %s", tbl_hiops_t[op], tbl_regs[dst], tbl_regs[src]);
457
458 return 0;
459 }
460
461 static WORD thumb_disasm_aluop(WORD inst, ADDRESS64 *addr)
462 {
463 short dst = inst & 0x07;
464 short src = (inst >> 3) & 0x07;
465 short op = (inst >> 6) & 0x0f;
466
467 dbg_printf("\n\t%s\t%s, %s", tbl_aluops_t[op], tbl_regs[dst], tbl_regs[src]);
468
469 return 0;
470 }
471
472 static WORD thumb_disasm_pushpop(WORD inst, ADDRESS64 *addr)
473 {
474 short lrpc = (inst >> 8) & 0x01;
475 short load = (inst >> 11) & 0x01;
476 short i;
477 short last;
478
479 for (i=7;i>=0;i--)
480 if ((inst>>i) & 1) break;
481 last = i;
482
483 dbg_printf("\n\t%s\t{", load ? "pop" : "push");
484
485 for (i=0;i<=7;i++)
486 if ((inst>>i) & 1)
487 {
488 if (i == last) dbg_printf("%s", tbl_regs[i]);
489 else dbg_printf("%s, ", tbl_regs[i]);
490 }
491 if (lrpc)
492 dbg_printf("%s%s", last ? ", " : "", load ? "pc" : "lr");
493
494 dbg_printf("}");
495 return 0;
496 }
497
498 static WORD thumb_disasm_blocktrans(WORD inst, ADDRESS64 *addr)
499 {
500 short load = (inst >> 11) & 0x01;
501 short i;
502 short last;
503
504 for (i=7;i>=0;i--)
505 if ((inst>>i) & 1) break;
506 last = i;
507
508 dbg_printf("\n\t%s\t%s!, {", load ? "ldmia" : "stmia", tbl_regs[(inst >> 8) & 0x07]);
509
510 for (i=0;i<=7;i++)
511 if ((inst>>i) & 1)
512 {
513 if (i == last) dbg_printf("%s", tbl_regs[i]);
514 else dbg_printf("%s, ", tbl_regs[i]);
515 }
516
517 dbg_printf("}");
518 return 0;
519 }
520
521 static WORD thumb_disasm_condbranch(WORD inst, ADDRESS64 *addr)
522 {
523 WORD offset = inst & 0x00ff;
524 dbg_printf("\n\tb%s\t", tbl_cond[(inst >> 8) & 0x0f]);
525 db_printsym(addr->Offset + offset);
526 return 0;
527 }
528
529 static WORD thumb_disasm_uncondbranch(WORD inst, ADDRESS64 *addr)
530 {
531 short offset = (inst & 0x07ff) << 1;
532
533 if (offset & 0x0800) offset |= 0xf000;
534 offset += 4;
535
536 dbg_printf("\n\tb\t");
537 db_printsym(addr->Offset + offset);
538 return 0;
539 }
540
541 static WORD thumb_disasm_loadadr(WORD inst, ADDRESS64 *addr)
542 {
543 WORD src = (inst >> 11) & 0x01;
544 WORD offset = (inst & 0xff) << 2;
545
546 dbg_printf("\n\tadd\t%s, %s, #%d", tbl_regs[(inst >> 8) & 0x07], src ? "sp" : "pc", offset);
547 return 0;
548 }
549
550 static WORD thumb_disasm_swi(WORD inst, ADDRESS64 *addr)
551 {
552 WORD comment = inst & 0x00ff;
553 dbg_printf("\n\tswi\t#%d", comment);
554 return 0;
555 }
556
557 static WORD thumb_disasm_nop(WORD inst, ADDRESS64 *addr)
558 {
559 dbg_printf("\n\tnop");
560 return 0;
561 }
562
563 static WORD thumb_disasm_ldrpcrel(WORD inst, ADDRESS64 *addr)
564 {
565 WORD offset = (inst & 0xff) << 2;
566 dbg_printf("\n\tldr\t%s, [pc, #%u]", tbl_regs[(inst >> 8) & 0x07], offset);
567 return 0;
568 }
569
570 static WORD thumb_disasm_ldrsprel(WORD inst, ADDRESS64 *addr)
571 {
572 WORD offset = (inst & 0xff) << 2;
573 dbg_printf("\n\t%s\t%s, [sp, #%u]", (inst & 0x0800)?"ldr":"str", tbl_regs[(inst >> 8) & 0x07], offset);
574 return 0;
575 }
576
577 static WORD thumb_disasm_addsprel(WORD inst, ADDRESS64 *addr)
578 {
579 WORD offset = (inst & 0x7f) << 2;
580 if ((inst >> 7) & 0x01)
581 dbg_printf("\n\tsub\tsp, sp, #%u", offset);
582 else
583 dbg_printf("\n\tadd\tsp, sp, #%u", offset);
584 return 0;
585 }
586
587 static WORD thumb_disasm_ldrimm(WORD inst, ADDRESS64 *addr)
588 {
589 WORD offset = (inst & 0x07c0) >> 6;
590 dbg_printf("\n\t%s%s\t%s, [%s, #%u]", (inst & 0x0800)?"ldr":"str", (inst & 0x1000)?"b":"",
591 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], (inst & 0x1000)?offset:(offset << 2));
592 return 0;
593 }
594
595 static WORD thumb_disasm_ldrhimm(WORD inst, ADDRESS64 *addr)
596 {
597 WORD offset = (inst & 0x07c0) >> 5;
598 dbg_printf("\n\t%s\t%s, [%s, #%u]", (inst & 0x0800)?"ldrh":"strh",
599 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], offset);
600 return 0;
601 }
602
603 static WORD thumb_disasm_ldrreg(WORD inst, ADDRESS64 *addr)
604 {
605 dbg_printf("\n\t%s%s\t%s, [%s, %s]", (inst & 0x0800)?"ldr":"str", (inst & 0x0400)?"b":"",
606 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], tbl_regs[(inst >> 6) & 0x07]);
607 return 0;
608 }
609
610 static WORD thumb_disasm_ldrsreg(WORD inst, ADDRESS64 *addr)
611 {
612 dbg_printf("\n\t%s\t%s, [%s, %s]", tbl_sregops_t[(inst >> 10) & 0x03],
613 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], tbl_regs[(inst >> 6) & 0x07]);
614 return 0;
615 }
616
617 static WORD thumb_disasm_immop(WORD inst, ADDRESS64 *addr)
618 {
619 WORD op = (inst >> 11) & 0x03;
620 dbg_printf("\n\t%s\t%s, #%u", tbl_immops_t[op], tbl_regs[(inst >> 8) & 0x07], inst & 0xff);
621 return 0;
622 }
623
624 static WORD thumb_disasm_addsub(WORD inst, ADDRESS64 *addr)
625 {
626 WORD op = (inst >> 9) & 0x01;
627 WORD immediate = (inst >> 10) & 0x01;
628
629 dbg_printf("\n\t%s\t%s, %s, ", op ? "sub" : "add",
630 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07]);
631 if (immediate)
632 dbg_printf("#%d", (inst >> 6) & 0x07);
633 else
634 dbg_printf("%s", tbl_regs[(inst >> 6) & 0x07]);
635 return 0;
636 }
637
638 static WORD thumb_disasm_movshift(WORD inst, ADDRESS64 *addr)
639 {
640 WORD op = (inst >> 11) & 0x03;
641 dbg_printf("\n\t%s\t%s, %s, #%u", tbl_shifts[op],
642 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], (inst >> 6) & 0x1f);
643 return 0;
644 }
645
646 static UINT thumb2_disasm_branch(UINT inst, ADDRESS64 *addr)
647 {
648 UINT S = (inst >> 26) & 0x01;
649 UINT L = (inst >> 14) & 0x01;
650 UINT I1 = !(((inst >> 13) & 0x01) ^ S);
651 UINT C = !((inst >> 12) & 0x01);
652 UINT I2 = !(((inst >> 11) & 0x01) ^ S);
653 UINT offset = (inst & 0x000007ff) << 1;
654
655 if (C)
656 {
657 offset |= I1 << 19 | I2 << 18 | (inst & 0x003f0000) >> 4;
658 offset += 4;
659 if (S) offset |= 0x0fff << 20;
660 }
661 else
662 {
663 offset |= I1 << 23 | I2 << 22 | (inst & 0x03ff0000) >> 4;
664 offset += 4;
665 if (S) offset |= 0xff << 24;
666 }
667
668 dbg_printf("\n\tb%s%s\t", L ? "l" : "", C ? tbl_cond[(inst >> 22) & 0x0f] : "");
669 db_printsym(addr->Offset + offset);
670 return 0;
671 }
672
673 static UINT thumb2_disasm_srtrans(UINT inst, ADDRESS64 *addr)
674 {
675 UINT fromsr = (inst >> 21) & 0x03;
676 UINT sysreg = inst & 0xff;
677
678 if (fromsr == 3 && get_nibble(inst,4) == 0x0f && sysreg <= 20)
679 {
680 dbg_printf("\n\tmrs\t%s, %s", tbl_regs[get_nibble(inst, 2)], tbl_special_regs_t2[sysreg]);
681 return 0;
682 }
683
684 if (fromsr == 0 && sysreg <= 20)
685 {
686 dbg_printf("\n\tmsr\t%s, %s", tbl_special_regs_t2[sysreg], tbl_regs[get_nibble(inst, 4)]);
687 return 0;
688 }
689
690 return inst;
691 }
692
693 static UINT thumb2_disasm_hint(UINT inst, ADDRESS64 *addr)
694 {
695 WORD op1 = (inst >> 8) & 0x07;
696 WORD op2 = inst & 0xff;
697
698 if (op1) return inst;
699
700 if (op2 <= 4)
701 {
702 dbg_printf("\n\t%s", tbl_hints_t2[op2]);
703 return 0;
704 }
705
706 if (op2 & 0xf0)
707 {
708 dbg_printf("\n\tdbg\t#%u", get_nibble(inst, 0));
709 return 0;
710 }
711
712 return inst;
713 }
714
715 static UINT thumb2_disasm_misc(UINT inst, ADDRESS64 *addr)
716 {
717 WORD op1 = (inst >> 20) & 0x03;
718 WORD op2 = (inst >> 4) & 0x03;
719
720 if (get_nibble(inst, 4) != get_nibble(inst, 0))
721 return inst;
722
723 if (op1 == 3 && op2 == 0)
724 {
725 dbg_printf("\n\tclz\t%s, %s", tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 0)]);
726 return 0;
727 }
728
729 if (op1 == 1)
730 {
731 dbg_printf("\n\t%s\t%s, %s", tbl_miscops_t2[op2], tbl_regs[get_nibble(inst, 2)],
732 tbl_regs[get_nibble(inst, 0)]);
733 return 0;
734 }
735
736 return inst;
737 }
738
739 static UINT thumb2_disasm_dataprocessingreg(UINT inst, ADDRESS64 *addr)
740 {
741 WORD op1 = (inst >> 20) & 0x07;
742 WORD op2 = (inst >> 4) & 0x0f;
743
744 if (!op2)
745 {
746 dbg_printf("\n\t%s%s\t%s, %s, %s", tbl_shifts[op1 >> 1], (op1 & 1)?"s":"",
747 tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 4)],
748 tbl_regs[get_nibble(inst, 0)]);
749 return 0;
750 }
751
752 if ((op2 & 0x0C) == 0x08 && get_nibble(inst, 4) == 0x0f)
753 {
754 dbg_printf("\n\t%sxt%s\t%s, %s", (op1 & 1)?"u":"s", (op1 & 4)?"b":"h",
755 tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 0)]);
756 if (op2 & 0x03)
757 dbg_printf(", ROR #%u", (op2 & 3) * 8);
758 return 0;
759 }
760
761 return inst;
762 }
763
764 static UINT thumb2_disasm_mul(UINT inst, ADDRESS64 *addr)
765 {
766 WORD op1 = (inst >> 20) & 0x07;
767 WORD op2 = (inst >> 4) & 0x03;
768
769 if (op1)
770 return inst;
771
772 if (op2 == 0 && get_nibble(inst, 3) != 0xf)
773 {
774 dbg_printf("\n\tmla\t%s, %s, %s, %s", tbl_regs[get_nibble(inst, 2)],
775 tbl_regs[get_nibble(inst, 4)],
776 tbl_regs[get_nibble(inst, 0)],
777 tbl_regs[get_nibble(inst, 3)]);
778 return 0;
779 }
780
781 if (op2 == 0 && get_nibble(inst, 3) == 0xf)
782 {
783 dbg_printf("\n\tmul\t%s, %s, %s", tbl_regs[get_nibble(inst, 2)],
784 tbl_regs[get_nibble(inst, 4)],
785 tbl_regs[get_nibble(inst, 0)]);
786 return 0;
787 }
788
789 if (op2 == 1)
790 {
791 dbg_printf("\n\tmls\t%s, %s, %s, %s", tbl_regs[get_nibble(inst, 2)],
792 tbl_regs[get_nibble(inst, 4)],
793 tbl_regs[get_nibble(inst, 0)],
794 tbl_regs[get_nibble(inst, 3)]);
795 return 0;
796 }
797
798 return inst;
799 }
800
801 static UINT thumb2_disasm_longmuldiv(UINT inst, ADDRESS64 *addr)
802 {
803 WORD op1 = (inst >> 20) & 0x07;
804 WORD op2 = (inst >> 4) & 0x0f;
805
806 if (op2 == 0)
807 {
808 switch (op1)
809 {
810 case 0:
811 dbg_printf("\n\tsmull\t");
812 break;
813 case 2:
814 dbg_printf("\n\tumull\t");
815 break;
816 case 4:
817 dbg_printf("\n\tsmlal\t");
818 break;
819 case 6:
820 dbg_printf("\n\tumlal\t");
821 break;
822 default:
823 return inst;
824 }
825 dbg_printf("%s, %s, %s, %s", tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 2)],
826 tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)]);
827 return 0;
828 }
829
830 if (op2 == 0xffff)
831 {
832 switch (op1)
833 {
834 case 1:
835 dbg_printf("\n\tsdiv\t");
836 break;
837 case 3:
838 dbg_printf("\n\tudiv\t");
839 break;
840 default:
841 return inst;
842 }
843 dbg_printf("%s, %s, %s", tbl_regs[get_nibble(inst, 2)], tbl_regs[get_nibble(inst, 4)],
844 tbl_regs[get_nibble(inst, 0)]);
845 return 0;
846 }
847
848 return inst;
849 }
850
851 static UINT thumb2_disasm_str(UINT inst, ADDRESS64 *addr)
852 {
853 WORD op1 = (inst >> 21) & 0x07;
854 WORD op2 = (inst >> 6) & 0x3f;
855
856 if ((op1 & 0x03) == 3) return inst;
857
858 if (!(op1 & 0x04) && inst & 0x0800)
859 {
860 int offset;
861 dbg_printf("\n\tstr%s\t%s, [%s", tbl_width_t2[op1 & 0x03], tbl_regs[get_nibble(inst, 3)],
862 tbl_regs[get_nibble(inst, 4)]);
863
864 offset = inst & 0xff;
865 if (!(inst & 0x0200)) offset *= -1;
866
867 if (!(inst & 0x0400) && (inst & 0x0100)) dbg_printf("], #%i", offset);
868 else if (inst & 0x0400) dbg_printf(", #%i]%s", offset, (inst & 0x0100)?"!":"");
869 else return inst;
870 return 0;
871 }
872
873 if (!(op1 & 0x04) && !op2)
874 {
875 dbg_printf("\n\tstr%s\t%s, [%s, %s, LSL #%u]", tbl_width_t2[op1 & 0x03],
876 tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)],
877 tbl_regs[get_nibble(inst, 0)], (inst >> 4) & 0x3);
878 return 0;
879 }
880
881 if (op1 & 0x04)
882 {
883 dbg_printf("\n\tstr%s\t%s, [%s, #%u]", tbl_width_t2[op1 & 0x03],
884 tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)], inst & 0x0fff);
885 return 0;
886 }
887
888 return inst;
889 }
890
891 static UINT thumb2_disasm_ldrword(UINT inst, ADDRESS64 *addr)
892 {
893 WORD op1 = (inst >> 23) & 0x01;
894 WORD op2 = (inst >> 6) & 0x3f;
895 int offset;
896
897 if (get_nibble(inst, 4) == 0x0f)
898 {
899 offset = inst & 0x0fff;
900
901 if (!op1) offset *= -1;
902 offset += 3;
903
904 dbg_printf("\n\tldr\t%s, ", tbl_regs[get_nibble(inst, 3)]);
905 db_printsym(addr->Offset + offset);
906 return 0;
907 }
908
909 if (!op1 && !op2)
910 {
911 dbg_printf("\n\tldr\t%s, [%s, %s, LSL #%u]", tbl_regs[get_nibble(inst, 3)],
912 tbl_regs[get_nibble(inst, 4)], tbl_regs[get_nibble(inst, 0)], (inst >> 4) & 0x3);
913 return 0;
914 }
915
916 if (!op1 && (op2 & 0x3c) == 0x38)
917 {
918 dbg_printf("\n\tldrt\t%s, [%s, #%u]", tbl_regs[get_nibble(inst, 3)],
919 tbl_regs[get_nibble(inst, 4)], inst & 0xff);
920 return 0;
921 }
922
923 dbg_printf("\n\tldr\t%s, [%s", tbl_regs[get_nibble(inst, 3)], tbl_regs[get_nibble(inst, 4)]);
924
925 if (op1)
926 {
927 dbg_printf(", #%u]", inst & 0x0fff);
928 return 0;
929 }
930
931 offset = inst & 0xff;
932 if (!(inst & 0x0200)) offset *= -1;
933
934 if (!(inst & 0x0400) && (inst & 0x0100)) dbg_printf("], #%i", offset);
935 else if (inst & 0x0400) dbg_printf(", #%i]%s", offset, (inst & 0x0100)?"!":"");
936 else return inst;
937
938 return 0;
939 }
940
941 static UINT thumb2_disasm_coprocmov1(UINT inst, ADDRESS64 *addr)
942 {
943 WORD opc1 = (inst >> 21) & 0x07;
944 WORD opc2 = (inst >> 5) & 0x07;
945
946 if (opc2)
947 dbg_printf("\n\t%s%s\tp%u, #%u, %s, cr%u, cr%u, #%u", (inst & 0x00100000)?"mrc":"mcr",
948 (inst & 0x10000000)?"2":"", get_nibble(inst, 2), opc1,
949 tbl_regs[get_nibble(inst, 3)], get_nibble(inst, 4), get_nibble(inst, 0), opc2);
950 else
951 dbg_printf("\n\t%s%s\tp%u, #%u, %s, cr%u, cr%u", (inst & 0x00100000)?"mrc":"mcr",
952 (inst & 0x10000000)?"2":"", get_nibble(inst, 2), opc1,
953 tbl_regs[get_nibble(inst, 3)], get_nibble(inst, 4), get_nibble(inst, 0));
954
955 return 0;
956 }
957
958 struct inst_arm
959 {
960 UINT mask;
961 UINT pattern;
962 UINT (*func)(UINT, ADDRESS64*);
963 };
964
965 static const struct inst_arm tbl_arm[] = {
966 { 0x0e000000, 0x0a000000, arm_disasm_branch },
967 { 0x0fc000f0, 0x00000090, arm_disasm_mul },
968 { 0x0f8000f0, 0x00800090, arm_disasm_longmul },
969 { 0x0fb00ff0, 0x01000090, arm_disasm_swp },
970 { 0x0e000090, 0x00000090, arm_disasm_halfwordtrans },
971 { 0x0ffffff0, 0x012fff00, arm_disasm_branchreg },
972 { 0x0ffffff0, 0x012fff10, arm_disasm_branchxchg },
973 { 0x0fbf0fff, 0x010f0000, arm_disasm_mrstrans },
974 { 0x0dbef000, 0x0128f000, arm_disasm_msrtrans },
975 { 0x0fb00000, 0x03000000, arm_disasm_wordmov },
976 { 0x0fffffff, 0x0320f000, arm_disasm_nop },
977 { 0x0c000000, 0x00000000, arm_disasm_dataprocessing },
978 { 0x0c000000, 0x04000000, arm_disasm_singletrans },
979 { 0x0e000000, 0x08000000, arm_disasm_blocktrans },
980 { 0x0f000000, 0x0f000000, arm_disasm_swi },
981 { 0x0f000010, 0x0e000010, arm_disasm_coproctrans },
982 { 0x0f000010, 0x0e000000, arm_disasm_coprocdataop },
983 { 0x0e000000, 0x0c000000, arm_disasm_coprocdatatrans },
984 { 0x00000000, 0x00000000, NULL }
985 };
986
987 struct inst_thumb16
988 {
989 WORD mask;
990 WORD pattern;
991 WORD (*func)(WORD, ADDRESS64*);
992 };
993
994 static const struct inst_thumb16 tbl_thumb16[] = {
995 { 0xfc00, 0x4400, thumb_disasm_hireg },
996 { 0xfc00, 0x4000, thumb_disasm_aluop },
997 { 0xf600, 0xb400, thumb_disasm_pushpop },
998 { 0xf000, 0xc000, thumb_disasm_blocktrans },
999 { 0xf000, 0xd000, thumb_disasm_condbranch },
1000 { 0xf800, 0xe000, thumb_disasm_uncondbranch },
1001 { 0xf000, 0xa000, thumb_disasm_loadadr },
1002 { 0xf800, 0x4800, thumb_disasm_ldrpcrel },
1003 { 0xf000, 0x9000, thumb_disasm_ldrsprel },
1004 { 0xff00, 0xb000, thumb_disasm_addsprel },
1005 { 0xe000, 0x6000, thumb_disasm_ldrimm },
1006 { 0xf000, 0x8000, thumb_disasm_ldrhimm },
1007 { 0xf200, 0x5000, thumb_disasm_ldrreg },
1008 { 0xf200, 0x5200, thumb_disasm_ldrsreg },
1009 { 0xe000, 0x2000, thumb_disasm_immop },
1010 { 0xff00, 0xdf00, thumb_disasm_swi },
1011 { 0xff00, 0xbf00, thumb_disasm_nop },
1012 { 0xf800, 0x1800, thumb_disasm_addsub },
1013 { 0xe000, 0x0000, thumb_disasm_movshift },
1014 { 0x0000, 0x0000, NULL }
1015 };
1016
1017 static const struct inst_arm tbl_thumb32[] = {
1018 { 0xfff0f000, 0xf3e08000, thumb2_disasm_srtrans },
1019 { 0xfff0f000, 0xf3808000, thumb2_disasm_srtrans },
1020 { 0xfff0d000, 0xf3a08000, thumb2_disasm_hint },
1021 { 0xf8008000, 0xf0008000, thumb2_disasm_branch },
1022 { 0xffc0f0c0, 0xfa80f080, thumb2_disasm_misc },
1023 { 0xff80f000, 0xfa00f000, thumb2_disasm_dataprocessingreg },
1024 { 0xff8000c0, 0xfb000000, thumb2_disasm_mul },
1025 { 0xff8000f0, 0xfb800000, thumb2_disasm_longmuldiv },
1026 { 0xff8000f0, 0xfb8000f0, thumb2_disasm_longmuldiv },
1027 { 0xff100000, 0xf8000000, thumb2_disasm_str },
1028 { 0xff700000, 0xf8500000, thumb2_disasm_ldrword },
1029 { 0xef000010, 0xee000010, thumb2_disasm_coprocmov1 },
1030 { 0x00000000, 0x00000000, NULL }
1031 };
1032
1033 /***********************************************************************
1034 * disasm_one_insn
1035 *
1036 * Disassemble instruction at 'addr'. addr is changed to point to the
1037 * start of the next instruction.
1038 */
1039 void be_arm_disasm_one_insn(ADDRESS64 *addr, int display)
1040 {
1041 struct inst_arm *a_ptr = (struct inst_arm *)&tbl_arm;
1042 struct inst_thumb16 *t_ptr = (struct inst_thumb16 *)&tbl_thumb16;
1043 struct inst_arm *t2_ptr = (struct inst_arm *)&tbl_thumb32;
1044 UINT inst;
1045 WORD tinst;
1046 int size;
1047 int matched = 0;
1048
1049 char tmp[64];
1050 DWORD_PTR* pval;
1051
1052 if (!memory_get_register(CV_ARM_CPSR, &pval, tmp, sizeof(tmp)))
1053 dbg_printf("\n\tmemory_get_register failed: %s", tmp);
1054 else
1055 db_disasm_thumb = (*pval & 0x20) != 0;
1056
1057 db_display = display;
1058
1059 if (!db_disasm_thumb)
1060 {
1061 size = ARM_INSN_SIZE;
1062 inst = db_get_inst( memory_to_linear_addr(addr), size );
1063 while (a_ptr->func) {
1064 if ((inst & a_ptr->mask) == a_ptr->pattern) {
1065 matched = 1;
1066 break;
1067 }
1068 a_ptr++;
1069 }
1070
1071 if (!matched) {
1072 dbg_printf("\n\tUnknown ARM Instruction: %08x", inst);
1073 addr->Offset += size;
1074 }
1075 else
1076 {
1077 if (!a_ptr->func(inst, addr))
1078 addr->Offset += size;
1079 }
1080 return;
1081 }
1082 else
1083 {
1084 WORD *taddr = memory_to_linear_addr(addr);
1085 tinst = db_get_inst( taddr, THUMB_INSN_SIZE );
1086 switch (tinst & 0xf800)
1087 {
1088 case 0xe800:
1089 case 0xf000:
1090 case 0xf800:
1091 size = THUMB2_INSN_SIZE;
1092 taddr++;
1093 inst = db_get_inst( taddr, THUMB_INSN_SIZE );
1094 inst |= (tinst << 16);
1095
1096 while (t2_ptr->func) {
1097 if ((inst & t2_ptr->mask) == t2_ptr->pattern) {
1098 matched = 1;
1099 break;
1100 }
1101 t2_ptr++;
1102 }
1103
1104 if (!matched) {
1105 dbg_printf("\n\tUnknown Thumb2 Instruction: %08x", inst);
1106 addr->Offset += size;
1107 }
1108 else
1109 {
1110 if (!t2_ptr->func(inst, addr))
1111 addr->Offset += size;
1112 }
1113 return;
1114 default:
1115 break;
1116 }
1117
1118 size = THUMB_INSN_SIZE;
1119 while (t_ptr->func) {
1120 if ((tinst & t_ptr->mask) == t_ptr->pattern) {
1121 matched = 1;
1122 break;
1123 }
1124 t_ptr++;
1125 }
1126
1127 if (!matched) {
1128 dbg_printf("\n\tUnknown Thumb Instruction: %04x", tinst);
1129 addr->Offset += size;
1130 }
1131 else
1132 {
1133 if (!t_ptr->func(tinst, addr))
1134 addr->Offset += size;
1135 }
1136 return;
1137 }
1138 }
1139
1140 static unsigned be_arm_get_addr(HANDLE hThread, const CONTEXT* ctx,
1141 enum be_cpu_addr bca, ADDRESS64* addr)
1142 {
1143 switch (bca)
1144 {
1145 case be_cpu_addr_pc:
1146 return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->Pc);
1147 case be_cpu_addr_stack:
1148 return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->Sp);
1149 case be_cpu_addr_frame:
1150 return be_cpu_build_addr(hThread, ctx, addr, 0, ctx->Fp);
1151 }
1152 return FALSE;
1153 }
1154
1155 static unsigned be_arm_get_register_info(int regno, enum be_cpu_addr* kind)
1156 {
1157 switch (regno)
1158 {
1159 case CV_ARM_PC: *kind = be_cpu_addr_pc; return TRUE;
1160 case CV_ARM_R0 + 11: *kind = be_cpu_addr_frame; return TRUE;
1161 case CV_ARM_SP: *kind = be_cpu_addr_stack; return TRUE;
1162 }
1163 return FALSE;
1164 }
1165
1166 static void be_arm_single_step(CONTEXT* ctx, unsigned enable)
1167 {
1168 dbg_printf("be_arm_single_step: not done\n");
1169 }
1170
1171 static void be_arm_print_context(HANDLE hThread, const CONTEXT* ctx, int all_regs)
1172 {
1173 static const char condflags[] = "NZCV";
1174 int i;
1175 char buf[8];
1176
1177 switch (ctx->Cpsr & 0x1F)
1178 {
1179 case 0: strcpy(buf, "User26"); break;
1180 case 1: strcpy(buf, "FIQ26"); break;
1181 case 2: strcpy(buf, "IRQ26"); break;
1182 case 3: strcpy(buf, "SVC26"); break;
1183 case 16: strcpy(buf, "User"); break;
1184 case 17: strcpy(buf, "FIQ"); break;
1185 case 18: strcpy(buf, "IRQ"); break;
1186 case 19: strcpy(buf, "SVC"); break;
1187 case 23: strcpy(buf, "ABT"); break;
1188 case 27: strcpy(buf, "UND"); break;
1189 default: strcpy(buf, "UNKNWN"); break;
1190 }
1191
1192 dbg_printf("Register dump:\n");
1193 dbg_printf("%s %s Mode\n", (ctx->Cpsr & 0x20) ? "Thumb" : "ARM", buf);
1194
1195 strcpy(buf, condflags);
1196 for (i = 0; buf[i]; i++)
1197 if (!((ctx->Cpsr >> 26) & (1 << (sizeof(condflags) - i))))
1198 buf[i] = '-';
1199
1200 dbg_printf(" Pc:%04x Sp:%04x Lr:%04x Cpsr:%04x(%s)\n",
1201 ctx->Pc, ctx->Sp, ctx->Lr, ctx->Cpsr, buf);
1202 dbg_printf(" r0:%04x r1:%04x r2:%04x r3:%04x\n",
1203 ctx->R0, ctx->R1, ctx->R2, ctx->R3);
1204 dbg_printf(" r4:%04x r5:%04x r6:%04x r7:%04x r8:%04x\n",
1205 ctx->R4, ctx->R5, ctx->R6, ctx->R7, ctx->R8 );
1206 dbg_printf(" r9:%04x r10:%04x Fp:%04x Ip:%04x\n",
1207 ctx->R9, ctx->R10, ctx->Fp, ctx->Ip );
1208
1209 if (all_regs) dbg_printf( "Floating point ARM dump not implemented\n" );
1210 }
1211
1212 static void be_arm_print_segment_info(HANDLE hThread, const CONTEXT* ctx)
1213 {
1214 }
1215
1216 static struct dbg_internal_var be_arm_ctx[] =
1217 {
1218 {CV_ARM_R0 + 0, "r0", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R0), dbg_itype_unsigned_int},
1219 {CV_ARM_R0 + 1, "r1", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R1), dbg_itype_unsigned_int},
1220 {CV_ARM_R0 + 2, "r2", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R2), dbg_itype_unsigned_int},
1221 {CV_ARM_R0 + 3, "r3", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R3), dbg_itype_unsigned_int},
1222 {CV_ARM_R0 + 4, "r4", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R4), dbg_itype_unsigned_int},
1223 {CV_ARM_R0 + 5, "r5", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R5), dbg_itype_unsigned_int},
1224 {CV_ARM_R0 + 6, "r6", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R6), dbg_itype_unsigned_int},
1225 {CV_ARM_R0 + 7, "r7", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R7), dbg_itype_unsigned_int},
1226 {CV_ARM_R0 + 8, "r8", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R8), dbg_itype_unsigned_int},
1227 {CV_ARM_R0 + 9, "r9", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R9), dbg_itype_unsigned_int},
1228 {CV_ARM_R0 + 10, "r10", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R10), dbg_itype_unsigned_int},
1229 {CV_ARM_R0 + 11, "r11", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Fp), dbg_itype_unsigned_int},
1230 {CV_ARM_R0 + 12, "r12", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Ip), dbg_itype_unsigned_int},
1231 {CV_ARM_SP, "sp", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Sp), dbg_itype_unsigned_int},
1232 {CV_ARM_LR, "lr", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Lr), dbg_itype_unsigned_int},
1233 {CV_ARM_PC, "pc", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Pc), dbg_itype_unsigned_int},
1234 {CV_ARM_CPSR, "cpsr", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Cpsr), dbg_itype_unsigned_int},
1235 {0, NULL, 0, dbg_itype_none}
1236 };
1237
1238 static unsigned be_arm_is_step_over_insn(const void* insn)
1239 {
1240 dbg_printf("be_arm_is_step_over_insn: not done\n");
1241 return FALSE;
1242 }
1243
1244 static unsigned be_arm_is_function_return(const void* insn)
1245 {
1246 dbg_printf("be_arm_is_function_return: not done\n");
1247 return FALSE;
1248 }
1249
1250 static unsigned be_arm_is_break_insn(const void* insn)
1251 {
1252 dbg_printf("be_arm_is_break_insn: not done\n");
1253 return FALSE;
1254 }
1255
1256 static unsigned be_arm_is_func_call(const void* insn, ADDRESS64* callee)
1257 {
1258 return FALSE;
1259 }
1260
1261 static unsigned be_arm_is_jump(const void* insn, ADDRESS64* jumpee)
1262 {
1263 return FALSE;
1264 }
1265
1266 static unsigned be_arm_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
1267 CONTEXT* ctx, enum be_xpoint_type type,
1268 void* addr, unsigned long* val, unsigned size)
1269 {
1270 SIZE_T sz;
1271
1272 switch (type)
1273 {
1274 case be_xpoint_break:
1275 if (!size) return 0;
1276 if (!pio->read(hProcess, addr, val, 4, &sz) || sz != 4) return 0;
1277 default:
1278 dbg_printf("Unknown/unsupported bp type %c\n", type);
1279 return 0;
1280 }
1281 return 1;
1282 }
1283
1284 static unsigned be_arm_remove_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
1285 CONTEXT* ctx, enum be_xpoint_type type,
1286 void* addr, unsigned long val, unsigned size)
1287 {
1288 SIZE_T sz;
1289
1290 switch (type)
1291 {
1292 case be_xpoint_break:
1293 if (!size) return 0;
1294 if (!pio->write(hProcess, addr, &val, 4, &sz) || sz == 4) return 0;
1295 break;
1296 default:
1297 dbg_printf("Unknown/unsupported bp type %c\n", type);
1298 return 0;
1299 }
1300 return 1;
1301 }
1302
1303 static unsigned be_arm_is_watchpoint_set(const CONTEXT* ctx, unsigned idx)
1304 {
1305 dbg_printf("be_arm_is_watchpoint_set: not done\n");
1306 return FALSE;
1307 }
1308
1309 static void be_arm_clear_watchpoint(CONTEXT* ctx, unsigned idx)
1310 {
1311 dbg_printf("be_arm_clear_watchpoint: not done\n");
1312 }
1313
1314 static int be_arm_adjust_pc_for_break(CONTEXT* ctx, BOOL way)
1315 {
1316 INT step = (ctx->Cpsr & 0x20) ? 2 : 4;
1317
1318 if (way)
1319 {
1320 ctx->Pc -= step;
1321 return -step;
1322 }
1323 ctx->Pc += step;
1324 return step;
1325 }
1326
1327 static int be_arm_fetch_integer(const struct dbg_lvalue* lvalue, unsigned size,
1328 unsigned ext_sign, LONGLONG* ret)
1329 {
1330 if (size != 1 && size != 2 && size != 4 && size != 8) return FALSE;
1331
1332 memset(ret, 0, sizeof(*ret)); /* clear unread bytes */
1333 /* FIXME: this assumes that debuggee and debugger use the same
1334 * integral representation
1335 */
1336 if (!memory_read_value(lvalue, size, ret)) return FALSE;
1337
1338 /* propagate sign information */
1339 if (ext_sign && size < 8 && (*ret >> (size * 8 - 1)) != 0)
1340 {
1341 ULONGLONG neg = -1;
1342 *ret |= neg << (size * 8);
1343 }
1344 return TRUE;
1345 }
1346
1347 static int be_arm_fetch_float(const struct dbg_lvalue* lvalue, unsigned size,
1348 long double* ret)
1349 {
1350 char tmp[sizeof(long double)];
1351
1352 /* FIXME: this assumes that debuggee and debugger use the same
1353 * representation for reals
1354 */
1355 if (!memory_read_value(lvalue, size, tmp)) return FALSE;
1356
1357 switch (size)
1358 {
1359 case sizeof(float): *ret = *(float*)tmp; break;
1360 case sizeof(double): *ret = *(double*)tmp; break;
1361 default: return FALSE;
1362 }
1363 return TRUE;
1364 }
1365
1366 static int be_arm_store_integer(const struct dbg_lvalue* lvalue, unsigned size,
1367 unsigned is_signed, LONGLONG val)
1368 {
1369 /* this is simple if we're on a little endian CPU */
1370 return memory_write_value(lvalue, size, &val);
1371 }
1372
1373 struct backend_cpu be_arm =
1374 {
1375 IMAGE_FILE_MACHINE_ARMNT,
1376 4,
1377 be_cpu_linearize,
1378 be_cpu_build_addr,
1379 be_arm_get_addr,
1380 be_arm_get_register_info,
1381 be_arm_single_step,
1382 be_arm_print_context,
1383 be_arm_print_segment_info,
1384 be_arm_ctx,
1385 be_arm_is_step_over_insn,
1386 be_arm_is_function_return,
1387 be_arm_is_break_insn,
1388 be_arm_is_func_call,
1389 be_arm_is_jump,
1390 be_arm_disasm_one_insn,
1391 be_arm_insert_Xpoint,
1392 be_arm_remove_Xpoint,
1393 be_arm_is_watchpoint_set,
1394 be_arm_clear_watchpoint,
1395 be_arm_adjust_pc_for_break,
1396 be_arm_fetch_integer,
1397 be_arm_fetch_float,
1398 be_arm_store_integer,
1399 };
1400 #endif
Windows API implementation