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winedbg: Implemented is_step_over method for x86-64 CPU.
[wine.git] / programs / winedbg / be_x86_64.c
bloba0e56371258b6a4a8405c6ec824d17aaf8608fd1
1 /*
2 * Debugger x86_64 specific functions
3 *
4 * Copyright 2004 Vincent Béron
5 * Copyright 2009 Eric Pouech
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
20 */
21
22 #include "debugger.h"
23 #include "wine/debug.h"
24
25 WINE_DEFAULT_DEBUG_CHANNEL(winedbg);
26
27 #if defined(__x86_64__)
28
29 #define STEP_FLAG 0x00000100 /* single step flag */
30
31 static unsigned be_x86_64_get_addr(HANDLE hThread, const CONTEXT* ctx,
32 enum be_cpu_addr bca, ADDRESS64* addr)
33 {
34 addr->Mode = AddrModeFlat;
35 switch (bca)
36 {
37 case be_cpu_addr_pc:
38 addr->Segment = ctx->SegCs;
39 addr->Offset = ctx->Rip;
40 return TRUE;
41 case be_cpu_addr_stack:
42 addr->Segment = ctx->SegSs;
43 addr->Offset = ctx->Rsp;
44 return TRUE;
45 case be_cpu_addr_frame:
46 addr->Segment = ctx->SegSs;
47 addr->Offset = ctx->Rbp;
48 return TRUE;
49 default:
50 addr->Mode = -1;
51 return FALSE;
52 }
53 }
54
55 static unsigned be_x86_64_get_register_info(int regno, enum be_cpu_addr* kind)
56 {
57 /* this is true when running in 32bit mode... and wrong in 64 :-/ */
58 switch (regno)
59 {
60 case CV_AMD64_RIP: *kind = be_cpu_addr_pc; return TRUE;
61 case CV_AMD64_EBP: *kind = be_cpu_addr_frame; return TRUE;
62 case CV_AMD64_ESP: *kind = be_cpu_addr_stack; return TRUE;
63 }
64 return FALSE;
65 }
66
67 static void be_x86_64_single_step(CONTEXT* ctx, unsigned enable)
68 {
69 if (enable) ctx->EFlags |= STEP_FLAG;
70 else ctx->EFlags &= ~STEP_FLAG;
71 }
72
73 static void be_x86_64_print_context(HANDLE hThread, const CONTEXT* ctx,
74 int all_regs)
75 {
76 static const char flags[] = "aVR-N--ODITSZ-A-P-C";
77 char buf[33];
78 int i;
79
80 strcpy(buf, flags);
81 for (i = 0; buf[i]; i++)
82 if (buf[i] != '-' && !(ctx->EFlags & (1 << (sizeof(flags) - 2 - i))))
83 buf[i] = ' ';
84
85 dbg_printf("Register dump:\n");
86 dbg_printf(" rip:%016lx rsp:%016lx rbp:%016lx eflags:%08x (%s)\n",
87 ctx->Rip, ctx->Rsp, ctx->Rbp, ctx->EFlags, buf);
88 dbg_printf(" rax:%016lx rbx:%016lx rcx:%016lx rdx:%016lx\n",
89 ctx->Rax, ctx->Rbx, ctx->Rcx, ctx->Rdx);
90 dbg_printf(" rsi:%016lx rdi:%016lx r8:%016lx r9:%016lx r10:%016lx\n",
91 ctx->Rsi, ctx->Rdi, ctx->R8, ctx->R9, ctx->R10 );
92 dbg_printf(" r11:%016lx r12:%016lx r13:%016lx r14:%016lx r15:%016lx\n",
93 ctx->R11, ctx->R12, ctx->R13, ctx->R14, ctx->R15 );
94
95 if (all_regs) dbg_printf( "Floating point x86_64 dump not implemented\n" );
96 }
97
98 static void be_x86_64_print_segment_info(HANDLE hThread, const CONTEXT* ctx)
99 {
100 }
101
102 static struct dbg_internal_var be_x86_64_ctx[] =
103 {
104 {CV_AMD64_AL, "AL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_char_int},
105 {CV_AMD64_BL, "BL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_char_int},
106 {CV_AMD64_CL, "CL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_char_int},
107 {CV_AMD64_DL, "DL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_char_int},
108 {CV_AMD64_AH, "AH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rax)+1), dbg_itype_unsigned_char_int},
109 {CV_AMD64_BH, "BH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rbx)+1), dbg_itype_unsigned_char_int},
110 {CV_AMD64_CH, "CH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rcx)+1), dbg_itype_unsigned_char_int},
111 {CV_AMD64_DH, "DH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rdx)+1), dbg_itype_unsigned_char_int},
112 {CV_AMD64_AX, "AX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_short_int},
113 {CV_AMD64_BX, "BX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_short_int},
114 {CV_AMD64_CX, "CX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_short_int},
115 {CV_AMD64_DX, "DX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_short_int},
116 {CV_AMD64_SP, "SP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_short_int},
117 {CV_AMD64_BP, "BP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_short_int},
118 {CV_AMD64_SI, "SI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_short_int},
119 {CV_AMD64_DI, "DI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_short_int},
120 {CV_AMD64_EAX, "EAX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_int},
121 {CV_AMD64_EBX, "EBX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_int},
122 {CV_AMD64_ECX, "ECX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_int},
123 {CV_AMD64_EDX, "EDX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_int},
124 {CV_AMD64_ESP, "ESP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_int},
125 {CV_AMD64_EBP, "EBP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_int},
126 {CV_AMD64_ESI, "ESI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_int},
127 {CV_AMD64_EDI, "EDI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_int},
128 {CV_AMD64_ES, "ES", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegEs), dbg_itype_unsigned_short_int},
129 {CV_AMD64_CS, "CS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegCs), dbg_itype_unsigned_short_int},
130 {CV_AMD64_SS, "SS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegSs), dbg_itype_unsigned_short_int},
131 {CV_AMD64_DS, "DS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegDs), dbg_itype_unsigned_short_int},
132 {CV_AMD64_FS, "FS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegFs), dbg_itype_unsigned_short_int},
133 {CV_AMD64_GS, "GS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegGs), dbg_itype_unsigned_short_int},
134 {CV_AMD64_FLAGS, "FLAGS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, EFlags), dbg_itype_unsigned_short_int},
135 {CV_AMD64_EFLAGS, "EFLAGS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, EFlags), dbg_itype_unsigned_int},
136 {CV_AMD64_RIP, "RIP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rip), dbg_itype_unsigned_long_int},
137 {CV_AMD64_RAX, "RAX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_long_int},
138 {CV_AMD64_RBX, "RBX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_long_int},
139 {CV_AMD64_RCX, "RCX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_long_int},
140 {CV_AMD64_RDX, "RDX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_long_int},
141 {CV_AMD64_RSP, "RSP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_long_int},
142 {CV_AMD64_RBP, "RBP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_long_int},
143 {CV_AMD64_RSI, "RSI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_long_int},
144 {CV_AMD64_RDI, "RDI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_long_int},
145 {CV_AMD64_R8, "R8", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R8), dbg_itype_unsigned_long_int},
146 {CV_AMD64_R9, "R9", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R9), dbg_itype_unsigned_long_int},
147 {CV_AMD64_R10, "R10", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R10), dbg_itype_unsigned_long_int},
148 {CV_AMD64_R11, "R11", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R11), dbg_itype_unsigned_long_int},
149 {CV_AMD64_R12, "R12", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R12), dbg_itype_unsigned_long_int},
150 {CV_AMD64_R13, "R13", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R13), dbg_itype_unsigned_long_int},
151 {CV_AMD64_R14, "R14", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R14), dbg_itype_unsigned_long_int},
152 {CV_AMD64_R15, "R15", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R15), dbg_itype_unsigned_long_int},
153 {0, NULL, 0, dbg_itype_none}
154 };
155
156 static const struct dbg_internal_var* be_x86_64_init_registers(CONTEXT* ctx)
157 {
158 struct dbg_internal_var* div;
159
160 for (div = be_x86_64_ctx; div->name; div++)
161 div->pval = (DWORD_PTR*)((char*)ctx + (DWORD_PTR)div->pval);
162 return be_x86_64_ctx;
163 }
164
165 static unsigned be_x86_64_is_step_over_insn(const void* insn)
166 {
167 BYTE ch;
168
169 for (;;)
170 {
171 if (!dbg_read_memory(insn, &ch, sizeof(ch))) return FALSE;
172
173 switch (ch)
174 {
175 /* Skip all prefixes */
176 case 0x2e: /* cs: */
177 case 0x36: /* ss: */
178 case 0x3e: /* ds: */
179 case 0x26: /* es: */
180 case 0x64: /* fs: */
181 case 0x65: /* gs: */
182 case 0x66: /* opcode size prefix */
183 case 0x67: /* addr size prefix */
184 case 0xf0: /* lock */
185 case 0xf2: /* repne */
186 case 0xf3: /* repe */
187 insn = (const char*)insn + 1;
188 continue;
189
190 /* Handle call instructions */
191 case 0xcd: /* int <intno> */
192 case 0xe8: /* call <offset> */
193 case 0x9a: /* lcall <seg>:<off> */
194 return TRUE;
195
196 case 0xff: /* call <regmodrm> */
197 if (!dbg_read_memory((const char*)insn + 1, &ch, sizeof(ch)))
198 return FALSE;
199 return (((ch & 0x38) == 0x10) || ((ch & 0x38) == 0x18));
200
201 /* Handle string instructions */
202 case 0x6c: /* insb */
203 case 0x6d: /* insw */
204 case 0x6e: /* outsb */
205 case 0x6f: /* outsw */
206 case 0xa4: /* movsb */
207 case 0xa5: /* movsw */
208 case 0xa6: /* cmpsb */
209 case 0xa7: /* cmpsw */
210 case 0xaa: /* stosb */
211 case 0xab: /* stosw */
212 case 0xac: /* lodsb */
213 case 0xad: /* lodsw */
214 case 0xae: /* scasb */
215 case 0xaf: /* scasw */
216 return TRUE;
217
218 default:
219 return FALSE;
220 }
221 }
222 }
223
224 static unsigned be_x86_64_is_function_return(const void* insn)
225 {
226 BYTE c;
227 return dbg_read_memory(insn, &c, sizeof(c)) && ((c == 0xC2) || (c == 0xC3));
228 }
229
230 static unsigned be_x86_64_is_break_insn(const void* insn)
231 {
232 BYTE c;
233 return dbg_read_memory(insn, &c, sizeof(c)) && c == 0xCC;
234 }
235
236 static unsigned be_x86_64_is_func_call(const void* insn, ADDRESS64* callee)
237 {
238 dbg_printf("not done is_func_call\n");
239 return FALSE;
240 }
241
242 extern void be_x86_64_disasm_one_insn(ADDRESS64* addr, int display);
243
244 #define DR7_CONTROL_SHIFT 16
245 #define DR7_CONTROL_SIZE 4
246
247 #define DR7_RW_EXECUTE (0x0)
248 #define DR7_RW_WRITE (0x1)
249 #define DR7_RW_READ (0x3)
250
251 #define DR7_LEN_1 (0x0)
252 #define DR7_LEN_2 (0x4)
253 #define DR7_LEN_4 (0xC)
254
255 #define DR7_LOCAL_ENABLE_SHIFT 0
256 #define DR7_GLOBAL_ENABLE_SHIFT 1
257 #define DR7_ENABLE_SIZE 2
258
259 #define DR7_LOCAL_ENABLE_MASK (0x55)
260 #define DR7_GLOBAL_ENABLE_MASK (0xAA)
261
262 #define DR7_CONTROL_RESERVED (0xFC00)
263 #define DR7_LOCAL_SLOWDOWN (0x100)
264 #define DR7_GLOBAL_SLOWDOWN (0x200)
265
266 #define DR7_ENABLE_MASK(dr) (1<<(DR7_LOCAL_ENABLE_SHIFT+DR7_ENABLE_SIZE*(dr)))
267 #define IS_DR7_SET(ctrl,dr) ((ctrl)&DR7_ENABLE_MASK(dr))
268
269 static inline int be_x86_64_get_unused_DR(CONTEXT* ctx, DWORD64** r)
270 {
271 if (!IS_DR7_SET(ctx->Dr7, 0))
272 {
273 *r = &ctx->Dr0;
274 return 0;
275 }
276 if (!IS_DR7_SET(ctx->Dr7, 1))
277 {
278 *r = &ctx->Dr1;
279 return 1;
280 }
281 if (!IS_DR7_SET(ctx->Dr7, 2))
282 {
283 *r = &ctx->Dr2;
284 return 2;
285 }
286 if (!IS_DR7_SET(ctx->Dr7, 3))
287 {
288 *r = &ctx->Dr3;
289 return 3;
290 }
291 dbg_printf("All hardware registers have been used\n");
292
293 return -1;
294 }
295
296 static unsigned be_x86_64_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
297 CONTEXT* ctx, enum be_xpoint_type type,
298 void* addr, unsigned long* val, unsigned size)
299 {
300 unsigned char ch;
301 SIZE_T sz;
302 DWORD64 *pr;
303 int reg;
304 unsigned long bits;
305
306 switch (type)
307 {
308 case be_xpoint_break:
309 if (size != 0) return 0;
310 if (!pio->read(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
311 *val = ch;
312 ch = 0xcc;
313 if (!pio->write(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
314 break;
315 case be_xpoint_watch_exec:
316 bits = DR7_RW_EXECUTE;
317 goto hw_bp;
318 case be_xpoint_watch_read:
319 bits = DR7_RW_READ;
320 goto hw_bp;
321 case be_xpoint_watch_write:
322 bits = DR7_RW_WRITE;
323 hw_bp:
324 if ((reg = be_x86_64_get_unused_DR(ctx, &pr)) == -1) return 0;
325 *pr = (DWORD64)addr;
326 if (type != be_xpoint_watch_exec) switch (size)
327 {
328 case 4: bits |= DR7_LEN_4; break;
329 case 2: bits |= DR7_LEN_2; break;
330 case 1: bits |= DR7_LEN_1; break;
331 default: return 0;
332 }
333 *val = reg;
334 /* clear old values */
335 ctx->Dr7 &= ~(0x0F << (DR7_CONTROL_SHIFT + DR7_CONTROL_SIZE * reg));
336 /* set the correct ones */
337 ctx->Dr7 |= bits << (DR7_CONTROL_SHIFT + DR7_CONTROL_SIZE * reg);
338 ctx->Dr7 |= DR7_ENABLE_MASK(reg) | DR7_LOCAL_SLOWDOWN;
339 break;
340 default:
341 dbg_printf("Unknown bp type %c\n", type);
342 return 0;
343 }
344 return 1;
345 }
346
347 static unsigned be_x86_64_remove_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
348 CONTEXT* ctx, enum be_xpoint_type type,
349 void* addr, unsigned long val, unsigned size)
350 {
351 SIZE_T sz;
352 unsigned char ch;
353
354 switch (type)
355 {
356 case be_xpoint_break:
357 if (size != 0) return 0;
358 if (!pio->read(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
359 if (ch != (unsigned char)0xCC)
360 WINE_FIXME("Cannot get back %02x instead of 0xCC at %08lx\n",
361 ch, (unsigned long)addr);
362 ch = (unsigned char)val;
363 if (!pio->write(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
364 break;
365 case be_xpoint_watch_exec:
366 case be_xpoint_watch_read:
367 case be_xpoint_watch_write:
368 /* simply disable the entry */
369 ctx->Dr7 &= ~DR7_ENABLE_MASK(val);
370 break;
371 default:
372 dbg_printf("Unknown bp type %c\n", type);
373 return 0;
374 }
375 return 1;
376 }
377
378 static unsigned be_x86_64_is_watchpoint_set(const CONTEXT* ctx, unsigned idx)
379 {
380 return ctx->Dr6 & (1 << idx);
381 }
382
383 static void be_x86_64_clear_watchpoint(CONTEXT* ctx, unsigned idx)
384 {
385 ctx->Dr6 &= ~(1 << idx);
386 }
387
388 static int be_x86_64_adjust_pc_for_break(CONTEXT* ctx, BOOL way)
389 {
390 if (way)
391 {
392 ctx->Rip--;
393 return -1;
394 }
395 ctx->Rip++;
396 return 1;
397 }
398
399 static int be_x86_64_fetch_integer(const struct dbg_lvalue* lvalue, unsigned size,
400 unsigned ext_sign, LONGLONG* ret)
401 {
402 if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16)
403 return FALSE;
404
405 memset(ret, 0, sizeof(*ret)); /* clear unread bytes */
406 /* FIXME: this assumes that debuggee and debugger use the same
407 * integral representation
408 */
409 if (!memory_read_value(lvalue, size, ret)) return FALSE;
410
411 /* propagate sign information */
412 if (ext_sign && size < 16 && (*ret >> (size * 8 - 1)) != 0)
413 {
414 ULONGLONG neg = -1;
415 *ret |= neg << (size * 8);
416 }
417 return TRUE;
418 }
419
420 static int be_x86_64_fetch_float(const struct dbg_lvalue* lvalue, unsigned size,
421 long double* ret)
422 {
423 char tmp[sizeof(long double)];
424
425 /* FIXME: this assumes that debuggee and debugger use the same
426 * representation for reals
427 */
428 if (!memory_read_value(lvalue, size, tmp)) return FALSE;
429
430 /* float & double types have to be promoted to a long double */
431 switch (size)
432 {
433 case sizeof(float): *ret = *(float*)tmp; break;
434 case sizeof(double): *ret = *(double*)tmp; break;
435 case sizeof(long double): *ret = *(long double*)tmp; break;
436 default: return FALSE;
437 }
438 return TRUE;
439 }
440
441 struct backend_cpu be_x86_64 =
442 {
443 IMAGE_FILE_MACHINE_AMD64,
444 be_cpu_linearize,
445 be_cpu_build_addr,
446 be_x86_64_get_addr,
447 be_x86_64_get_register_info,
448 be_x86_64_single_step,
449 be_x86_64_print_context,
450 be_x86_64_print_segment_info,
451 be_x86_64_init_registers,
452 be_x86_64_is_step_over_insn,
453 be_x86_64_is_function_return,
454 be_x86_64_is_break_insn,
455 be_x86_64_is_func_call,
456 be_x86_64_disasm_one_insn,
457 be_x86_64_insert_Xpoint,
458 be_x86_64_remove_Xpoint,
459 be_x86_64_is_watchpoint_set,
460 be_x86_64_clear_watchpoint,
461 be_x86_64_adjust_pc_for_break,
462 be_x86_64_fetch_integer,
463 be_x86_64_fetch_float,
464 };
465 #endif
Windows API implementation