drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/analog_intf_reg.h

   1 #ifndef _ANALOG_INTF_REG_REG_H_
   2 #define _ANALOG_INTF_REG_REG_H_
   3
   4 #define SW_OVERRIDE_ADDRESS                      0x00000080
   5 #define SW_OVERRIDE_OFFSET                       0x00000080
   6 #define SW_OVERRIDE_SUPDATE_DELAY_MSB            1
   7 #define SW_OVERRIDE_SUPDATE_DELAY_LSB            1
   8 #define SW_OVERRIDE_SUPDATE_DELAY_MASK           0x00000002
   9 #define SW_OVERRIDE_SUPDATE_DELAY_GET(x)         (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB)
  10 #define SW_OVERRIDE_SUPDATE_DELAY_SET(x)         (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK)
  11 #define SW_OVERRIDE_ENABLE_MSB                   0
  12 #define SW_OVERRIDE_ENABLE_LSB                   0
  13 #define SW_OVERRIDE_ENABLE_MASK                  0x00000001
  14 #define SW_OVERRIDE_ENABLE_GET(x)                (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB)
  15 #define SW_OVERRIDE_ENABLE_SET(x)                (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK)
  16
  17 #define SIN_VAL_ADDRESS                          0x00000084
  18 #define SIN_VAL_OFFSET                           0x00000084
  19 #define SIN_VAL_SIN_MSB                          0
  20 #define SIN_VAL_SIN_LSB                          0
  21 #define SIN_VAL_SIN_MASK                         0x00000001
  22 #define SIN_VAL_SIN_GET(x)                       (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB)
  23 #define SIN_VAL_SIN_SET(x)                       (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK)
  24
  25 #define SW_SCLK_ADDRESS                          0x00000088
  26 #define SW_SCLK_OFFSET                           0x00000088
  27 #define SW_SCLK_SW_SCLK_MSB                      0
  28 #define SW_SCLK_SW_SCLK_LSB                      0
  29 #define SW_SCLK_SW_SCLK_MASK                     0x00000001
  30 #define SW_SCLK_SW_SCLK_GET(x)                   (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB)
  31 #define SW_SCLK_SW_SCLK_SET(x)                   (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK)
  32
  33 #define SW_CNTL_ADDRESS                          0x0000008c
  34 #define SW_CNTL_OFFSET                           0x0000008c
  35 #define SW_CNTL_SW_SCAPTURE_MSB                  2
  36 #define SW_CNTL_SW_SCAPTURE_LSB                  2
  37 #define SW_CNTL_SW_SCAPTURE_MASK                 0x00000004
  38 #define SW_CNTL_SW_SCAPTURE_GET(x)               (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB)
  39 #define SW_CNTL_SW_SCAPTURE_SET(x)               (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK)
  40 #define SW_CNTL_SW_SUPDATE_MSB                   1
  41 #define SW_CNTL_SW_SUPDATE_LSB                   1
  42 #define SW_CNTL_SW_SUPDATE_MASK                  0x00000002
  43 #define SW_CNTL_SW_SUPDATE_GET(x)                (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB)
  44 #define SW_CNTL_SW_SUPDATE_SET(x)                (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK)
  45 #define SW_CNTL_SW_SOUT_MSB                      0
  46 #define SW_CNTL_SW_SOUT_LSB                      0
  47 #define SW_CNTL_SW_SOUT_MASK                     0x00000001
  48 #define SW_CNTL_SW_SOUT_GET(x)                   (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB)
  49 #define SW_CNTL_SW_SOUT_SET(x)                   (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK)
  50
  51
  52 #ifndef __ASSEMBLER__
  53
  54 typedef struct analog_intf_reg_reg_s {
  55   unsigned char pad0[128]; /* pad to 0x80 */
  56   volatile unsigned int sw_override;
  57   volatile unsigned int sin_val;
  58   volatile unsigned int sw_sclk;
  59   volatile unsigned int sw_cntl;
  60 } analog_intf_reg_reg_t;
  61
  62 #endif /* __ASSEMBLER__ */
  63
  64 #endif /* _ANALOG_INTF_REG_H_ */