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powerpc/fsl_pci: Fix P2P bridge handling for MPC83xx PCIe controllers
[wandboard.git] / arch / powerpc / sysdev / fsl_pci.c
blobe1a028c1f18d0a94a415038c343f160309eb034c
1 /*
2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
3 *
4 * Copyright 2007-2009 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
6 *
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/bootmem.h>
26 #include <linux/lmb.h>
27 #include <linux/log2.h>
28
29 #include <asm/io.h>
30 #include <asm/prom.h>
31 #include <asm/pci-bridge.h>
32 #include <asm/machdep.h>
33 #include <sysdev/fsl_soc.h>
34 #include <sysdev/fsl_pci.h>
35
36 static int fsl_pcie_bus_fixup;
37
38 static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
39 {
40 /* if we aren't a PCIe don't bother */
41 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
42 return;
43
44 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
45 fsl_pcie_bus_fixup = 1;
46 return;
47 }
48
49 static int __init fsl_pcie_check_link(struct pci_controller *hose)
50 {
51 u32 val;
52
53 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
54 if (val < PCIE_LTSSM_L0)
55 return 1;
56 return 0;
57 }
58
59 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
60 static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
61 unsigned int index, const struct resource *res,
62 resource_size_t offset)
63 {
64 resource_size_t pci_addr = res->start - offset;
65 resource_size_t phys_addr = res->start;
66 resource_size_t size = res->end - res->start + 1;
67 u32 flags = 0x80044000; /* enable & mem R/W */
68 unsigned int i;
69
70 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
71 (u64)res->start, (u64)size);
72
73 if (res->flags & IORESOURCE_PREFETCH)
74 flags |= 0x10000000; /* enable relaxed ordering */
75
76 for (i = 0; size > 0; i++) {
77 unsigned int bits = min(__ilog2(size),
78 __ffs(pci_addr | phys_addr));
79
80 if (index + i >= 5)
81 return -1;
82
83 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
84 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
85 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
86 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
87
88 pci_addr += (resource_size_t)1U << bits;
89 phys_addr += (resource_size_t)1U << bits;
90 size -= (resource_size_t)1U << bits;
91 }
92
93 return i;
94 }
95
96 /* atmu setup for fsl pci/pcie controller */
97 static void __init setup_pci_atmu(struct pci_controller *hose,
98 struct resource *rsrc)
99 {
100 struct ccsr_pci __iomem *pci;
101 int i, j, n, mem_log, win_idx = 2;
102 u64 mem, sz, paddr_hi = 0;
103 u64 paddr_lo = ULLONG_MAX;
104 u32 pcicsrbar = 0, pcicsrbar_sz;
105 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
106 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
107 char *name = hose->dn->full_name;
108
109 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
110 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
111 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
112 if (!pci) {
113 dev_err(hose->parent, "Unable to map ATMU registers\n");
114 return;
115 }
116
117 /* Disable all windows (except powar0 since it's ignored) */
118 for(i = 1; i < 5; i++)
119 out_be32(&pci->pow[i].powar, 0);
120 for(i = 0; i < 3; i++)
121 out_be32(&pci->piw[i].piwar, 0);
122
123 /* Setup outbound MEM window */
124 for(i = 0, j = 1; i < 3; i++) {
125 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
126 continue;
127
128 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
129 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
130
131 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
132 hose->pci_mem_offset);
133
134 if (n < 0 || j >= 5) {
135 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
136 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
137 } else
138 j += n;
139 }
140
141 /* Setup outbound IO window */
142 if (hose->io_resource.flags & IORESOURCE_IO) {
143 if (j >= 5) {
144 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
145 } else {
146 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
147 "phy base 0x%016llx.\n",
148 (u64)hose->io_resource.start,
149 (u64)hose->io_resource.end - (u64)hose->io_resource.start + 1,
150 (u64)hose->io_base_phys);
151 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
152 out_be32(&pci->pow[j].potear, 0);
153 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
154 /* Enable, IO R/W */
155 out_be32(&pci->pow[j].powar, 0x80088000
156 | (__ilog2(hose->io_resource.end
157 - hose->io_resource.start + 1) - 1));
158 }
159 }
160
161 /* convert to pci address space */
162 paddr_hi -= hose->pci_mem_offset;
163 paddr_lo -= hose->pci_mem_offset;
164
165 if (paddr_hi == paddr_lo) {
166 pr_err("%s: No outbound window space\n", name);
167 return ;
168 }
169
170 if (paddr_lo == 0) {
171 pr_err("%s: No space for inbound window\n", name);
172 return ;
173 }
174
175 /* setup PCSRBAR/PEXCSRBAR */
176 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
177 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
178 pcicsrbar_sz = ~pcicsrbar_sz + 1;
179
180 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
181 (paddr_lo > 0x100000000ull))
182 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
183 else
184 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
185 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
186
187 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
188
189 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
190
191 /* Setup inbound mem window */
192 mem = lmb_end_of_DRAM();
193 sz = min(mem, paddr_lo);
194 mem_log = __ilog2_u64(sz);
195
196 /* PCIe can overmap inbound & outbound since RX & TX are separated */
197 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
198 /* Size window to exact size if power-of-two or one size up */
199 if ((1ull << mem_log) != mem) {
200 if ((1ull << mem_log) > mem)
201 pr_info("%s: Setting PCI inbound window "
202 "greater than memory size\n", name);
203 mem_log++;
204 }
205
206 piwar |= (mem_log - 1);
207
208 /* Setup inbound memory window */
209 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
210 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
211 out_be32(&pci->piw[win_idx].piwar, piwar);
212 win_idx--;
213
214 hose->dma_window_base_cur = 0x00000000;
215 hose->dma_window_size = (resource_size_t)sz;
216 } else {
217 u64 paddr = 0;
218
219 /* Setup inbound memory window */
220 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
221 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
222 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
223 win_idx--;
224
225 paddr += 1ull << mem_log;
226 sz -= 1ull << mem_log;
227
228 if (sz) {
229 mem_log = __ilog2_u64(sz);
230 piwar |= (mem_log - 1);
231
232 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
233 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
234 out_be32(&pci->piw[win_idx].piwar, piwar);
235 win_idx--;
236
237 paddr += 1ull << mem_log;
238 }
239
240 hose->dma_window_base_cur = 0x00000000;
241 hose->dma_window_size = (resource_size_t)paddr;
242 }
243
244 if (hose->dma_window_size < mem) {
245 #ifndef CONFIG_SWIOTLB
246 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
247 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
248 name);
249 #endif
250 /* adjusting outbound windows could reclaim space in mem map */
251 if (paddr_hi < 0xffffffffull)
252 pr_warning("%s: WARNING: Outbound window cfg leaves "
253 "gaps in memory map. Adjusting the memory map "
254 "could reduce unnecessary bounce buffering.\n",
255 name);
256
257 pr_info("%s: DMA window size is 0x%llx\n", name,
258 (u64)hose->dma_window_size);
259 }
260
261 iounmap(pci);
262 }
263
264 static void __init setup_pci_cmd(struct pci_controller *hose)
265 {
266 u16 cmd;
267 int cap_x;
268
269 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
270 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
271 | PCI_COMMAND_IO;
272 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
273
274 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
275 if (cap_x) {
276 int pci_x_cmd = cap_x + PCI_X_CMD;
277 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
278 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
279 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
280 } else {
281 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
282 }
283 }
284
285 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
286 {
287 struct pci_controller *hose = pci_bus_to_host(bus);
288 int i;
289
290 if ((bus->parent == hose->bus) &&
291 ((fsl_pcie_bus_fixup &&
292 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
293 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
294 {
295 for (i = 0; i < 4; ++i) {
296 struct resource *res = bus->resource[i];
297 struct resource *par = bus->parent->resource[i];
298 if (res) {
299 res->start = 0;
300 res->end = 0;
301 res->flags = 0;
302 }
303 if (res && par) {
304 res->start = par->start;
305 res->end = par->end;
306 res->flags = par->flags;
307 }
308 }
309 }
310 }
311
312 int __init fsl_add_bridge(struct device_node *dev, int is_primary)
313 {
314 int len;
315 struct pci_controller *hose;
316 struct resource rsrc;
317 const int *bus_range;
318
319 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
320
321 /* Fetch host bridge registers address */
322 if (of_address_to_resource(dev, 0, &rsrc)) {
323 printk(KERN_WARNING "Can't get pci register base!");
324 return -ENOMEM;
325 }
326
327 /* Get bus range if any */
328 bus_range = of_get_property(dev, "bus-range", &len);
329 if (bus_range == NULL || len < 2 * sizeof(int))
330 printk(KERN_WARNING "Can't get bus-range for %s, assume"
331 " bus 0\n", dev->full_name);
332
333 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
334 hose = pcibios_alloc_controller(dev);
335 if (!hose)
336 return -ENOMEM;
337
338 hose->first_busno = bus_range ? bus_range[0] : 0x0;
339 hose->last_busno = bus_range ? bus_range[1] : 0xff;
340
341 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
342 PPC_INDIRECT_TYPE_BIG_ENDIAN);
343 setup_pci_cmd(hose);
344
345 /* check PCI express link status */
346 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
347 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
348 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
349 if (fsl_pcie_check_link(hose))
350 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
351 }
352
353 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
354 "Firmware bus number: %d->%d\n",
355 (unsigned long long)rsrc.start, hose->first_busno,
356 hose->last_busno);
357
358 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
359 hose, hose->cfg_addr, hose->cfg_data);
360
361 /* Interpret the "ranges" property */
362 /* This also maps the I/O region and sets isa_io/mem_base */
363 pci_process_bridge_OF_ranges(hose, dev, is_primary);
364
365 /* Setup PEX window registers */
366 setup_pci_atmu(hose, &rsrc);
367
368 return 0;
369 }
370
371 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548E, quirk_fsl_pcie_header);
372 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8548, quirk_fsl_pcie_header);
373 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543E, quirk_fsl_pcie_header);
374 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8543, quirk_fsl_pcie_header);
375 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8547E, quirk_fsl_pcie_header);
376 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545E, quirk_fsl_pcie_header);
377 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8545, quirk_fsl_pcie_header);
378 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569E, quirk_fsl_pcie_header);
379 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8569, quirk_fsl_pcie_header);
380 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568E, quirk_fsl_pcie_header);
381 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8568, quirk_fsl_pcie_header);
382 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567E, quirk_fsl_pcie_header);
383 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8567, quirk_fsl_pcie_header);
384 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533E, quirk_fsl_pcie_header);
385 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8533, quirk_fsl_pcie_header);
386 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544E, quirk_fsl_pcie_header);
387 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8544, quirk_fsl_pcie_header);
388 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572E, quirk_fsl_pcie_header);
389 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8572, quirk_fsl_pcie_header);
390 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536E, quirk_fsl_pcie_header);
391 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8536, quirk_fsl_pcie_header);
392 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641, quirk_fsl_pcie_header);
393 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8641D, quirk_fsl_pcie_header);
394 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8610, quirk_fsl_pcie_header);
395 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011E, quirk_fsl_pcie_header);
396 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1011, quirk_fsl_pcie_header);
397 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013E, quirk_fsl_pcie_header);
398 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1013, quirk_fsl_pcie_header);
399 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020E, quirk_fsl_pcie_header);
400 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1020, quirk_fsl_pcie_header);
401 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022E, quirk_fsl_pcie_header);
402 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P1022, quirk_fsl_pcie_header);
403 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010E, quirk_fsl_pcie_header);
404 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2010, quirk_fsl_pcie_header);
405 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020E, quirk_fsl_pcie_header);
406 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P2020, quirk_fsl_pcie_header);
407 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040E, quirk_fsl_pcie_header);
408 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4040, quirk_fsl_pcie_header);
409 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080E, quirk_fsl_pcie_header);
410 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_P4080, quirk_fsl_pcie_header);
411 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
412
413 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
414 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314E, quirk_fsl_pcie_header);
415 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8314, quirk_fsl_pcie_header);
416 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315E, quirk_fsl_pcie_header);
417 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8315, quirk_fsl_pcie_header);
418 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377E, quirk_fsl_pcie_header);
419 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8377, quirk_fsl_pcie_header);
420 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378E, quirk_fsl_pcie_header);
421 DECLARE_PCI_FIXUP_HEADER(0x1957, PCI_DEVICE_ID_MPC8378, quirk_fsl_pcie_header);
422
423 struct mpc83xx_pcie_priv {
424 void __iomem *cfg_type0;
425 void __iomem *cfg_type1;
426 u32 dev_base;
427 };
428
429 /*
430 * With the convention of u-boot, the PCIE outbound window 0 serves
431 * as configuration transactions outbound.
432 */
433 #define PEX_OUTWIN0_BAR 0xCA4
434 #define PEX_OUTWIN0_TAL 0xCA8
435 #define PEX_OUTWIN0_TAH 0xCAC
436
437 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
438 {
439 struct pci_controller *hose = pci_bus_to_host(bus);
440
441 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
442 return PCIBIOS_DEVICE_NOT_FOUND;
443 /*
444 * Workaround for the HW bug: for Type 0 configure transactions the
445 * PCI-E controller does not check the device number bits and just
446 * assumes that the device number bits are 0.
447 */
448 if (bus->number == hose->first_busno ||
449 bus->primary == hose->first_busno) {
450 if (devfn & 0xf8)
451 return PCIBIOS_DEVICE_NOT_FOUND;
452 }
453
454 if (ppc_md.pci_exclude_device) {
455 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
456 return PCIBIOS_DEVICE_NOT_FOUND;
457 }
458
459 return PCIBIOS_SUCCESSFUL;
460 }
461
462 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
463 unsigned int devfn, int offset)
464 {
465 struct pci_controller *hose = pci_bus_to_host(bus);
466 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
467 u32 dev_base = bus->number << 24 | devfn << 16;
468 int ret;
469
470 ret = mpc83xx_pcie_exclude_device(bus, devfn);
471 if (ret)
472 return NULL;
473
474 offset &= 0xfff;
475
476 /* Type 0 */
477 if (bus->number == hose->first_busno)
478 return pcie->cfg_type0 + offset;
479
480 if (pcie->dev_base == dev_base)
481 goto mapped;
482
483 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
484
485 pcie->dev_base = dev_base;
486 mapped:
487 return pcie->cfg_type1 + offset;
488 }
489
490 static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
491 int offset, int len, u32 *val)
492 {
493 void __iomem *cfg_addr;
494
495 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
496 if (!cfg_addr)
497 return PCIBIOS_DEVICE_NOT_FOUND;
498
499 switch (len) {
500 case 1:
501 *val = in_8(cfg_addr);
502 break;
503 case 2:
504 *val = in_le16(cfg_addr);
505 break;
506 default:
507 *val = in_le32(cfg_addr);
508 break;
509 }
510
511 return PCIBIOS_SUCCESSFUL;
512 }
513
514 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
515 int offset, int len, u32 val)
516 {
517 struct pci_controller *hose = pci_bus_to_host(bus);
518 void __iomem *cfg_addr;
519
520 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
521 if (!cfg_addr)
522 return PCIBIOS_DEVICE_NOT_FOUND;
523
524 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
525 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
526 val &= 0xffffff00;
527
528 switch (len) {
529 case 1:
530 out_8(cfg_addr, val);
531 break;
532 case 2:
533 out_le16(cfg_addr, val);
534 break;
535 default:
536 out_le32(cfg_addr, val);
537 break;
538 }
539
540 return PCIBIOS_SUCCESSFUL;
541 }
542
543 static struct pci_ops mpc83xx_pcie_ops = {
544 .read = mpc83xx_pcie_read_config,
545 .write = mpc83xx_pcie_write_config,
546 };
547
548 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
549 struct resource *reg)
550 {
551 struct mpc83xx_pcie_priv *pcie;
552 u32 cfg_bar;
553 int ret = -ENOMEM;
554
555 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
556 if (!pcie)
557 return ret;
558
559 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
560 if (!pcie->cfg_type0)
561 goto err0;
562
563 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
564 if (!cfg_bar) {
565 /* PCI-E isn't configured. */
566 ret = -ENODEV;
567 goto err1;
568 }
569
570 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
571 if (!pcie->cfg_type1)
572 goto err1;
573
574 WARN_ON(hose->dn->data);
575 hose->dn->data = pcie;
576 hose->ops = &mpc83xx_pcie_ops;
577
578 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
579 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
580
581 if (fsl_pcie_check_link(hose))
582 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
583
584 return 0;
585 err1:
586 iounmap(pcie->cfg_type0);
587 err0:
588 kfree(pcie);
589 return ret;
590
591 }
592
593 int __init mpc83xx_add_bridge(struct device_node *dev)
594 {
595 int ret;
596 int len;
597 struct pci_controller *hose;
598 struct resource rsrc_reg;
599 struct resource rsrc_cfg;
600 const int *bus_range;
601 int primary;
602
603 if (!of_device_is_available(dev)) {
604 pr_warning("%s: disabled by the firmware.\n",
605 dev->full_name);
606 return -ENODEV;
607 }
608 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
609
610 /* Fetch host bridge registers address */
611 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
612 printk(KERN_WARNING "Can't get pci register base!\n");
613 return -ENOMEM;
614 }
615
616 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
617
618 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
619 printk(KERN_WARNING
620 "No pci config register base in dev tree, "
621 "using default\n");
622 /*
623 * MPC83xx supports up to two host controllers
624 * one at 0x8500 has config space registers at 0x8300
625 * one at 0x8600 has config space registers at 0x8380
626 */
627 if ((rsrc_reg.start & 0xfffff) == 0x8500)
628 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
629 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
630 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
631 }
632 /*
633 * Controller at offset 0x8500 is primary
634 */
635 if ((rsrc_reg.start & 0xfffff) == 0x8500)
636 primary = 1;
637 else
638 primary = 0;
639
640 /* Get bus range if any */
641 bus_range = of_get_property(dev, "bus-range", &len);
642 if (bus_range == NULL || len < 2 * sizeof(int)) {
643 printk(KERN_WARNING "Can't get bus-range for %s, assume"
644 " bus 0\n", dev->full_name);
645 }
646
647 ppc_pci_add_flags(PPC_PCI_REASSIGN_ALL_BUS);
648 hose = pcibios_alloc_controller(dev);
649 if (!hose)
650 return -ENOMEM;
651
652 hose->first_busno = bus_range ? bus_range[0] : 0;
653 hose->last_busno = bus_range ? bus_range[1] : 0xff;
654
655 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
656 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
657 if (ret)
658 goto err0;
659 } else {
660 setup_indirect_pci(hose, rsrc_cfg.start,
661 rsrc_cfg.start + 4, 0);
662 }
663
664 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
665 "Firmware bus number: %d->%d\n",
666 (unsigned long long)rsrc_reg.start, hose->first_busno,
667 hose->last_busno);
668
669 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
670 hose, hose->cfg_addr, hose->cfg_data);
671
672 /* Interpret the "ranges" property */
673 /* This also maps the I/O region and sets isa_io/mem_base */
674 pci_process_bridge_OF_ranges(hose, dev, primary);
675
676 return 0;
677 err0:
678 pcibios_free_controller(hose);
679 return ret;
680 }
681 #endif /* CONFIG_PPC_83xx */
WandBoard kernel