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Merge branch 'upstream'
[wandboard.git] / drivers / net / bnx2.c
blob11d25231822112b08fc478e64fea577b983a12e7
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12 #include "bnx2.h"
13 #include "bnx2_fw.h"
14
15 #define DRV_MODULE_NAME "bnx2"
16 #define PFX DRV_MODULE_NAME ": "
17 #define DRV_MODULE_VERSION "1.2.21"
18 #define DRV_MODULE_RELDATE "September 7, 2005"
19
20 #define RUN_AT(x) (jiffies + (x))
21
22 /* Time in jiffies before concluding the transmitter is hung. */
23 #define TX_TIMEOUT (5*HZ)
24
25 static char version[] __devinitdata =
26 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
29 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
30 MODULE_LICENSE("GPL");
31 MODULE_VERSION(DRV_MODULE_VERSION);
32
33 static int disable_msi = 0;
34
35 module_param(disable_msi, int, 0);
36 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38 typedef enum {
39 BCM5706 = 0,
40 NC370T,
41 NC370I,
42 BCM5706S,
43 NC370F,
44 } board_t;
45
46 /* indexed by board_t, above */
47 static struct {
48 char *name;
49 } board_info[] __devinitdata = {
50 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
51 { "HP NC370T Multifunction Gigabit Server Adapter" },
52 { "HP NC370i Multifunction Gigabit Server Adapter" },
53 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
54 { "HP NC370F Multifunction Gigabit Server Adapter" },
55 };
56
57 static struct pci_device_id bnx2_pci_tbl[] = {
58 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
59 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
60 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
61 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
62 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
63 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
64 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
65 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
66 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
67 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
68 { 0, }
69 };
70
71 static struct flash_spec flash_table[] =
72 {
73 /* Slow EEPROM */
74 {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
75 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
76 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
77 "EEPROM - slow"},
78 /* Fast EEPROM */
79 {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
80 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
81 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
82 "EEPROM - fast"},
83 /* ATMEL AT45DB011B (buffered flash) */
84 {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
85 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
86 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
87 "Buffered flash"},
88 /* Saifun SA25F005 (non-buffered flash) */
89 /* strap, cfg1, & write1 need updates */
90 {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
91 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
92 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
93 "Non-buffered flash (64kB)"},
94 /* Saifun SA25F010 (non-buffered flash) */
95 /* strap, cfg1, & write1 need updates */
96 {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
97 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
98 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
99 "Non-buffered flash (128kB)"},
100 /* Saifun SA25F020 (non-buffered flash) */
101 /* strap, cfg1, & write1 need updates */
102 {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
103 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
104 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
105 "Non-buffered flash (256kB)"},
106 };
107
108 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
109
110 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
111 {
112 u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
113
114 if (diff > MAX_TX_DESC_CNT)
115 diff = (diff & MAX_TX_DESC_CNT) - 1;
116 return (bp->tx_ring_size - diff);
117 }
118
119 static u32
120 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
121 {
122 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
123 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
124 }
125
126 static void
127 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
128 {
129 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
130 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
131 }
132
133 static void
134 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
135 {
136 offset += cid_addr;
137 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
138 REG_WR(bp, BNX2_CTX_DATA, val);
139 }
140
141 static int
142 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
143 {
144 u32 val1;
145 int i, ret;
146
147 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
148 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
149 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
150
151 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
152 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
153
154 udelay(40);
155 }
156
157 val1 = (bp->phy_addr << 21) | (reg << 16) |
158 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
159 BNX2_EMAC_MDIO_COMM_START_BUSY;
160 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
161
162 for (i = 0; i < 50; i++) {
163 udelay(10);
164
165 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
166 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
167 udelay(5);
168
169 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
170 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
171
172 break;
173 }
174 }
175
176 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
177 *val = 0x0;
178 ret = -EBUSY;
179 }
180 else {
181 *val = val1;
182 ret = 0;
183 }
184
185 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
186 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
187 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
188
189 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
190 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
191
192 udelay(40);
193 }
194
195 return ret;
196 }
197
198 static int
199 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
200 {
201 u32 val1;
202 int i, ret;
203
204 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
205 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
206 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
207
208 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
209 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
210
211 udelay(40);
212 }
213
214 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
215 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
216 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
217 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
218
219 for (i = 0; i < 50; i++) {
220 udelay(10);
221
222 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
223 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
224 udelay(5);
225 break;
226 }
227 }
228
229 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
230 ret = -EBUSY;
231 else
232 ret = 0;
233
234 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
235 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
236 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
237
238 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
239 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
240
241 udelay(40);
242 }
243
244 return ret;
245 }
246
247 static void
248 bnx2_disable_int(struct bnx2 *bp)
249 {
250 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
251 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
252 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
253 }
254
255 static void
256 bnx2_enable_int(struct bnx2 *bp)
257 {
258 u32 val;
259
260 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
261 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
262
263 val = REG_RD(bp, BNX2_HC_COMMAND);
264 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
265 }
266
267 static void
268 bnx2_disable_int_sync(struct bnx2 *bp)
269 {
270 atomic_inc(&bp->intr_sem);
271 bnx2_disable_int(bp);
272 synchronize_irq(bp->pdev->irq);
273 }
274
275 static void
276 bnx2_netif_stop(struct bnx2 *bp)
277 {
278 bnx2_disable_int_sync(bp);
279 if (netif_running(bp->dev)) {
280 netif_poll_disable(bp->dev);
281 netif_tx_disable(bp->dev);
282 bp->dev->trans_start = jiffies; /* prevent tx timeout */
283 }
284 }
285
286 static void
287 bnx2_netif_start(struct bnx2 *bp)
288 {
289 if (atomic_dec_and_test(&bp->intr_sem)) {
290 if (netif_running(bp->dev)) {
291 netif_wake_queue(bp->dev);
292 netif_poll_enable(bp->dev);
293 bnx2_enable_int(bp);
294 }
295 }
296 }
297
298 static void
299 bnx2_free_mem(struct bnx2 *bp)
300 {
301 if (bp->stats_blk) {
302 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
303 bp->stats_blk, bp->stats_blk_mapping);
304 bp->stats_blk = NULL;
305 }
306 if (bp->status_blk) {
307 pci_free_consistent(bp->pdev, sizeof(struct status_block),
308 bp->status_blk, bp->status_blk_mapping);
309 bp->status_blk = NULL;
310 }
311 if (bp->tx_desc_ring) {
312 pci_free_consistent(bp->pdev,
313 sizeof(struct tx_bd) * TX_DESC_CNT,
314 bp->tx_desc_ring, bp->tx_desc_mapping);
315 bp->tx_desc_ring = NULL;
316 }
317 kfree(bp->tx_buf_ring);
318 bp->tx_buf_ring = NULL;
319 if (bp->rx_desc_ring) {
320 pci_free_consistent(bp->pdev,
321 sizeof(struct rx_bd) * RX_DESC_CNT,
322 bp->rx_desc_ring, bp->rx_desc_mapping);
323 bp->rx_desc_ring = NULL;
324 }
325 kfree(bp->rx_buf_ring);
326 bp->rx_buf_ring = NULL;
327 }
328
329 static int
330 bnx2_alloc_mem(struct bnx2 *bp)
331 {
332 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
333 GFP_KERNEL);
334 if (bp->tx_buf_ring == NULL)
335 return -ENOMEM;
336
337 memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
338 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
339 sizeof(struct tx_bd) *
340 TX_DESC_CNT,
341 &bp->tx_desc_mapping);
342 if (bp->tx_desc_ring == NULL)
343 goto alloc_mem_err;
344
345 bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
346 GFP_KERNEL);
347 if (bp->rx_buf_ring == NULL)
348 goto alloc_mem_err;
349
350 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
351 bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
352 sizeof(struct rx_bd) *
353 RX_DESC_CNT,
354 &bp->rx_desc_mapping);
355 if (bp->rx_desc_ring == NULL)
356 goto alloc_mem_err;
357
358 bp->status_blk = pci_alloc_consistent(bp->pdev,
359 sizeof(struct status_block),
360 &bp->status_blk_mapping);
361 if (bp->status_blk == NULL)
362 goto alloc_mem_err;
363
364 memset(bp->status_blk, 0, sizeof(struct status_block));
365
366 bp->stats_blk = pci_alloc_consistent(bp->pdev,
367 sizeof(struct statistics_block),
368 &bp->stats_blk_mapping);
369 if (bp->stats_blk == NULL)
370 goto alloc_mem_err;
371
372 memset(bp->stats_blk, 0, sizeof(struct statistics_block));
373
374 return 0;
375
376 alloc_mem_err:
377 bnx2_free_mem(bp);
378 return -ENOMEM;
379 }
380
381 static void
382 bnx2_report_link(struct bnx2 *bp)
383 {
384 if (bp->link_up) {
385 netif_carrier_on(bp->dev);
386 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
387
388 printk("%d Mbps ", bp->line_speed);
389
390 if (bp->duplex == DUPLEX_FULL)
391 printk("full duplex");
392 else
393 printk("half duplex");
394
395 if (bp->flow_ctrl) {
396 if (bp->flow_ctrl & FLOW_CTRL_RX) {
397 printk(", receive ");
398 if (bp->flow_ctrl & FLOW_CTRL_TX)
399 printk("& transmit ");
400 }
401 else {
402 printk(", transmit ");
403 }
404 printk("flow control ON");
405 }
406 printk("\n");
407 }
408 else {
409 netif_carrier_off(bp->dev);
410 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
411 }
412 }
413
414 static void
415 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
416 {
417 u32 local_adv, remote_adv;
418
419 bp->flow_ctrl = 0;
420 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
421 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
422
423 if (bp->duplex == DUPLEX_FULL) {
424 bp->flow_ctrl = bp->req_flow_ctrl;
425 }
426 return;
427 }
428
429 if (bp->duplex != DUPLEX_FULL) {
430 return;
431 }
432
433 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
434 bnx2_read_phy(bp, MII_LPA, &remote_adv);
435
436 if (bp->phy_flags & PHY_SERDES_FLAG) {
437 u32 new_local_adv = 0;
438 u32 new_remote_adv = 0;
439
440 if (local_adv & ADVERTISE_1000XPAUSE)
441 new_local_adv |= ADVERTISE_PAUSE_CAP;
442 if (local_adv & ADVERTISE_1000XPSE_ASYM)
443 new_local_adv |= ADVERTISE_PAUSE_ASYM;
444 if (remote_adv & ADVERTISE_1000XPAUSE)
445 new_remote_adv |= ADVERTISE_PAUSE_CAP;
446 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
447 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
448
449 local_adv = new_local_adv;
450 remote_adv = new_remote_adv;
451 }
452
453 /* See Table 28B-3 of 802.3ab-1999 spec. */
454 if (local_adv & ADVERTISE_PAUSE_CAP) {
455 if(local_adv & ADVERTISE_PAUSE_ASYM) {
456 if (remote_adv & ADVERTISE_PAUSE_CAP) {
457 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
458 }
459 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
460 bp->flow_ctrl = FLOW_CTRL_RX;
461 }
462 }
463 else {
464 if (remote_adv & ADVERTISE_PAUSE_CAP) {
465 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
466 }
467 }
468 }
469 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
470 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
471 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
472
473 bp->flow_ctrl = FLOW_CTRL_TX;
474 }
475 }
476 }
477
478 static int
479 bnx2_serdes_linkup(struct bnx2 *bp)
480 {
481 u32 bmcr, local_adv, remote_adv, common;
482
483 bp->link_up = 1;
484 bp->line_speed = SPEED_1000;
485
486 bnx2_read_phy(bp, MII_BMCR, &bmcr);
487 if (bmcr & BMCR_FULLDPLX) {
488 bp->duplex = DUPLEX_FULL;
489 }
490 else {
491 bp->duplex = DUPLEX_HALF;
492 }
493
494 if (!(bmcr & BMCR_ANENABLE)) {
495 return 0;
496 }
497
498 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
499 bnx2_read_phy(bp, MII_LPA, &remote_adv);
500
501 common = local_adv & remote_adv;
502 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
503
504 if (common & ADVERTISE_1000XFULL) {
505 bp->duplex = DUPLEX_FULL;
506 }
507 else {
508 bp->duplex = DUPLEX_HALF;
509 }
510 }
511
512 return 0;
513 }
514
515 static int
516 bnx2_copper_linkup(struct bnx2 *bp)
517 {
518 u32 bmcr;
519
520 bnx2_read_phy(bp, MII_BMCR, &bmcr);
521 if (bmcr & BMCR_ANENABLE) {
522 u32 local_adv, remote_adv, common;
523
524 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
525 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
526
527 common = local_adv & (remote_adv >> 2);
528 if (common & ADVERTISE_1000FULL) {
529 bp->line_speed = SPEED_1000;
530 bp->duplex = DUPLEX_FULL;
531 }
532 else if (common & ADVERTISE_1000HALF) {
533 bp->line_speed = SPEED_1000;
534 bp->duplex = DUPLEX_HALF;
535 }
536 else {
537 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
538 bnx2_read_phy(bp, MII_LPA, &remote_adv);
539
540 common = local_adv & remote_adv;
541 if (common & ADVERTISE_100FULL) {
542 bp->line_speed = SPEED_100;
543 bp->duplex = DUPLEX_FULL;
544 }
545 else if (common & ADVERTISE_100HALF) {
546 bp->line_speed = SPEED_100;
547 bp->duplex = DUPLEX_HALF;
548 }
549 else if (common & ADVERTISE_10FULL) {
550 bp->line_speed = SPEED_10;
551 bp->duplex = DUPLEX_FULL;
552 }
553 else if (common & ADVERTISE_10HALF) {
554 bp->line_speed = SPEED_10;
555 bp->duplex = DUPLEX_HALF;
556 }
557 else {
558 bp->line_speed = 0;
559 bp->link_up = 0;
560 }
561 }
562 }
563 else {
564 if (bmcr & BMCR_SPEED100) {
565 bp->line_speed = SPEED_100;
566 }
567 else {
568 bp->line_speed = SPEED_10;
569 }
570 if (bmcr & BMCR_FULLDPLX) {
571 bp->duplex = DUPLEX_FULL;
572 }
573 else {
574 bp->duplex = DUPLEX_HALF;
575 }
576 }
577
578 return 0;
579 }
580
581 static int
582 bnx2_set_mac_link(struct bnx2 *bp)
583 {
584 u32 val;
585
586 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
587 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
588 (bp->duplex == DUPLEX_HALF)) {
589 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
590 }
591
592 /* Configure the EMAC mode register. */
593 val = REG_RD(bp, BNX2_EMAC_MODE);
594
595 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
596 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK);
597
598 if (bp->link_up) {
599 if (bp->line_speed != SPEED_1000)
600 val |= BNX2_EMAC_MODE_PORT_MII;
601 else
602 val |= BNX2_EMAC_MODE_PORT_GMII;
603 }
604 else {
605 val |= BNX2_EMAC_MODE_PORT_GMII;
606 }
607
608 /* Set the MAC to operate in the appropriate duplex mode. */
609 if (bp->duplex == DUPLEX_HALF)
610 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
611 REG_WR(bp, BNX2_EMAC_MODE, val);
612
613 /* Enable/disable rx PAUSE. */
614 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
615
616 if (bp->flow_ctrl & FLOW_CTRL_RX)
617 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
618 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
619
620 /* Enable/disable tx PAUSE. */
621 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
622 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
623
624 if (bp->flow_ctrl & FLOW_CTRL_TX)
625 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
626 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
627
628 /* Acknowledge the interrupt. */
629 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
630
631 return 0;
632 }
633
634 static int
635 bnx2_set_link(struct bnx2 *bp)
636 {
637 u32 bmsr;
638 u8 link_up;
639
640 if (bp->loopback == MAC_LOOPBACK) {
641 bp->link_up = 1;
642 return 0;
643 }
644
645 link_up = bp->link_up;
646
647 bnx2_read_phy(bp, MII_BMSR, &bmsr);
648 bnx2_read_phy(bp, MII_BMSR, &bmsr);
649
650 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
651 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
652 u32 val;
653
654 val = REG_RD(bp, BNX2_EMAC_STATUS);
655 if (val & BNX2_EMAC_STATUS_LINK)
656 bmsr |= BMSR_LSTATUS;
657 else
658 bmsr &= ~BMSR_LSTATUS;
659 }
660
661 if (bmsr & BMSR_LSTATUS) {
662 bp->link_up = 1;
663
664 if (bp->phy_flags & PHY_SERDES_FLAG) {
665 bnx2_serdes_linkup(bp);
666 }
667 else {
668 bnx2_copper_linkup(bp);
669 }
670 bnx2_resolve_flow_ctrl(bp);
671 }
672 else {
673 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
674 (bp->autoneg & AUTONEG_SPEED)) {
675
676 u32 bmcr;
677
678 bnx2_read_phy(bp, MII_BMCR, &bmcr);
679 if (!(bmcr & BMCR_ANENABLE)) {
680 bnx2_write_phy(bp, MII_BMCR, bmcr |
681 BMCR_ANENABLE);
682 }
683 }
684 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
685 bp->link_up = 0;
686 }
687
688 if (bp->link_up != link_up) {
689 bnx2_report_link(bp);
690 }
691
692 bnx2_set_mac_link(bp);
693
694 return 0;
695 }
696
697 static int
698 bnx2_reset_phy(struct bnx2 *bp)
699 {
700 int i;
701 u32 reg;
702
703 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
704
705 #define PHY_RESET_MAX_WAIT 100
706 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
707 udelay(10);
708
709 bnx2_read_phy(bp, MII_BMCR, &reg);
710 if (!(reg & BMCR_RESET)) {
711 udelay(20);
712 break;
713 }
714 }
715 if (i == PHY_RESET_MAX_WAIT) {
716 return -EBUSY;
717 }
718 return 0;
719 }
720
721 static u32
722 bnx2_phy_get_pause_adv(struct bnx2 *bp)
723 {
724 u32 adv = 0;
725
726 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
727 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
728
729 if (bp->phy_flags & PHY_SERDES_FLAG) {
730 adv = ADVERTISE_1000XPAUSE;
731 }
732 else {
733 adv = ADVERTISE_PAUSE_CAP;
734 }
735 }
736 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
737 if (bp->phy_flags & PHY_SERDES_FLAG) {
738 adv = ADVERTISE_1000XPSE_ASYM;
739 }
740 else {
741 adv = ADVERTISE_PAUSE_ASYM;
742 }
743 }
744 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
745 if (bp->phy_flags & PHY_SERDES_FLAG) {
746 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
747 }
748 else {
749 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
750 }
751 }
752 return adv;
753 }
754
755 static int
756 bnx2_setup_serdes_phy(struct bnx2 *bp)
757 {
758 u32 adv, bmcr;
759 u32 new_adv = 0;
760
761 if (!(bp->autoneg & AUTONEG_SPEED)) {
762 u32 new_bmcr;
763
764 bnx2_read_phy(bp, MII_BMCR, &bmcr);
765 new_bmcr = bmcr & ~BMCR_ANENABLE;
766 new_bmcr |= BMCR_SPEED1000;
767 if (bp->req_duplex == DUPLEX_FULL) {
768 new_bmcr |= BMCR_FULLDPLX;
769 }
770 else {
771 new_bmcr &= ~BMCR_FULLDPLX;
772 }
773 if (new_bmcr != bmcr) {
774 /* Force a link down visible on the other side */
775 if (bp->link_up) {
776 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
777 adv &= ~(ADVERTISE_1000XFULL |
778 ADVERTISE_1000XHALF);
779 bnx2_write_phy(bp, MII_ADVERTISE, adv);
780 bnx2_write_phy(bp, MII_BMCR, bmcr |
781 BMCR_ANRESTART | BMCR_ANENABLE);
782
783 bp->link_up = 0;
784 netif_carrier_off(bp->dev);
785 }
786 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
787 }
788 return 0;
789 }
790
791 if (bp->advertising & ADVERTISED_1000baseT_Full)
792 new_adv |= ADVERTISE_1000XFULL;
793
794 new_adv |= bnx2_phy_get_pause_adv(bp);
795
796 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
797 bnx2_read_phy(bp, MII_BMCR, &bmcr);
798
799 bp->serdes_an_pending = 0;
800 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
801 /* Force a link down visible on the other side */
802 if (bp->link_up) {
803 int i;
804
805 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
806 for (i = 0; i < 110; i++) {
807 udelay(100);
808 }
809 }
810
811 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
812 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
813 BMCR_ANENABLE);
814 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
815 /* Speed up link-up time when the link partner
816 * does not autonegotiate which is very common
817 * in blade servers. Some blade servers use
818 * IPMI for kerboard input and it's important
819 * to minimize link disruptions. Autoneg. involves
820 * exchanging base pages plus 3 next pages and
821 * normally completes in about 120 msec.
822 */
823 bp->current_interval = SERDES_AN_TIMEOUT;
824 bp->serdes_an_pending = 1;
825 mod_timer(&bp->timer, jiffies + bp->current_interval);
826 }
827 }
828
829 return 0;
830 }
831
832 #define ETHTOOL_ALL_FIBRE_SPEED \
833 (ADVERTISED_1000baseT_Full)
834
835 #define ETHTOOL_ALL_COPPER_SPEED \
836 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
837 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
838 ADVERTISED_1000baseT_Full)
839
840 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
841 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
842
843 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
844
845 static int
846 bnx2_setup_copper_phy(struct bnx2 *bp)
847 {
848 u32 bmcr;
849 u32 new_bmcr;
850
851 bnx2_read_phy(bp, MII_BMCR, &bmcr);
852
853 if (bp->autoneg & AUTONEG_SPEED) {
854 u32 adv_reg, adv1000_reg;
855 u32 new_adv_reg = 0;
856 u32 new_adv1000_reg = 0;
857
858 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
859 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
860 ADVERTISE_PAUSE_ASYM);
861
862 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
863 adv1000_reg &= PHY_ALL_1000_SPEED;
864
865 if (bp->advertising & ADVERTISED_10baseT_Half)
866 new_adv_reg |= ADVERTISE_10HALF;
867 if (bp->advertising & ADVERTISED_10baseT_Full)
868 new_adv_reg |= ADVERTISE_10FULL;
869 if (bp->advertising & ADVERTISED_100baseT_Half)
870 new_adv_reg |= ADVERTISE_100HALF;
871 if (bp->advertising & ADVERTISED_100baseT_Full)
872 new_adv_reg |= ADVERTISE_100FULL;
873 if (bp->advertising & ADVERTISED_1000baseT_Full)
874 new_adv1000_reg |= ADVERTISE_1000FULL;
875
876 new_adv_reg |= ADVERTISE_CSMA;
877
878 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
879
880 if ((adv1000_reg != new_adv1000_reg) ||
881 (adv_reg != new_adv_reg) ||
882 ((bmcr & BMCR_ANENABLE) == 0)) {
883
884 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
885 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
886 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
887 BMCR_ANENABLE);
888 }
889 else if (bp->link_up) {
890 /* Flow ctrl may have changed from auto to forced */
891 /* or vice-versa. */
892
893 bnx2_resolve_flow_ctrl(bp);
894 bnx2_set_mac_link(bp);
895 }
896 return 0;
897 }
898
899 new_bmcr = 0;
900 if (bp->req_line_speed == SPEED_100) {
901 new_bmcr |= BMCR_SPEED100;
902 }
903 if (bp->req_duplex == DUPLEX_FULL) {
904 new_bmcr |= BMCR_FULLDPLX;
905 }
906 if (new_bmcr != bmcr) {
907 u32 bmsr;
908 int i = 0;
909
910 bnx2_read_phy(bp, MII_BMSR, &bmsr);
911 bnx2_read_phy(bp, MII_BMSR, &bmsr);
912
913 if (bmsr & BMSR_LSTATUS) {
914 /* Force link down */
915 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
916 do {
917 udelay(100);
918 bnx2_read_phy(bp, MII_BMSR, &bmsr);
919 bnx2_read_phy(bp, MII_BMSR, &bmsr);
920 i++;
921 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
922 }
923
924 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
925
926 /* Normally, the new speed is setup after the link has
927 * gone down and up again. In some cases, link will not go
928 * down so we need to set up the new speed here.
929 */
930 if (bmsr & BMSR_LSTATUS) {
931 bp->line_speed = bp->req_line_speed;
932 bp->duplex = bp->req_duplex;
933 bnx2_resolve_flow_ctrl(bp);
934 bnx2_set_mac_link(bp);
935 }
936 }
937 return 0;
938 }
939
940 static int
941 bnx2_setup_phy(struct bnx2 *bp)
942 {
943 if (bp->loopback == MAC_LOOPBACK)
944 return 0;
945
946 if (bp->phy_flags & PHY_SERDES_FLAG) {
947 return (bnx2_setup_serdes_phy(bp));
948 }
949 else {
950 return (bnx2_setup_copper_phy(bp));
951 }
952 }
953
954 static int
955 bnx2_init_serdes_phy(struct bnx2 *bp)
956 {
957 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
958
959 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
960 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
961 }
962
963 if (bp->dev->mtu > 1500) {
964 u32 val;
965
966 /* Set extended packet length bit */
967 bnx2_write_phy(bp, 0x18, 0x7);
968 bnx2_read_phy(bp, 0x18, &val);
969 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
970
971 bnx2_write_phy(bp, 0x1c, 0x6c00);
972 bnx2_read_phy(bp, 0x1c, &val);
973 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
974 }
975 else {
976 u32 val;
977
978 bnx2_write_phy(bp, 0x18, 0x7);
979 bnx2_read_phy(bp, 0x18, &val);
980 bnx2_write_phy(bp, 0x18, val & ~0x4007);
981
982 bnx2_write_phy(bp, 0x1c, 0x6c00);
983 bnx2_read_phy(bp, 0x1c, &val);
984 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
985 }
986
987 return 0;
988 }
989
990 static int
991 bnx2_init_copper_phy(struct bnx2 *bp)
992 {
993 bp->phy_flags |= PHY_CRC_FIX_FLAG;
994
995 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
996 bnx2_write_phy(bp, 0x18, 0x0c00);
997 bnx2_write_phy(bp, 0x17, 0x000a);
998 bnx2_write_phy(bp, 0x15, 0x310b);
999 bnx2_write_phy(bp, 0x17, 0x201f);
1000 bnx2_write_phy(bp, 0x15, 0x9506);
1001 bnx2_write_phy(bp, 0x17, 0x401f);
1002 bnx2_write_phy(bp, 0x15, 0x14e2);
1003 bnx2_write_phy(bp, 0x18, 0x0400);
1004 }
1005
1006 if (bp->dev->mtu > 1500) {
1007 u32 val;
1008
1009 /* Set extended packet length bit */
1010 bnx2_write_phy(bp, 0x18, 0x7);
1011 bnx2_read_phy(bp, 0x18, &val);
1012 bnx2_write_phy(bp, 0x18, val | 0x4000);
1013
1014 bnx2_read_phy(bp, 0x10, &val);
1015 bnx2_write_phy(bp, 0x10, val | 0x1);
1016 }
1017 else {
1018 u32 val;
1019
1020 bnx2_write_phy(bp, 0x18, 0x7);
1021 bnx2_read_phy(bp, 0x18, &val);
1022 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1023
1024 bnx2_read_phy(bp, 0x10, &val);
1025 bnx2_write_phy(bp, 0x10, val & ~0x1);
1026 }
1027
1028 return 0;
1029 }
1030
1031
1032 static int
1033 bnx2_init_phy(struct bnx2 *bp)
1034 {
1035 u32 val;
1036 int rc = 0;
1037
1038 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1039 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1040
1041 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1042
1043 bnx2_reset_phy(bp);
1044
1045 bnx2_read_phy(bp, MII_PHYSID1, &val);
1046 bp->phy_id = val << 16;
1047 bnx2_read_phy(bp, MII_PHYSID2, &val);
1048 bp->phy_id |= val & 0xffff;
1049
1050 if (bp->phy_flags & PHY_SERDES_FLAG) {
1051 rc = bnx2_init_serdes_phy(bp);
1052 }
1053 else {
1054 rc = bnx2_init_copper_phy(bp);
1055 }
1056
1057 bnx2_setup_phy(bp);
1058
1059 return rc;
1060 }
1061
1062 static int
1063 bnx2_set_mac_loopback(struct bnx2 *bp)
1064 {
1065 u32 mac_mode;
1066
1067 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1068 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1069 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1070 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1071 bp->link_up = 1;
1072 return 0;
1073 }
1074
1075 static int
1076 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
1077 {
1078 int i;
1079 u32 val;
1080
1081 if (bp->fw_timed_out)
1082 return -EBUSY;
1083
1084 bp->fw_wr_seq++;
1085 msg_data |= bp->fw_wr_seq;
1086
1087 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1088
1089 /* wait for an acknowledgement. */
1090 for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
1091 udelay(5);
1092
1093 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
1094
1095 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1096 break;
1097 }
1098
1099 /* If we timed out, inform the firmware that this is the case. */
1100 if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
1101 ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
1102
1103 msg_data &= ~BNX2_DRV_MSG_CODE;
1104 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1105
1106 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1107
1108 bp->fw_timed_out = 1;
1109
1110 return -EBUSY;
1111 }
1112
1113 return 0;
1114 }
1115
1116 static void
1117 bnx2_init_context(struct bnx2 *bp)
1118 {
1119 u32 vcid;
1120
1121 vcid = 96;
1122 while (vcid) {
1123 u32 vcid_addr, pcid_addr, offset;
1124
1125 vcid--;
1126
1127 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1128 u32 new_vcid;
1129
1130 vcid_addr = GET_PCID_ADDR(vcid);
1131 if (vcid & 0x8) {
1132 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1133 }
1134 else {
1135 new_vcid = vcid;
1136 }
1137 pcid_addr = GET_PCID_ADDR(new_vcid);
1138 }
1139 else {
1140 vcid_addr = GET_CID_ADDR(vcid);
1141 pcid_addr = vcid_addr;
1142 }
1143
1144 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1145 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1146
1147 /* Zero out the context. */
1148 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1149 CTX_WR(bp, 0x00, offset, 0);
1150 }
1151
1152 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1153 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1154 }
1155 }
1156
1157 static int
1158 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1159 {
1160 u16 *good_mbuf;
1161 u32 good_mbuf_cnt;
1162 u32 val;
1163
1164 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1165 if (good_mbuf == NULL) {
1166 printk(KERN_ERR PFX "Failed to allocate memory in "
1167 "bnx2_alloc_bad_rbuf\n");
1168 return -ENOMEM;
1169 }
1170
1171 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1172 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1173
1174 good_mbuf_cnt = 0;
1175
1176 /* Allocate a bunch of mbufs and save the good ones in an array. */
1177 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1178 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1179 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1180
1181 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1182
1183 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1184
1185 /* The addresses with Bit 9 set are bad memory blocks. */
1186 if (!(val & (1 << 9))) {
1187 good_mbuf[good_mbuf_cnt] = (u16) val;
1188 good_mbuf_cnt++;
1189 }
1190
1191 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1192 }
1193
1194 /* Free the good ones back to the mbuf pool thus discarding
1195 * all the bad ones. */
1196 while (good_mbuf_cnt) {
1197 good_mbuf_cnt--;
1198
1199 val = good_mbuf[good_mbuf_cnt];
1200 val = (val << 9) | val | 1;
1201
1202 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1203 }
1204 kfree(good_mbuf);
1205 return 0;
1206 }
1207
1208 static void
1209 bnx2_set_mac_addr(struct bnx2 *bp)
1210 {
1211 u32 val;
1212 u8 *mac_addr = bp->dev->dev_addr;
1213
1214 val = (mac_addr[0] << 8) | mac_addr[1];
1215
1216 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1217
1218 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1219 (mac_addr[4] << 8) | mac_addr[5];
1220
1221 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1222 }
1223
1224 static inline int
1225 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1226 {
1227 struct sk_buff *skb;
1228 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1229 dma_addr_t mapping;
1230 struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1231 unsigned long align;
1232
1233 skb = dev_alloc_skb(bp->rx_buf_size);
1234 if (skb == NULL) {
1235 return -ENOMEM;
1236 }
1237
1238 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1239 skb_reserve(skb, 8 - align);
1240 }
1241
1242 skb->dev = bp->dev;
1243 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1244 PCI_DMA_FROMDEVICE);
1245
1246 rx_buf->skb = skb;
1247 pci_unmap_addr_set(rx_buf, mapping, mapping);
1248
1249 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1250 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1251
1252 bp->rx_prod_bseq += bp->rx_buf_use_size;
1253
1254 return 0;
1255 }
1256
1257 static void
1258 bnx2_phy_int(struct bnx2 *bp)
1259 {
1260 u32 new_link_state, old_link_state;
1261
1262 new_link_state = bp->status_blk->status_attn_bits &
1263 STATUS_ATTN_BITS_LINK_STATE;
1264 old_link_state = bp->status_blk->status_attn_bits_ack &
1265 STATUS_ATTN_BITS_LINK_STATE;
1266 if (new_link_state != old_link_state) {
1267 if (new_link_state) {
1268 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1269 STATUS_ATTN_BITS_LINK_STATE);
1270 }
1271 else {
1272 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1273 STATUS_ATTN_BITS_LINK_STATE);
1274 }
1275 bnx2_set_link(bp);
1276 }
1277 }
1278
1279 static void
1280 bnx2_tx_int(struct bnx2 *bp)
1281 {
1282 u16 hw_cons, sw_cons, sw_ring_cons;
1283 int tx_free_bd = 0;
1284
1285 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1286 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1287 hw_cons++;
1288 }
1289 sw_cons = bp->tx_cons;
1290
1291 while (sw_cons != hw_cons) {
1292 struct sw_bd *tx_buf;
1293 struct sk_buff *skb;
1294 int i, last;
1295
1296 sw_ring_cons = TX_RING_IDX(sw_cons);
1297
1298 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1299 skb = tx_buf->skb;
1300 #ifdef BCM_TSO
1301 /* partial BD completions possible with TSO packets */
1302 if (skb_shinfo(skb)->tso_size) {
1303 u16 last_idx, last_ring_idx;
1304
1305 last_idx = sw_cons +
1306 skb_shinfo(skb)->nr_frags + 1;
1307 last_ring_idx = sw_ring_cons +
1308 skb_shinfo(skb)->nr_frags + 1;
1309 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1310 last_idx++;
1311 }
1312 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1313 break;
1314 }
1315 }
1316 #endif
1317 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1318 skb_headlen(skb), PCI_DMA_TODEVICE);
1319
1320 tx_buf->skb = NULL;
1321 last = skb_shinfo(skb)->nr_frags;
1322
1323 for (i = 0; i < last; i++) {
1324 sw_cons = NEXT_TX_BD(sw_cons);
1325
1326 pci_unmap_page(bp->pdev,
1327 pci_unmap_addr(
1328 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1329 mapping),
1330 skb_shinfo(skb)->frags[i].size,
1331 PCI_DMA_TODEVICE);
1332 }
1333
1334 sw_cons = NEXT_TX_BD(sw_cons);
1335
1336 tx_free_bd += last + 1;
1337
1338 dev_kfree_skb_irq(skb);
1339
1340 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1341 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1342 hw_cons++;
1343 }
1344 }
1345
1346 bp->tx_cons = sw_cons;
1347
1348 if (unlikely(netif_queue_stopped(bp->dev))) {
1349 spin_lock(&bp->tx_lock);
1350 if ((netif_queue_stopped(bp->dev)) &&
1351 (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1352
1353 netif_wake_queue(bp->dev);
1354 }
1355 spin_unlock(&bp->tx_lock);
1356 }
1357 }
1358
1359 static inline void
1360 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1361 u16 cons, u16 prod)
1362 {
1363 struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1364 struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1365 struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1366 struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1367
1368 pci_dma_sync_single_for_device(bp->pdev,
1369 pci_unmap_addr(cons_rx_buf, mapping),
1370 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1371
1372 prod_rx_buf->skb = cons_rx_buf->skb;
1373 pci_unmap_addr_set(prod_rx_buf, mapping,
1374 pci_unmap_addr(cons_rx_buf, mapping));
1375
1376 memcpy(prod_bd, cons_bd, 8);
1377
1378 bp->rx_prod_bseq += bp->rx_buf_use_size;
1379
1380 }
1381
1382 static int
1383 bnx2_rx_int(struct bnx2 *bp, int budget)
1384 {
1385 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1386 struct l2_fhdr *rx_hdr;
1387 int rx_pkt = 0;
1388
1389 hw_cons = bp->status_blk->status_rx_quick_consumer_index0;
1390 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1391 hw_cons++;
1392 }
1393 sw_cons = bp->rx_cons;
1394 sw_prod = bp->rx_prod;
1395
1396 /* Memory barrier necessary as speculative reads of the rx
1397 * buffer can be ahead of the index in the status block
1398 */
1399 rmb();
1400 while (sw_cons != hw_cons) {
1401 unsigned int len;
1402 u16 status;
1403 struct sw_bd *rx_buf;
1404 struct sk_buff *skb;
1405
1406 sw_ring_cons = RX_RING_IDX(sw_cons);
1407 sw_ring_prod = RX_RING_IDX(sw_prod);
1408
1409 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1410 skb = rx_buf->skb;
1411 pci_dma_sync_single_for_cpu(bp->pdev,
1412 pci_unmap_addr(rx_buf, mapping),
1413 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1414
1415 rx_hdr = (struct l2_fhdr *) skb->data;
1416 len = rx_hdr->l2_fhdr_pkt_len - 4;
1417
1418 if (rx_hdr->l2_fhdr_errors &
1419 (L2_FHDR_ERRORS_BAD_CRC |
1420 L2_FHDR_ERRORS_PHY_DECODE |
1421 L2_FHDR_ERRORS_ALIGNMENT |
1422 L2_FHDR_ERRORS_TOO_SHORT |
1423 L2_FHDR_ERRORS_GIANT_FRAME)) {
1424
1425 goto reuse_rx;
1426 }
1427
1428 /* Since we don't have a jumbo ring, copy small packets
1429 * if mtu > 1500
1430 */
1431 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1432 struct sk_buff *new_skb;
1433
1434 new_skb = dev_alloc_skb(len + 2);
1435 if (new_skb == NULL)
1436 goto reuse_rx;
1437
1438 /* aligned copy */
1439 memcpy(new_skb->data,
1440 skb->data + bp->rx_offset - 2,
1441 len + 2);
1442
1443 skb_reserve(new_skb, 2);
1444 skb_put(new_skb, len);
1445 new_skb->dev = bp->dev;
1446
1447 bnx2_reuse_rx_skb(bp, skb,
1448 sw_ring_cons, sw_ring_prod);
1449
1450 skb = new_skb;
1451 }
1452 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1453 pci_unmap_single(bp->pdev,
1454 pci_unmap_addr(rx_buf, mapping),
1455 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1456
1457 skb_reserve(skb, bp->rx_offset);
1458 skb_put(skb, len);
1459 }
1460 else {
1461 reuse_rx:
1462 bnx2_reuse_rx_skb(bp, skb,
1463 sw_ring_cons, sw_ring_prod);
1464 goto next_rx;
1465 }
1466
1467 skb->protocol = eth_type_trans(skb, bp->dev);
1468
1469 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1470 (htons(skb->protocol) != 0x8100)) {
1471
1472 dev_kfree_skb_irq(skb);
1473 goto next_rx;
1474
1475 }
1476
1477 status = rx_hdr->l2_fhdr_status;
1478 skb->ip_summed = CHECKSUM_NONE;
1479 if (bp->rx_csum &&
1480 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1481 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1482
1483 u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1484
1485 if (cksum == 0xffff)
1486 skb->ip_summed = CHECKSUM_UNNECESSARY;
1487 }
1488
1489 #ifdef BCM_VLAN
1490 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1491 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1492 rx_hdr->l2_fhdr_vlan_tag);
1493 }
1494 else
1495 #endif
1496 netif_receive_skb(skb);
1497
1498 bp->dev->last_rx = jiffies;
1499 rx_pkt++;
1500
1501 next_rx:
1502 rx_buf->skb = NULL;
1503
1504 sw_cons = NEXT_RX_BD(sw_cons);
1505 sw_prod = NEXT_RX_BD(sw_prod);
1506
1507 if ((rx_pkt == budget))
1508 break;
1509 }
1510 bp->rx_cons = sw_cons;
1511 bp->rx_prod = sw_prod;
1512
1513 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1514
1515 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1516
1517 mmiowb();
1518
1519 return rx_pkt;
1520
1521 }
1522
1523 /* MSI ISR - The only difference between this and the INTx ISR
1524 * is that the MSI interrupt is always serviced.
1525 */
1526 static irqreturn_t
1527 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1528 {
1529 struct net_device *dev = dev_instance;
1530 struct bnx2 *bp = dev->priv;
1531
1532 prefetch(bp->status_blk);
1533 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1534 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1535 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1536
1537 /* Return here if interrupt is disabled. */
1538 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1539 return IRQ_HANDLED;
1540
1541 netif_rx_schedule(dev);
1542
1543 return IRQ_HANDLED;
1544 }
1545
1546 static irqreturn_t
1547 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1548 {
1549 struct net_device *dev = dev_instance;
1550 struct bnx2 *bp = dev->priv;
1551
1552 /* When using INTx, it is possible for the interrupt to arrive
1553 * at the CPU before the status block posted prior to the
1554 * interrupt. Reading a register will flush the status block.
1555 * When using MSI, the MSI message will always complete after
1556 * the status block write.
1557 */
1558 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
1559 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1560 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1561 return IRQ_NONE;
1562
1563 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1564 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1565 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1566
1567 /* Return here if interrupt is shared and is disabled. */
1568 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1569 return IRQ_HANDLED;
1570
1571 netif_rx_schedule(dev);
1572
1573 return IRQ_HANDLED;
1574 }
1575
1576 static int
1577 bnx2_poll(struct net_device *dev, int *budget)
1578 {
1579 struct bnx2 *bp = dev->priv;
1580 int rx_done = 1;
1581
1582 bp->last_status_idx = bp->status_blk->status_idx;
1583
1584 rmb();
1585 if ((bp->status_blk->status_attn_bits &
1586 STATUS_ATTN_BITS_LINK_STATE) !=
1587 (bp->status_blk->status_attn_bits_ack &
1588 STATUS_ATTN_BITS_LINK_STATE)) {
1589
1590 spin_lock(&bp->phy_lock);
1591 bnx2_phy_int(bp);
1592 spin_unlock(&bp->phy_lock);
1593 }
1594
1595 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) {
1596 bnx2_tx_int(bp);
1597 }
1598
1599 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
1600 int orig_budget = *budget;
1601 int work_done;
1602
1603 if (orig_budget > dev->quota)
1604 orig_budget = dev->quota;
1605
1606 work_done = bnx2_rx_int(bp, orig_budget);
1607 *budget -= work_done;
1608 dev->quota -= work_done;
1609
1610 if (work_done >= orig_budget) {
1611 rx_done = 0;
1612 }
1613 }
1614
1615 if (rx_done) {
1616 netif_rx_complete(dev);
1617 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1618 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1619 bp->last_status_idx);
1620 return 0;
1621 }
1622
1623 return 1;
1624 }
1625
1626 /* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1627 * from set_multicast.
1628 */
1629 static void
1630 bnx2_set_rx_mode(struct net_device *dev)
1631 {
1632 struct bnx2 *bp = dev->priv;
1633 u32 rx_mode, sort_mode;
1634 int i;
1635
1636 spin_lock_bh(&bp->phy_lock);
1637
1638 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1639 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1640 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1641 #ifdef BCM_VLAN
1642 if (!bp->vlgrp) {
1643 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1644 }
1645 #else
1646 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1647 #endif
1648 if (dev->flags & IFF_PROMISC) {
1649 /* Promiscuous mode. */
1650 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1651 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1652 }
1653 else if (dev->flags & IFF_ALLMULTI) {
1654 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1655 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1656 0xffffffff);
1657 }
1658 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1659 }
1660 else {
1661 /* Accept one or more multicast(s). */
1662 struct dev_mc_list *mclist;
1663 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1664 u32 regidx;
1665 u32 bit;
1666 u32 crc;
1667
1668 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1669
1670 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1671 i++, mclist = mclist->next) {
1672
1673 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1674 bit = crc & 0xff;
1675 regidx = (bit & 0xe0) >> 5;
1676 bit &= 0x1f;
1677 mc_filter[regidx] |= (1 << bit);
1678 }
1679
1680 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1681 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1682 mc_filter[i]);
1683 }
1684
1685 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1686 }
1687
1688 if (rx_mode != bp->rx_mode) {
1689 bp->rx_mode = rx_mode;
1690 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1691 }
1692
1693 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1694 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1695 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1696
1697 spin_unlock_bh(&bp->phy_lock);
1698 }
1699
1700 static void
1701 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1702 u32 rv2p_proc)
1703 {
1704 int i;
1705 u32 val;
1706
1707
1708 for (i = 0; i < rv2p_code_len; i += 8) {
1709 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1710 rv2p_code++;
1711 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1712 rv2p_code++;
1713
1714 if (rv2p_proc == RV2P_PROC1) {
1715 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1716 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1717 }
1718 else {
1719 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1720 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1721 }
1722 }
1723
1724 /* Reset the processor, un-stall is done later. */
1725 if (rv2p_proc == RV2P_PROC1) {
1726 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1727 }
1728 else {
1729 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1730 }
1731 }
1732
1733 static void
1734 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1735 {
1736 u32 offset;
1737 u32 val;
1738
1739 /* Halt the CPU. */
1740 val = REG_RD_IND(bp, cpu_reg->mode);
1741 val |= cpu_reg->mode_value_halt;
1742 REG_WR_IND(bp, cpu_reg->mode, val);
1743 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1744
1745 /* Load the Text area. */
1746 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1747 if (fw->text) {
1748 int j;
1749
1750 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1751 REG_WR_IND(bp, offset, fw->text[j]);
1752 }
1753 }
1754
1755 /* Load the Data area. */
1756 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1757 if (fw->data) {
1758 int j;
1759
1760 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1761 REG_WR_IND(bp, offset, fw->data[j]);
1762 }
1763 }
1764
1765 /* Load the SBSS area. */
1766 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1767 if (fw->sbss) {
1768 int j;
1769
1770 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1771 REG_WR_IND(bp, offset, fw->sbss[j]);
1772 }
1773 }
1774
1775 /* Load the BSS area. */
1776 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1777 if (fw->bss) {
1778 int j;
1779
1780 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1781 REG_WR_IND(bp, offset, fw->bss[j]);
1782 }
1783 }
1784
1785 /* Load the Read-Only area. */
1786 offset = cpu_reg->spad_base +
1787 (fw->rodata_addr - cpu_reg->mips_view_base);
1788 if (fw->rodata) {
1789 int j;
1790
1791 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1792 REG_WR_IND(bp, offset, fw->rodata[j]);
1793 }
1794 }
1795
1796 /* Clear the pre-fetch instruction. */
1797 REG_WR_IND(bp, cpu_reg->inst, 0);
1798 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1799
1800 /* Start the CPU. */
1801 val = REG_RD_IND(bp, cpu_reg->mode);
1802 val &= ~cpu_reg->mode_value_halt;
1803 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1804 REG_WR_IND(bp, cpu_reg->mode, val);
1805 }
1806
1807 static void
1808 bnx2_init_cpus(struct bnx2 *bp)
1809 {
1810 struct cpu_reg cpu_reg;
1811 struct fw_info fw;
1812
1813 /* Initialize the RV2P processor. */
1814 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1815 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1816
1817 /* Initialize the RX Processor. */
1818 cpu_reg.mode = BNX2_RXP_CPU_MODE;
1819 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1820 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1821 cpu_reg.state = BNX2_RXP_CPU_STATE;
1822 cpu_reg.state_value_clear = 0xffffff;
1823 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1824 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1825 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1826 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1827 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1828 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1829 cpu_reg.mips_view_base = 0x8000000;
1830
1831 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1832 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1833 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1834 fw.start_addr = bnx2_RXP_b06FwStartAddr;
1835
1836 fw.text_addr = bnx2_RXP_b06FwTextAddr;
1837 fw.text_len = bnx2_RXP_b06FwTextLen;
1838 fw.text_index = 0;
1839 fw.text = bnx2_RXP_b06FwText;
1840
1841 fw.data_addr = bnx2_RXP_b06FwDataAddr;
1842 fw.data_len = bnx2_RXP_b06FwDataLen;
1843 fw.data_index = 0;
1844 fw.data = bnx2_RXP_b06FwData;
1845
1846 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1847 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1848 fw.sbss_index = 0;
1849 fw.sbss = bnx2_RXP_b06FwSbss;
1850
1851 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1852 fw.bss_len = bnx2_RXP_b06FwBssLen;
1853 fw.bss_index = 0;
1854 fw.bss = bnx2_RXP_b06FwBss;
1855
1856 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
1857 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
1858 fw.rodata_index = 0;
1859 fw.rodata = bnx2_RXP_b06FwRodata;
1860
1861 load_cpu_fw(bp, &cpu_reg, &fw);
1862
1863 /* Initialize the TX Processor. */
1864 cpu_reg.mode = BNX2_TXP_CPU_MODE;
1865 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
1866 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
1867 cpu_reg.state = BNX2_TXP_CPU_STATE;
1868 cpu_reg.state_value_clear = 0xffffff;
1869 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
1870 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
1871 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
1872 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
1873 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1874 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
1875 cpu_reg.mips_view_base = 0x8000000;
1876
1877 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
1878 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
1879 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
1880 fw.start_addr = bnx2_TXP_b06FwStartAddr;
1881
1882 fw.text_addr = bnx2_TXP_b06FwTextAddr;
1883 fw.text_len = bnx2_TXP_b06FwTextLen;
1884 fw.text_index = 0;
1885 fw.text = bnx2_TXP_b06FwText;
1886
1887 fw.data_addr = bnx2_TXP_b06FwDataAddr;
1888 fw.data_len = bnx2_TXP_b06FwDataLen;
1889 fw.data_index = 0;
1890 fw.data = bnx2_TXP_b06FwData;
1891
1892 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
1893 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
1894 fw.sbss_index = 0;
1895 fw.sbss = bnx2_TXP_b06FwSbss;
1896
1897 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
1898 fw.bss_len = bnx2_TXP_b06FwBssLen;
1899 fw.bss_index = 0;
1900 fw.bss = bnx2_TXP_b06FwBss;
1901
1902 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
1903 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
1904 fw.rodata_index = 0;
1905 fw.rodata = bnx2_TXP_b06FwRodata;
1906
1907 load_cpu_fw(bp, &cpu_reg, &fw);
1908
1909 /* Initialize the TX Patch-up Processor. */
1910 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
1911 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
1912 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
1913 cpu_reg.state = BNX2_TPAT_CPU_STATE;
1914 cpu_reg.state_value_clear = 0xffffff;
1915 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
1916 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
1917 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
1918 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
1919 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1920 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
1921 cpu_reg.mips_view_base = 0x8000000;
1922
1923 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
1924 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
1925 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
1926 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
1927
1928 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
1929 fw.text_len = bnx2_TPAT_b06FwTextLen;
1930 fw.text_index = 0;
1931 fw.text = bnx2_TPAT_b06FwText;
1932
1933 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
1934 fw.data_len = bnx2_TPAT_b06FwDataLen;
1935 fw.data_index = 0;
1936 fw.data = bnx2_TPAT_b06FwData;
1937
1938 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
1939 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
1940 fw.sbss_index = 0;
1941 fw.sbss = bnx2_TPAT_b06FwSbss;
1942
1943 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
1944 fw.bss_len = bnx2_TPAT_b06FwBssLen;
1945 fw.bss_index = 0;
1946 fw.bss = bnx2_TPAT_b06FwBss;
1947
1948 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
1949 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
1950 fw.rodata_index = 0;
1951 fw.rodata = bnx2_TPAT_b06FwRodata;
1952
1953 load_cpu_fw(bp, &cpu_reg, &fw);
1954
1955 /* Initialize the Completion Processor. */
1956 cpu_reg.mode = BNX2_COM_CPU_MODE;
1957 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
1958 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
1959 cpu_reg.state = BNX2_COM_CPU_STATE;
1960 cpu_reg.state_value_clear = 0xffffff;
1961 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
1962 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
1963 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
1964 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
1965 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1966 cpu_reg.spad_base = BNX2_COM_SCRATCH;
1967 cpu_reg.mips_view_base = 0x8000000;
1968
1969 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
1970 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
1971 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
1972 fw.start_addr = bnx2_COM_b06FwStartAddr;
1973
1974 fw.text_addr = bnx2_COM_b06FwTextAddr;
1975 fw.text_len = bnx2_COM_b06FwTextLen;
1976 fw.text_index = 0;
1977 fw.text = bnx2_COM_b06FwText;
1978
1979 fw.data_addr = bnx2_COM_b06FwDataAddr;
1980 fw.data_len = bnx2_COM_b06FwDataLen;
1981 fw.data_index = 0;
1982 fw.data = bnx2_COM_b06FwData;
1983
1984 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
1985 fw.sbss_len = bnx2_COM_b06FwSbssLen;
1986 fw.sbss_index = 0;
1987 fw.sbss = bnx2_COM_b06FwSbss;
1988
1989 fw.bss_addr = bnx2_COM_b06FwBssAddr;
1990 fw.bss_len = bnx2_COM_b06FwBssLen;
1991 fw.bss_index = 0;
1992 fw.bss = bnx2_COM_b06FwBss;
1993
1994 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
1995 fw.rodata_len = bnx2_COM_b06FwRodataLen;
1996 fw.rodata_index = 0;
1997 fw.rodata = bnx2_COM_b06FwRodata;
1998
1999 load_cpu_fw(bp, &cpu_reg, &fw);
2000
2001 }
2002
2003 static int
2004 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2005 {
2006 u16 pmcsr;
2007
2008 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2009
2010 switch (state) {
2011 case PCI_D0: {
2012 u32 val;
2013
2014 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2015 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2016 PCI_PM_CTRL_PME_STATUS);
2017
2018 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2019 /* delay required during transition out of D3hot */
2020 msleep(20);
2021
2022 val = REG_RD(bp, BNX2_EMAC_MODE);
2023 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2024 val &= ~BNX2_EMAC_MODE_MPKT;
2025 REG_WR(bp, BNX2_EMAC_MODE, val);
2026
2027 val = REG_RD(bp, BNX2_RPM_CONFIG);
2028 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2029 REG_WR(bp, BNX2_RPM_CONFIG, val);
2030 break;
2031 }
2032 case PCI_D3hot: {
2033 int i;
2034 u32 val, wol_msg;
2035
2036 if (bp->wol) {
2037 u32 advertising;
2038 u8 autoneg;
2039
2040 autoneg = bp->autoneg;
2041 advertising = bp->advertising;
2042
2043 bp->autoneg = AUTONEG_SPEED;
2044 bp->advertising = ADVERTISED_10baseT_Half |
2045 ADVERTISED_10baseT_Full |
2046 ADVERTISED_100baseT_Half |
2047 ADVERTISED_100baseT_Full |
2048 ADVERTISED_Autoneg;
2049
2050 bnx2_setup_copper_phy(bp);
2051
2052 bp->autoneg = autoneg;
2053 bp->advertising = advertising;
2054
2055 bnx2_set_mac_addr(bp);
2056
2057 val = REG_RD(bp, BNX2_EMAC_MODE);
2058
2059 /* Enable port mode. */
2060 val &= ~BNX2_EMAC_MODE_PORT;
2061 val |= BNX2_EMAC_MODE_PORT_MII |
2062 BNX2_EMAC_MODE_MPKT_RCVD |
2063 BNX2_EMAC_MODE_ACPI_RCVD |
2064 BNX2_EMAC_MODE_FORCE_LINK |
2065 BNX2_EMAC_MODE_MPKT;
2066
2067 REG_WR(bp, BNX2_EMAC_MODE, val);
2068
2069 /* receive all multicast */
2070 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2071 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2072 0xffffffff);
2073 }
2074 REG_WR(bp, BNX2_EMAC_RX_MODE,
2075 BNX2_EMAC_RX_MODE_SORT_MODE);
2076
2077 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2078 BNX2_RPM_SORT_USER0_MC_EN;
2079 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2080 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2081 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2082 BNX2_RPM_SORT_USER0_ENA);
2083
2084 /* Need to enable EMAC and RPM for WOL. */
2085 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2086 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2087 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2088 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2089
2090 val = REG_RD(bp, BNX2_RPM_CONFIG);
2091 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2092 REG_WR(bp, BNX2_RPM_CONFIG, val);
2093
2094 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2095 }
2096 else {
2097 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2098 }
2099
2100 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
2101
2102 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2103 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2104 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2105
2106 if (bp->wol)
2107 pmcsr |= 3;
2108 }
2109 else {
2110 pmcsr |= 3;
2111 }
2112 if (bp->wol) {
2113 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2114 }
2115 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2116 pmcsr);
2117
2118 /* No more memory access after this point until
2119 * device is brought back to D0.
2120 */
2121 udelay(50);
2122 break;
2123 }
2124 default:
2125 return -EINVAL;
2126 }
2127 return 0;
2128 }
2129
2130 static int
2131 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2132 {
2133 u32 val;
2134 int j;
2135
2136 /* Request access to the flash interface. */
2137 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2138 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2139 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2140 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2141 break;
2142
2143 udelay(5);
2144 }
2145
2146 if (j >= NVRAM_TIMEOUT_COUNT)
2147 return -EBUSY;
2148
2149 return 0;
2150 }
2151
2152 static int
2153 bnx2_release_nvram_lock(struct bnx2 *bp)
2154 {
2155 int j;
2156 u32 val;
2157
2158 /* Relinquish nvram interface. */
2159 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2160
2161 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2162 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2163 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2164 break;
2165
2166 udelay(5);
2167 }
2168
2169 if (j >= NVRAM_TIMEOUT_COUNT)
2170 return -EBUSY;
2171
2172 return 0;
2173 }
2174
2175
2176 static int
2177 bnx2_enable_nvram_write(struct bnx2 *bp)
2178 {
2179 u32 val;
2180
2181 val = REG_RD(bp, BNX2_MISC_CFG);
2182 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2183
2184 if (!bp->flash_info->buffered) {
2185 int j;
2186
2187 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2188 REG_WR(bp, BNX2_NVM_COMMAND,
2189 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2190
2191 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2192 udelay(5);
2193
2194 val = REG_RD(bp, BNX2_NVM_COMMAND);
2195 if (val & BNX2_NVM_COMMAND_DONE)
2196 break;
2197 }
2198
2199 if (j >= NVRAM_TIMEOUT_COUNT)
2200 return -EBUSY;
2201 }
2202 return 0;
2203 }
2204
2205 static void
2206 bnx2_disable_nvram_write(struct bnx2 *bp)
2207 {
2208 u32 val;
2209
2210 val = REG_RD(bp, BNX2_MISC_CFG);
2211 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2212 }
2213
2214
2215 static void
2216 bnx2_enable_nvram_access(struct bnx2 *bp)
2217 {
2218 u32 val;
2219
2220 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2221 /* Enable both bits, even on read. */
2222 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2223 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2224 }
2225
2226 static void
2227 bnx2_disable_nvram_access(struct bnx2 *bp)
2228 {
2229 u32 val;
2230
2231 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2232 /* Disable both bits, even after read. */
2233 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2234 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2235 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2236 }
2237
2238 static int
2239 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2240 {
2241 u32 cmd;
2242 int j;
2243
2244 if (bp->flash_info->buffered)
2245 /* Buffered flash, no erase needed */
2246 return 0;
2247
2248 /* Build an erase command */
2249 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2250 BNX2_NVM_COMMAND_DOIT;
2251
2252 /* Need to clear DONE bit separately. */
2253 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2254
2255 /* Address of the NVRAM to read from. */
2256 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2257
2258 /* Issue an erase command. */
2259 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2260
2261 /* Wait for completion. */
2262 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2263 u32 val;
2264
2265 udelay(5);
2266
2267 val = REG_RD(bp, BNX2_NVM_COMMAND);
2268 if (val & BNX2_NVM_COMMAND_DONE)
2269 break;
2270 }
2271
2272 if (j >= NVRAM_TIMEOUT_COUNT)
2273 return -EBUSY;
2274
2275 return 0;
2276 }
2277
2278 static int
2279 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2280 {
2281 u32 cmd;
2282 int j;
2283
2284 /* Build the command word. */
2285 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2286
2287 /* Calculate an offset of a buffered flash. */
2288 if (bp->flash_info->buffered) {
2289 offset = ((offset / bp->flash_info->page_size) <<
2290 bp->flash_info->page_bits) +
2291 (offset % bp->flash_info->page_size);
2292 }
2293
2294 /* Need to clear DONE bit separately. */
2295 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2296
2297 /* Address of the NVRAM to read from. */
2298 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2299
2300 /* Issue a read command. */
2301 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2302
2303 /* Wait for completion. */
2304 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2305 u32 val;
2306
2307 udelay(5);
2308
2309 val = REG_RD(bp, BNX2_NVM_COMMAND);
2310 if (val & BNX2_NVM_COMMAND_DONE) {
2311 val = REG_RD(bp, BNX2_NVM_READ);
2312
2313 val = be32_to_cpu(val);
2314 memcpy(ret_val, &val, 4);
2315 break;
2316 }
2317 }
2318 if (j >= NVRAM_TIMEOUT_COUNT)
2319 return -EBUSY;
2320
2321 return 0;
2322 }
2323
2324
2325 static int
2326 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2327 {
2328 u32 cmd, val32;
2329 int j;
2330
2331 /* Build the command word. */
2332 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2333
2334 /* Calculate an offset of a buffered flash. */
2335 if (bp->flash_info->buffered) {
2336 offset = ((offset / bp->flash_info->page_size) <<
2337 bp->flash_info->page_bits) +
2338 (offset % bp->flash_info->page_size);
2339 }
2340
2341 /* Need to clear DONE bit separately. */
2342 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2343
2344 memcpy(&val32, val, 4);
2345 val32 = cpu_to_be32(val32);
2346
2347 /* Write the data. */
2348 REG_WR(bp, BNX2_NVM_WRITE, val32);
2349
2350 /* Address of the NVRAM to write to. */
2351 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2352
2353 /* Issue the write command. */
2354 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2355
2356 /* Wait for completion. */
2357 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2358 udelay(5);
2359
2360 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2361 break;
2362 }
2363 if (j >= NVRAM_TIMEOUT_COUNT)
2364 return -EBUSY;
2365
2366 return 0;
2367 }
2368
2369 static int
2370 bnx2_init_nvram(struct bnx2 *bp)
2371 {
2372 u32 val;
2373 int j, entry_count, rc;
2374 struct flash_spec *flash;
2375
2376 /* Determine the selected interface. */
2377 val = REG_RD(bp, BNX2_NVM_CFG1);
2378
2379 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2380
2381 rc = 0;
2382 if (val & 0x40000000) {
2383
2384 /* Flash interface has been reconfigured */
2385 for (j = 0, flash = &flash_table[0]; j < entry_count;
2386 j++, flash++) {
2387
2388 if (val == flash->config1) {
2389 bp->flash_info = flash;
2390 break;
2391 }
2392 }
2393 }
2394 else {
2395 /* Not yet been reconfigured */
2396
2397 for (j = 0, flash = &flash_table[0]; j < entry_count;
2398 j++, flash++) {
2399
2400 if ((val & FLASH_STRAP_MASK) == flash->strapping) {
2401 bp->flash_info = flash;
2402
2403 /* Request access to the flash interface. */
2404 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2405 return rc;
2406
2407 /* Enable access to flash interface */
2408 bnx2_enable_nvram_access(bp);
2409
2410 /* Reconfigure the flash interface */
2411 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2412 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2413 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2414 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2415
2416 /* Disable access to flash interface */
2417 bnx2_disable_nvram_access(bp);
2418 bnx2_release_nvram_lock(bp);
2419
2420 break;
2421 }
2422 }
2423 } /* if (val & 0x40000000) */
2424
2425 if (j == entry_count) {
2426 bp->flash_info = NULL;
2427 printk(KERN_ALERT "Unknown flash/EEPROM type.\n");
2428 rc = -ENODEV;
2429 }
2430
2431 return rc;
2432 }
2433
2434 static int
2435 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2436 int buf_size)
2437 {
2438 int rc = 0;
2439 u32 cmd_flags, offset32, len32, extra;
2440
2441 if (buf_size == 0)
2442 return 0;
2443
2444 /* Request access to the flash interface. */
2445 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2446 return rc;
2447
2448 /* Enable access to flash interface */
2449 bnx2_enable_nvram_access(bp);
2450
2451 len32 = buf_size;
2452 offset32 = offset;
2453 extra = 0;
2454
2455 cmd_flags = 0;
2456
2457 if (offset32 & 3) {
2458 u8 buf[4];
2459 u32 pre_len;
2460
2461 offset32 &= ~3;
2462 pre_len = 4 - (offset & 3);
2463
2464 if (pre_len >= len32) {
2465 pre_len = len32;
2466 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2467 BNX2_NVM_COMMAND_LAST;
2468 }
2469 else {
2470 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2471 }
2472
2473 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2474
2475 if (rc)
2476 return rc;
2477
2478 memcpy(ret_buf, buf + (offset & 3), pre_len);
2479
2480 offset32 += 4;
2481 ret_buf += pre_len;
2482 len32 -= pre_len;
2483 }
2484 if (len32 & 3) {
2485 extra = 4 - (len32 & 3);
2486 len32 = (len32 + 4) & ~3;
2487 }
2488
2489 if (len32 == 4) {
2490 u8 buf[4];
2491
2492 if (cmd_flags)
2493 cmd_flags = BNX2_NVM_COMMAND_LAST;
2494 else
2495 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2496 BNX2_NVM_COMMAND_LAST;
2497
2498 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2499
2500 memcpy(ret_buf, buf, 4 - extra);
2501 }
2502 else if (len32 > 0) {
2503 u8 buf[4];
2504
2505 /* Read the first word. */
2506 if (cmd_flags)
2507 cmd_flags = 0;
2508 else
2509 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2510
2511 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2512
2513 /* Advance to the next dword. */
2514 offset32 += 4;
2515 ret_buf += 4;
2516 len32 -= 4;
2517
2518 while (len32 > 4 && rc == 0) {
2519 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2520
2521 /* Advance to the next dword. */
2522 offset32 += 4;
2523 ret_buf += 4;
2524 len32 -= 4;
2525 }
2526
2527 if (rc)
2528 return rc;
2529
2530 cmd_flags = BNX2_NVM_COMMAND_LAST;
2531 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2532
2533 memcpy(ret_buf, buf, 4 - extra);
2534 }
2535
2536 /* Disable access to flash interface */
2537 bnx2_disable_nvram_access(bp);
2538
2539 bnx2_release_nvram_lock(bp);
2540
2541 return rc;
2542 }
2543
2544 static int
2545 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2546 int buf_size)
2547 {
2548 u32 written, offset32, len32;
2549 u8 *buf, start[4], end[4];
2550 int rc = 0;
2551 int align_start, align_end;
2552
2553 buf = data_buf;
2554 offset32 = offset;
2555 len32 = buf_size;
2556 align_start = align_end = 0;
2557
2558 if ((align_start = (offset32 & 3))) {
2559 offset32 &= ~3;
2560 len32 += align_start;
2561 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2562 return rc;
2563 }
2564
2565 if (len32 & 3) {
2566 if ((len32 > 4) || !align_start) {
2567 align_end = 4 - (len32 & 3);
2568 len32 += align_end;
2569 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2570 end, 4))) {
2571 return rc;
2572 }
2573 }
2574 }
2575
2576 if (align_start || align_end) {
2577 buf = kmalloc(len32, GFP_KERNEL);
2578 if (buf == 0)
2579 return -ENOMEM;
2580 if (align_start) {
2581 memcpy(buf, start, 4);
2582 }
2583 if (align_end) {
2584 memcpy(buf + len32 - 4, end, 4);
2585 }
2586 memcpy(buf + align_start, data_buf, buf_size);
2587 }
2588
2589 written = 0;
2590 while ((written < len32) && (rc == 0)) {
2591 u32 page_start, page_end, data_start, data_end;
2592 u32 addr, cmd_flags;
2593 int i;
2594 u8 flash_buffer[264];
2595
2596 /* Find the page_start addr */
2597 page_start = offset32 + written;
2598 page_start -= (page_start % bp->flash_info->page_size);
2599 /* Find the page_end addr */
2600 page_end = page_start + bp->flash_info->page_size;
2601 /* Find the data_start addr */
2602 data_start = (written == 0) ? offset32 : page_start;
2603 /* Find the data_end addr */
2604 data_end = (page_end > offset32 + len32) ?
2605 (offset32 + len32) : page_end;
2606
2607 /* Request access to the flash interface. */
2608 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2609 goto nvram_write_end;
2610
2611 /* Enable access to flash interface */
2612 bnx2_enable_nvram_access(bp);
2613
2614 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2615 if (bp->flash_info->buffered == 0) {
2616 int j;
2617
2618 /* Read the whole page into the buffer
2619 * (non-buffer flash only) */
2620 for (j = 0; j < bp->flash_info->page_size; j += 4) {
2621 if (j == (bp->flash_info->page_size - 4)) {
2622 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2623 }
2624 rc = bnx2_nvram_read_dword(bp,
2625 page_start + j,
2626 &flash_buffer[j],
2627 cmd_flags);
2628
2629 if (rc)
2630 goto nvram_write_end;
2631
2632 cmd_flags = 0;
2633 }
2634 }
2635
2636 /* Enable writes to flash interface (unlock write-protect) */
2637 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2638 goto nvram_write_end;
2639
2640 /* Erase the page */
2641 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2642 goto nvram_write_end;
2643
2644 /* Re-enable the write again for the actual write */
2645 bnx2_enable_nvram_write(bp);
2646
2647 /* Loop to write back the buffer data from page_start to
2648 * data_start */
2649 i = 0;
2650 if (bp->flash_info->buffered == 0) {
2651 for (addr = page_start; addr < data_start;
2652 addr += 4, i += 4) {
2653
2654 rc = bnx2_nvram_write_dword(bp, addr,
2655 &flash_buffer[i], cmd_flags);
2656
2657 if (rc != 0)
2658 goto nvram_write_end;
2659
2660 cmd_flags = 0;
2661 }
2662 }
2663
2664 /* Loop to write the new data from data_start to data_end */
2665 for (addr = data_start; addr < data_end; addr += 4, i++) {
2666 if ((addr == page_end - 4) ||
2667 ((bp->flash_info->buffered) &&
2668 (addr == data_end - 4))) {
2669
2670 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2671 }
2672 rc = bnx2_nvram_write_dword(bp, addr, buf,
2673 cmd_flags);
2674
2675 if (rc != 0)
2676 goto nvram_write_end;
2677
2678 cmd_flags = 0;
2679 buf += 4;
2680 }
2681
2682 /* Loop to write back the buffer data from data_end
2683 * to page_end */
2684 if (bp->flash_info->buffered == 0) {
2685 for (addr = data_end; addr < page_end;
2686 addr += 4, i += 4) {
2687
2688 if (addr == page_end-4) {
2689 cmd_flags = BNX2_NVM_COMMAND_LAST;
2690 }
2691 rc = bnx2_nvram_write_dword(bp, addr,
2692 &flash_buffer[i], cmd_flags);
2693
2694 if (rc != 0)
2695 goto nvram_write_end;
2696
2697 cmd_flags = 0;
2698 }
2699 }
2700
2701 /* Disable writes to flash interface (lock write-protect) */
2702 bnx2_disable_nvram_write(bp);
2703
2704 /* Disable access to flash interface */
2705 bnx2_disable_nvram_access(bp);
2706 bnx2_release_nvram_lock(bp);
2707
2708 /* Increment written */
2709 written += data_end - data_start;
2710 }
2711
2712 nvram_write_end:
2713 if (align_start || align_end)
2714 kfree(buf);
2715 return rc;
2716 }
2717
2718 static int
2719 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
2720 {
2721 u32 val;
2722 int i, rc = 0;
2723
2724 /* Wait for the current PCI transaction to complete before
2725 * issuing a reset. */
2726 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
2727 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2728 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2729 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2730 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2731 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
2732 udelay(5);
2733
2734 /* Deposit a driver reset signature so the firmware knows that
2735 * this is a soft reset. */
2736 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
2737 BNX2_DRV_RESET_SIGNATURE_MAGIC);
2738
2739 bp->fw_timed_out = 0;
2740
2741 /* Wait for the firmware to tell us it is ok to issue a reset. */
2742 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
2743
2744 /* Do a dummy read to force the chip to complete all current transaction
2745 * before we issue a reset. */
2746 val = REG_RD(bp, BNX2_MISC_ID);
2747
2748 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2749 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2750 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2751
2752 /* Chip reset. */
2753 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
2754
2755 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2756 (CHIP_ID(bp) == CHIP_ID_5706_A1))
2757 msleep(15);
2758
2759 /* Reset takes approximate 30 usec */
2760 for (i = 0; i < 10; i++) {
2761 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
2762 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2763 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2764 break;
2765 }
2766 udelay(10);
2767 }
2768
2769 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2770 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2771 printk(KERN_ERR PFX "Chip reset did not complete\n");
2772 return -EBUSY;
2773 }
2774
2775 /* Make sure byte swapping is properly configured. */
2776 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
2777 if (val != 0x01020304) {
2778 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
2779 return -ENODEV;
2780 }
2781
2782 bp->fw_timed_out = 0;
2783
2784 /* Wait for the firmware to finish its initialization. */
2785 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
2786
2787 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2788 /* Adjust the voltage regular to two steps lower. The default
2789 * of this register is 0x0000000e. */
2790 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
2791
2792 /* Remove bad rbuf memory from the free pool. */
2793 rc = bnx2_alloc_bad_rbuf(bp);
2794 }
2795
2796 return rc;
2797 }
2798
2799 static int
2800 bnx2_init_chip(struct bnx2 *bp)
2801 {
2802 u32 val;
2803
2804 /* Make sure the interrupt is not active. */
2805 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2806
2807 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
2808 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
2809 #ifdef __BIG_ENDIAN
2810 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
2811 #endif
2812 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
2813 DMA_READ_CHANS << 12 |
2814 DMA_WRITE_CHANS << 16;
2815
2816 val |= (0x2 << 20) | (1 << 11);
2817
2818 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
2819 val |= (1 << 23);
2820
2821 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
2822 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
2823 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
2824
2825 REG_WR(bp, BNX2_DMA_CONFIG, val);
2826
2827 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2828 val = REG_RD(bp, BNX2_TDMA_CONFIG);
2829 val |= BNX2_TDMA_CONFIG_ONE_DMA;
2830 REG_WR(bp, BNX2_TDMA_CONFIG, val);
2831 }
2832
2833 if (bp->flags & PCIX_FLAG) {
2834 u16 val16;
2835
2836 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2837 &val16);
2838 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2839 val16 & ~PCI_X_CMD_ERO);
2840 }
2841
2842 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2843 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
2844 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
2845 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
2846
2847 /* Initialize context mapping and zero out the quick contexts. The
2848 * context block must have already been enabled. */
2849 bnx2_init_context(bp);
2850
2851 bnx2_init_cpus(bp);
2852 bnx2_init_nvram(bp);
2853
2854 bnx2_set_mac_addr(bp);
2855
2856 val = REG_RD(bp, BNX2_MQ_CONFIG);
2857 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
2858 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
2859 REG_WR(bp, BNX2_MQ_CONFIG, val);
2860
2861 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
2862 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
2863 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
2864
2865 val = (BCM_PAGE_BITS - 8) << 24;
2866 REG_WR(bp, BNX2_RV2P_CONFIG, val);
2867
2868 /* Configure page size. */
2869 val = REG_RD(bp, BNX2_TBDR_CONFIG);
2870 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
2871 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
2872 REG_WR(bp, BNX2_TBDR_CONFIG, val);
2873
2874 val = bp->mac_addr[0] +
2875 (bp->mac_addr[1] << 8) +
2876 (bp->mac_addr[2] << 16) +
2877 bp->mac_addr[3] +
2878 (bp->mac_addr[4] << 8) +
2879 (bp->mac_addr[5] << 16);
2880 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
2881
2882 /* Program the MTU. Also include 4 bytes for CRC32. */
2883 val = bp->dev->mtu + ETH_HLEN + 4;
2884 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
2885 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
2886 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
2887
2888 bp->last_status_idx = 0;
2889 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
2890
2891 /* Set up how to generate a link change interrupt. */
2892 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2893
2894 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
2895 (u64) bp->status_blk_mapping & 0xffffffff);
2896 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
2897
2898 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
2899 (u64) bp->stats_blk_mapping & 0xffffffff);
2900 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
2901 (u64) bp->stats_blk_mapping >> 32);
2902
2903 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
2904 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
2905
2906 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
2907 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
2908
2909 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
2910 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
2911
2912 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
2913
2914 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
2915
2916 REG_WR(bp, BNX2_HC_COM_TICKS,
2917 (bp->com_ticks_int << 16) | bp->com_ticks);
2918
2919 REG_WR(bp, BNX2_HC_CMD_TICKS,
2920 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
2921
2922 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
2923 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
2924
2925 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
2926 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
2927 else {
2928 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
2929 BNX2_HC_CONFIG_TX_TMR_MODE |
2930 BNX2_HC_CONFIG_COLLECT_STATS);
2931 }
2932
2933 /* Clear internal stats counters. */
2934 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
2935
2936 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
2937
2938 /* Initialize the receive filter. */
2939 bnx2_set_rx_mode(bp->dev);
2940
2941 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
2942
2943 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
2944 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
2945
2946 udelay(20);
2947
2948 return 0;
2949 }
2950
2951
2952 static void
2953 bnx2_init_tx_ring(struct bnx2 *bp)
2954 {
2955 struct tx_bd *txbd;
2956 u32 val;
2957
2958 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2959
2960 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
2961 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
2962
2963 bp->tx_prod = 0;
2964 bp->tx_cons = 0;
2965 bp->tx_prod_bseq = 0;
2966
2967 val = BNX2_L2CTX_TYPE_TYPE_L2;
2968 val |= BNX2_L2CTX_TYPE_SIZE_L2;
2969 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2970
2971 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
2972 val |= 8 << 16;
2973 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2974
2975 val = (u64) bp->tx_desc_mapping >> 32;
2976 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
2977
2978 val = (u64) bp->tx_desc_mapping & 0xffffffff;
2979 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2980 }
2981
2982 static void
2983 bnx2_init_rx_ring(struct bnx2 *bp)
2984 {
2985 struct rx_bd *rxbd;
2986 int i;
2987 u16 prod, ring_prod;
2988 u32 val;
2989
2990 /* 8 for CRC and VLAN */
2991 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
2992 /* 8 for alignment */
2993 bp->rx_buf_size = bp->rx_buf_use_size + 8;
2994
2995 ring_prod = prod = bp->rx_prod = 0;
2996 bp->rx_cons = 0;
2997 bp->rx_prod_bseq = 0;
2998
2999 rxbd = &bp->rx_desc_ring[0];
3000 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3001 rxbd->rx_bd_len = bp->rx_buf_use_size;
3002 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3003 }
3004
3005 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3006 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3007
3008 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3009 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3010 val |= 0x02 << 8;
3011 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3012
3013 val = (u64) bp->rx_desc_mapping >> 32;
3014 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3015
3016 val = (u64) bp->rx_desc_mapping & 0xffffffff;
3017 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3018
3019 for ( ;ring_prod < bp->rx_ring_size; ) {
3020 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3021 break;
3022 }
3023 prod = NEXT_RX_BD(prod);
3024 ring_prod = RX_RING_IDX(prod);
3025 }
3026 bp->rx_prod = prod;
3027
3028 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3029
3030 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3031 }
3032
3033 static void
3034 bnx2_free_tx_skbs(struct bnx2 *bp)
3035 {
3036 int i;
3037
3038 if (bp->tx_buf_ring == NULL)
3039 return;
3040
3041 for (i = 0; i < TX_DESC_CNT; ) {
3042 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3043 struct sk_buff *skb = tx_buf->skb;
3044 int j, last;
3045
3046 if (skb == NULL) {
3047 i++;
3048 continue;
3049 }
3050
3051 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3052 skb_headlen(skb), PCI_DMA_TODEVICE);
3053
3054 tx_buf->skb = NULL;
3055
3056 last = skb_shinfo(skb)->nr_frags;
3057 for (j = 0; j < last; j++) {
3058 tx_buf = &bp->tx_buf_ring[i + j + 1];
3059 pci_unmap_page(bp->pdev,
3060 pci_unmap_addr(tx_buf, mapping),
3061 skb_shinfo(skb)->frags[j].size,
3062 PCI_DMA_TODEVICE);
3063 }
3064 dev_kfree_skb_any(skb);
3065 i += j + 1;
3066 }
3067
3068 }
3069
3070 static void
3071 bnx2_free_rx_skbs(struct bnx2 *bp)
3072 {
3073 int i;
3074
3075 if (bp->rx_buf_ring == NULL)
3076 return;
3077
3078 for (i = 0; i < RX_DESC_CNT; i++) {
3079 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3080 struct sk_buff *skb = rx_buf->skb;
3081
3082 if (skb == 0)
3083 continue;
3084
3085 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3086 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3087
3088 rx_buf->skb = NULL;
3089
3090 dev_kfree_skb_any(skb);
3091 }
3092 }
3093
3094 static void
3095 bnx2_free_skbs(struct bnx2 *bp)
3096 {
3097 bnx2_free_tx_skbs(bp);
3098 bnx2_free_rx_skbs(bp);
3099 }
3100
3101 static int
3102 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3103 {
3104 int rc;
3105
3106 rc = bnx2_reset_chip(bp, reset_code);
3107 bnx2_free_skbs(bp);
3108 if (rc)
3109 return rc;
3110
3111 bnx2_init_chip(bp);
3112 bnx2_init_tx_ring(bp);
3113 bnx2_init_rx_ring(bp);
3114 return 0;
3115 }
3116
3117 static int
3118 bnx2_init_nic(struct bnx2 *bp)
3119 {
3120 int rc;
3121
3122 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3123 return rc;
3124
3125 bnx2_init_phy(bp);
3126 bnx2_set_link(bp);
3127 return 0;
3128 }
3129
3130 static int
3131 bnx2_test_registers(struct bnx2 *bp)
3132 {
3133 int ret;
3134 int i;
3135 static struct {
3136 u16 offset;
3137 u16 flags;
3138 u32 rw_mask;
3139 u32 ro_mask;
3140 } reg_tbl[] = {
3141 { 0x006c, 0, 0x00000000, 0x0000003f },
3142 { 0x0090, 0, 0xffffffff, 0x00000000 },
3143 { 0x0094, 0, 0x00000000, 0x00000000 },
3144
3145 { 0x0404, 0, 0x00003f00, 0x00000000 },
3146 { 0x0418, 0, 0x00000000, 0xffffffff },
3147 { 0x041c, 0, 0x00000000, 0xffffffff },
3148 { 0x0420, 0, 0x00000000, 0x80ffffff },
3149 { 0x0424, 0, 0x00000000, 0x00000000 },
3150 { 0x0428, 0, 0x00000000, 0x00000001 },
3151 { 0x0450, 0, 0x00000000, 0x0000ffff },
3152 { 0x0454, 0, 0x00000000, 0xffffffff },
3153 { 0x0458, 0, 0x00000000, 0xffffffff },
3154
3155 { 0x0808, 0, 0x00000000, 0xffffffff },
3156 { 0x0854, 0, 0x00000000, 0xffffffff },
3157 { 0x0868, 0, 0x00000000, 0x77777777 },
3158 { 0x086c, 0, 0x00000000, 0x77777777 },
3159 { 0x0870, 0, 0x00000000, 0x77777777 },
3160 { 0x0874, 0, 0x00000000, 0x77777777 },
3161
3162 { 0x0c00, 0, 0x00000000, 0x00000001 },
3163 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3164 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3165 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3166 { 0x0c30, 0, 0x00000000, 0xffffffff },
3167 { 0x0c34, 0, 0x00000000, 0xffffffff },
3168 { 0x0c38, 0, 0x00000000, 0xffffffff },
3169 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3170 { 0x0c40, 0, 0x00000000, 0xffffffff },
3171 { 0x0c44, 0, 0x00000000, 0xffffffff },
3172 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3173 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3174 { 0x0c50, 0, 0x00000000, 0xffffffff },
3175 { 0x0c54, 0, 0x00000000, 0xffffffff },
3176 { 0x0c58, 0, 0x00000000, 0xffffffff },
3177 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3178 { 0x0c60, 0, 0x00000000, 0xffffffff },
3179 { 0x0c64, 0, 0x00000000, 0xffffffff },
3180 { 0x0c68, 0, 0x00000000, 0xffffffff },
3181 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3182 { 0x0c70, 0, 0x00000000, 0xffffffff },
3183 { 0x0c74, 0, 0x00000000, 0xffffffff },
3184 { 0x0c78, 0, 0x00000000, 0xffffffff },
3185 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3186 { 0x0c80, 0, 0x00000000, 0xffffffff },
3187 { 0x0c84, 0, 0x00000000, 0xffffffff },
3188 { 0x0c88, 0, 0x00000000, 0xffffffff },
3189 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3190 { 0x0c90, 0, 0x00000000, 0xffffffff },
3191 { 0x0c94, 0, 0x00000000, 0xffffffff },
3192 { 0x0c98, 0, 0x00000000, 0xffffffff },
3193 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3194 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3195 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3196 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3197 { 0x0cac, 0, 0x00000000, 0xffffffff },
3198 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3199 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3200 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3201 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3202 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3203 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3204 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3205 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3206 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3207 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3208 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3209 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3210 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3211 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3212 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3213 { 0x0cec, 0, 0x00000000, 0xffffffff },
3214 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3215 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3216 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3217 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3218 { 0x0d00, 0, 0x00000000, 0xffffffff },
3219 { 0x0d04, 0, 0x00000000, 0xffffffff },
3220
3221 { 0x1000, 0, 0x00000000, 0x00000001 },
3222 { 0x1004, 0, 0x00000000, 0x000f0001 },
3223 { 0x1044, 0, 0x00000000, 0xffc003ff },
3224 { 0x1080, 0, 0x00000000, 0x0001ffff },
3225 { 0x1084, 0, 0x00000000, 0xffffffff },
3226 { 0x1088, 0, 0x00000000, 0xffffffff },
3227 { 0x108c, 0, 0x00000000, 0xffffffff },
3228 { 0x1090, 0, 0x00000000, 0xffffffff },
3229 { 0x1094, 0, 0x00000000, 0xffffffff },
3230 { 0x1098, 0, 0x00000000, 0xffffffff },
3231 { 0x109c, 0, 0x00000000, 0xffffffff },
3232 { 0x10a0, 0, 0x00000000, 0xffffffff },
3233
3234 { 0x1408, 0, 0x01c00800, 0x00000000 },
3235 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3236 { 0x14a8, 0, 0x00000000, 0x000001ff },
3237 { 0x14ac, 0, 0x4fffffff, 0x10000000 },
3238 { 0x14b0, 0, 0x00000002, 0x00000001 },
3239 { 0x14b8, 0, 0x00000000, 0x00000000 },
3240 { 0x14c0, 0, 0x00000000, 0x00000009 },
3241 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3242 { 0x14cc, 0, 0x00000000, 0x00000001 },
3243 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3244 { 0x1500, 0, 0x00000000, 0xffffffff },
3245 { 0x1504, 0, 0x00000000, 0xffffffff },
3246 { 0x1508, 0, 0x00000000, 0xffffffff },
3247 { 0x150c, 0, 0x00000000, 0xffffffff },
3248 { 0x1510, 0, 0x00000000, 0xffffffff },
3249 { 0x1514, 0, 0x00000000, 0xffffffff },
3250 { 0x1518, 0, 0x00000000, 0xffffffff },
3251 { 0x151c, 0, 0x00000000, 0xffffffff },
3252 { 0x1520, 0, 0x00000000, 0xffffffff },
3253 { 0x1524, 0, 0x00000000, 0xffffffff },
3254 { 0x1528, 0, 0x00000000, 0xffffffff },
3255 { 0x152c, 0, 0x00000000, 0xffffffff },
3256 { 0x1530, 0, 0x00000000, 0xffffffff },
3257 { 0x1534, 0, 0x00000000, 0xffffffff },
3258 { 0x1538, 0, 0x00000000, 0xffffffff },
3259 { 0x153c, 0, 0x00000000, 0xffffffff },
3260 { 0x1540, 0, 0x00000000, 0xffffffff },
3261 { 0x1544, 0, 0x00000000, 0xffffffff },
3262 { 0x1548, 0, 0x00000000, 0xffffffff },
3263 { 0x154c, 0, 0x00000000, 0xffffffff },
3264 { 0x1550, 0, 0x00000000, 0xffffffff },
3265 { 0x1554, 0, 0x00000000, 0xffffffff },
3266 { 0x1558, 0, 0x00000000, 0xffffffff },
3267 { 0x1600, 0, 0x00000000, 0xffffffff },
3268 { 0x1604, 0, 0x00000000, 0xffffffff },
3269 { 0x1608, 0, 0x00000000, 0xffffffff },
3270 { 0x160c, 0, 0x00000000, 0xffffffff },
3271 { 0x1610, 0, 0x00000000, 0xffffffff },
3272 { 0x1614, 0, 0x00000000, 0xffffffff },
3273 { 0x1618, 0, 0x00000000, 0xffffffff },
3274 { 0x161c, 0, 0x00000000, 0xffffffff },
3275 { 0x1620, 0, 0x00000000, 0xffffffff },
3276 { 0x1624, 0, 0x00000000, 0xffffffff },
3277 { 0x1628, 0, 0x00000000, 0xffffffff },
3278 { 0x162c, 0, 0x00000000, 0xffffffff },
3279 { 0x1630, 0, 0x00000000, 0xffffffff },
3280 { 0x1634, 0, 0x00000000, 0xffffffff },
3281 { 0x1638, 0, 0x00000000, 0xffffffff },
3282 { 0x163c, 0, 0x00000000, 0xffffffff },
3283 { 0x1640, 0, 0x00000000, 0xffffffff },
3284 { 0x1644, 0, 0x00000000, 0xffffffff },
3285 { 0x1648, 0, 0x00000000, 0xffffffff },
3286 { 0x164c, 0, 0x00000000, 0xffffffff },
3287 { 0x1650, 0, 0x00000000, 0xffffffff },
3288 { 0x1654, 0, 0x00000000, 0xffffffff },
3289
3290 { 0x1800, 0, 0x00000000, 0x00000001 },
3291 { 0x1804, 0, 0x00000000, 0x00000003 },
3292 { 0x1840, 0, 0x00000000, 0xffffffff },
3293 { 0x1844, 0, 0x00000000, 0xffffffff },
3294 { 0x1848, 0, 0x00000000, 0xffffffff },
3295 { 0x184c, 0, 0x00000000, 0xffffffff },
3296 { 0x1850, 0, 0x00000000, 0xffffffff },
3297 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3298 { 0x1904, 0, 0xffffffff, 0x00000000 },
3299 { 0x190c, 0, 0xffffffff, 0x00000000 },
3300 { 0x1914, 0, 0xffffffff, 0x00000000 },
3301 { 0x191c, 0, 0xffffffff, 0x00000000 },
3302 { 0x1924, 0, 0xffffffff, 0x00000000 },
3303 { 0x192c, 0, 0xffffffff, 0x00000000 },
3304 { 0x1934, 0, 0xffffffff, 0x00000000 },
3305 { 0x193c, 0, 0xffffffff, 0x00000000 },
3306 { 0x1944, 0, 0xffffffff, 0x00000000 },
3307 { 0x194c, 0, 0xffffffff, 0x00000000 },
3308 { 0x1954, 0, 0xffffffff, 0x00000000 },
3309 { 0x195c, 0, 0xffffffff, 0x00000000 },
3310 { 0x1964, 0, 0xffffffff, 0x00000000 },
3311 { 0x196c, 0, 0xffffffff, 0x00000000 },
3312 { 0x1974, 0, 0xffffffff, 0x00000000 },
3313 { 0x197c, 0, 0xffffffff, 0x00000000 },
3314 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3315
3316 { 0x1c00, 0, 0x00000000, 0x00000001 },
3317 { 0x1c04, 0, 0x00000000, 0x00000003 },
3318 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3319 { 0x1c40, 0, 0x00000000, 0xffffffff },
3320 { 0x1c44, 0, 0x00000000, 0xffffffff },
3321 { 0x1c48, 0, 0x00000000, 0xffffffff },
3322 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3323 { 0x1c50, 0, 0x00000000, 0xffffffff },
3324 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3325 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3326 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3327 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3328 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3329 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3330 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3331 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3332 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3333 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3334 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3335 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3336 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3337 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3338 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3339 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3340 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3341 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3342
3343 { 0x2004, 0, 0x00000000, 0x0337000f },
3344 { 0x2008, 0, 0xffffffff, 0x00000000 },
3345 { 0x200c, 0, 0xffffffff, 0x00000000 },
3346 { 0x2010, 0, 0xffffffff, 0x00000000 },
3347 { 0x2014, 0, 0x801fff80, 0x00000000 },
3348 { 0x2018, 0, 0x000003ff, 0x00000000 },
3349
3350 { 0x2800, 0, 0x00000000, 0x00000001 },
3351 { 0x2804, 0, 0x00000000, 0x00003f01 },
3352 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3353 { 0x2810, 0, 0xffff0000, 0x00000000 },
3354 { 0x2814, 0, 0xffff0000, 0x00000000 },
3355 { 0x2818, 0, 0xffff0000, 0x00000000 },
3356 { 0x281c, 0, 0xffff0000, 0x00000000 },
3357 { 0x2834, 0, 0xffffffff, 0x00000000 },
3358 { 0x2840, 0, 0x00000000, 0xffffffff },
3359 { 0x2844, 0, 0x00000000, 0xffffffff },
3360 { 0x2848, 0, 0xffffffff, 0x00000000 },
3361 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3362
3363 { 0x2c00, 0, 0x00000000, 0x00000011 },
3364 { 0x2c04, 0, 0x00000000, 0x00030007 },
3365
3366 { 0x3000, 0, 0x00000000, 0x00000001 },
3367 { 0x3004, 0, 0x00000000, 0x007007ff },
3368 { 0x3008, 0, 0x00000003, 0x00000000 },
3369 { 0x300c, 0, 0xffffffff, 0x00000000 },
3370 { 0x3010, 0, 0xffffffff, 0x00000000 },
3371 { 0x3014, 0, 0xffffffff, 0x00000000 },
3372 { 0x3034, 0, 0xffffffff, 0x00000000 },
3373 { 0x3038, 0, 0xffffffff, 0x00000000 },
3374 { 0x3050, 0, 0x00000001, 0x00000000 },
3375
3376 { 0x3c00, 0, 0x00000000, 0x00000001 },
3377 { 0x3c04, 0, 0x00000000, 0x00070000 },
3378 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3379 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3380 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3381 { 0x3c14, 0, 0x00000000, 0xffffffff },
3382 { 0x3c18, 0, 0x00000000, 0xffffffff },
3383 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3384 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3385 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3386 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3387 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3388 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3389 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3390 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3391 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3392 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3393 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3394 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3395 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3396 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3397 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3398 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3399 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3400 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3401 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3402 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3403 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3404 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3405 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3406 { 0x3c78, 0, 0x00000000, 0x00000000 },
3407 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3408 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3409 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3410 { 0x3c88, 0, 0x00000000, 0xffffffff },
3411 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3412
3413 { 0x4000, 0, 0x00000000, 0x00000001 },
3414 { 0x4004, 0, 0x00000000, 0x00030000 },
3415 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3416 { 0x400c, 0, 0xffffffff, 0x00000000 },
3417 { 0x4088, 0, 0x00000000, 0x00070303 },
3418
3419 { 0x4400, 0, 0x00000000, 0x00000001 },
3420 { 0x4404, 0, 0x00000000, 0x00003f01 },
3421 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3422 { 0x440c, 0, 0xffffffff, 0x00000000 },
3423 { 0x4410, 0, 0xffff, 0x0000 },
3424 { 0x4414, 0, 0xffff, 0x0000 },
3425 { 0x4418, 0, 0xffff, 0x0000 },
3426 { 0x441c, 0, 0xffff, 0x0000 },
3427 { 0x4428, 0, 0xffffffff, 0x00000000 },
3428 { 0x442c, 0, 0xffffffff, 0x00000000 },
3429 { 0x4430, 0, 0xffffffff, 0x00000000 },
3430 { 0x4434, 0, 0xffffffff, 0x00000000 },
3431 { 0x4438, 0, 0xffffffff, 0x00000000 },
3432 { 0x443c, 0, 0xffffffff, 0x00000000 },
3433 { 0x4440, 0, 0xffffffff, 0x00000000 },
3434 { 0x4444, 0, 0xffffffff, 0x00000000 },
3435
3436 { 0x4c00, 0, 0x00000000, 0x00000001 },
3437 { 0x4c04, 0, 0x00000000, 0x0000003f },
3438 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3439 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3440 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3441 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3442 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3443 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3444 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3445 { 0x4c50, 0, 0x00000000, 0xffffffff },
3446
3447 { 0x5004, 0, 0x00000000, 0x0000007f },
3448 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3449 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3450
3451 { 0x5400, 0, 0x00000008, 0x00000001 },
3452 { 0x5404, 0, 0x00000000, 0x0000003f },
3453 { 0x5408, 0, 0x0000001f, 0x00000000 },
3454 { 0x540c, 0, 0xffffffff, 0x00000000 },
3455 { 0x5410, 0, 0xffffffff, 0x00000000 },
3456 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3457 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3458 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3459 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3460 { 0x5428, 0, 0x000000ff, 0x00000000 },
3461 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3462 { 0x5430, 0, 0x001fff80, 0x00000000 },
3463 { 0x5438, 0, 0xffffffff, 0x00000000 },
3464 { 0x543c, 0, 0xffffffff, 0x00000000 },
3465 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3466
3467 { 0x5c00, 0, 0x00000000, 0x00000001 },
3468 { 0x5c04, 0, 0x00000000, 0x0003000f },
3469 { 0x5c08, 0, 0x00000003, 0x00000000 },
3470 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3471 { 0x5c10, 0, 0x00000000, 0xffffffff },
3472 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3473 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3474 { 0x5c88, 0, 0x00000000, 0x00077373 },
3475 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3476
3477 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3478 { 0x680c, 0, 0xffffffff, 0x00000000 },
3479 { 0x6810, 0, 0xffffffff, 0x00000000 },
3480 { 0x6814, 0, 0xffffffff, 0x00000000 },
3481 { 0x6818, 0, 0xffffffff, 0x00000000 },
3482 { 0x681c, 0, 0xffffffff, 0x00000000 },
3483 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3484 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3485 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3486 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3487 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3488 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3489 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3490 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3491 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3492 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3493 { 0x684c, 0, 0xffffffff, 0x00000000 },
3494 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3495 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3496 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3497 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3498 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3499 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3500
3501 { 0xffff, 0, 0x00000000, 0x00000000 },
3502 };
3503
3504 ret = 0;
3505 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3506 u32 offset, rw_mask, ro_mask, save_val, val;
3507
3508 offset = (u32) reg_tbl[i].offset;
3509 rw_mask = reg_tbl[i].rw_mask;
3510 ro_mask = reg_tbl[i].ro_mask;
3511
3512 save_val = readl(bp->regview + offset);
3513
3514 writel(0, bp->regview + offset);
3515
3516 val = readl(bp->regview + offset);
3517 if ((val & rw_mask) != 0) {
3518 goto reg_test_err;
3519 }
3520
3521 if ((val & ro_mask) != (save_val & ro_mask)) {
3522 goto reg_test_err;
3523 }
3524
3525 writel(0xffffffff, bp->regview + offset);
3526
3527 val = readl(bp->regview + offset);
3528 if ((val & rw_mask) != rw_mask) {
3529 goto reg_test_err;
3530 }
3531
3532 if ((val & ro_mask) != (save_val & ro_mask)) {
3533 goto reg_test_err;
3534 }
3535
3536 writel(save_val, bp->regview + offset);
3537 continue;
3538
3539 reg_test_err:
3540 writel(save_val, bp->regview + offset);
3541 ret = -ENODEV;
3542 break;
3543 }
3544 return ret;
3545 }
3546
3547 static int
3548 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3549 {
3550 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3551 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3552 int i;
3553
3554 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3555 u32 offset;
3556
3557 for (offset = 0; offset < size; offset += 4) {
3558
3559 REG_WR_IND(bp, start + offset, test_pattern[i]);
3560
3561 if (REG_RD_IND(bp, start + offset) !=
3562 test_pattern[i]) {
3563 return -ENODEV;
3564 }
3565 }
3566 }
3567 return 0;
3568 }
3569
3570 static int
3571 bnx2_test_memory(struct bnx2 *bp)
3572 {
3573 int ret = 0;
3574 int i;
3575 static struct {
3576 u32 offset;
3577 u32 len;
3578 } mem_tbl[] = {
3579 { 0x60000, 0x4000 },
3580 { 0xa0000, 0x4000 },
3581 { 0xe0000, 0x4000 },
3582 { 0x120000, 0x4000 },
3583 { 0x1a0000, 0x4000 },
3584 { 0x160000, 0x4000 },
3585 { 0xffffffff, 0 },
3586 };
3587
3588 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3589 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3590 mem_tbl[i].len)) != 0) {
3591 return ret;
3592 }
3593 }
3594
3595 return ret;
3596 }
3597
3598 static int
3599 bnx2_test_loopback(struct bnx2 *bp)
3600 {
3601 unsigned int pkt_size, num_pkts, i;
3602 struct sk_buff *skb, *rx_skb;
3603 unsigned char *packet;
3604 u16 rx_start_idx, rx_idx, send_idx;
3605 u32 send_bseq, val;
3606 dma_addr_t map;
3607 struct tx_bd *txbd;
3608 struct sw_bd *rx_buf;
3609 struct l2_fhdr *rx_hdr;
3610 int ret = -ENODEV;
3611
3612 if (!netif_running(bp->dev))
3613 return -ENODEV;
3614
3615 bp->loopback = MAC_LOOPBACK;
3616 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3617 bnx2_set_mac_loopback(bp);
3618
3619 pkt_size = 1514;
3620 skb = dev_alloc_skb(pkt_size);
3621 packet = skb_put(skb, pkt_size);
3622 memcpy(packet, bp->mac_addr, 6);
3623 memset(packet + 6, 0x0, 8);
3624 for (i = 14; i < pkt_size; i++)
3625 packet[i] = (unsigned char) (i & 0xff);
3626
3627 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3628 PCI_DMA_TODEVICE);
3629
3630 val = REG_RD(bp, BNX2_HC_COMMAND);
3631 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3632 REG_RD(bp, BNX2_HC_COMMAND);
3633
3634 udelay(5);
3635 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3636
3637 send_idx = 0;
3638 send_bseq = 0;
3639 num_pkts = 0;
3640
3641 txbd = &bp->tx_desc_ring[send_idx];
3642
3643 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3644 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3645 txbd->tx_bd_mss_nbytes = pkt_size;
3646 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3647
3648 num_pkts++;
3649 send_idx = NEXT_TX_BD(send_idx);
3650
3651 send_bseq += pkt_size;
3652
3653 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3654 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3655
3656
3657 udelay(100);
3658
3659 val = REG_RD(bp, BNX2_HC_COMMAND);
3660 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3661 REG_RD(bp, BNX2_HC_COMMAND);
3662
3663 udelay(5);
3664
3665 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3666 dev_kfree_skb_irq(skb);
3667
3668 if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3669 goto loopback_test_done;
3670 }
3671
3672 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3673 if (rx_idx != rx_start_idx + num_pkts) {
3674 goto loopback_test_done;
3675 }
3676
3677 rx_buf = &bp->rx_buf_ring[rx_start_idx];
3678 rx_skb = rx_buf->skb;
3679
3680 rx_hdr = (struct l2_fhdr *) rx_skb->data;
3681 skb_reserve(rx_skb, bp->rx_offset);
3682
3683 pci_dma_sync_single_for_cpu(bp->pdev,
3684 pci_unmap_addr(rx_buf, mapping),
3685 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3686
3687 if (rx_hdr->l2_fhdr_errors &
3688 (L2_FHDR_ERRORS_BAD_CRC |
3689 L2_FHDR_ERRORS_PHY_DECODE |
3690 L2_FHDR_ERRORS_ALIGNMENT |
3691 L2_FHDR_ERRORS_TOO_SHORT |
3692 L2_FHDR_ERRORS_GIANT_FRAME)) {
3693
3694 goto loopback_test_done;
3695 }
3696
3697 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3698 goto loopback_test_done;
3699 }
3700
3701 for (i = 14; i < pkt_size; i++) {
3702 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3703 goto loopback_test_done;
3704 }
3705 }
3706
3707 ret = 0;
3708
3709 loopback_test_done:
3710 bp->loopback = 0;
3711 return ret;
3712 }
3713
3714 #define NVRAM_SIZE 0x200
3715 #define CRC32_RESIDUAL 0xdebb20e3
3716
3717 static int
3718 bnx2_test_nvram(struct bnx2 *bp)
3719 {
3720 u32 buf[NVRAM_SIZE / 4];
3721 u8 *data = (u8 *) buf;
3722 int rc = 0;
3723 u32 magic, csum;
3724
3725 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
3726 goto test_nvram_done;
3727
3728 magic = be32_to_cpu(buf[0]);
3729 if (magic != 0x669955aa) {
3730 rc = -ENODEV;
3731 goto test_nvram_done;
3732 }
3733
3734 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
3735 goto test_nvram_done;
3736
3737 csum = ether_crc_le(0x100, data);
3738 if (csum != CRC32_RESIDUAL) {
3739 rc = -ENODEV;
3740 goto test_nvram_done;
3741 }
3742
3743 csum = ether_crc_le(0x100, data + 0x100);
3744 if (csum != CRC32_RESIDUAL) {
3745 rc = -ENODEV;
3746 }
3747
3748 test_nvram_done:
3749 return rc;
3750 }
3751
3752 static int
3753 bnx2_test_link(struct bnx2 *bp)
3754 {
3755 u32 bmsr;
3756
3757 spin_lock_bh(&bp->phy_lock);
3758 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3759 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3760 spin_unlock_bh(&bp->phy_lock);
3761
3762 if (bmsr & BMSR_LSTATUS) {
3763 return 0;
3764 }
3765 return -ENODEV;
3766 }
3767
3768 static int
3769 bnx2_test_intr(struct bnx2 *bp)
3770 {
3771 int i;
3772 u32 val;
3773 u16 status_idx;
3774
3775 if (!netif_running(bp->dev))
3776 return -ENODEV;
3777
3778 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
3779
3780 /* This register is not touched during run-time. */
3781 val = REG_RD(bp, BNX2_HC_COMMAND);
3782 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
3783 REG_RD(bp, BNX2_HC_COMMAND);
3784
3785 for (i = 0; i < 10; i++) {
3786 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
3787 status_idx) {
3788
3789 break;
3790 }
3791
3792 msleep_interruptible(10);
3793 }
3794 if (i < 10)
3795 return 0;
3796
3797 return -ENODEV;
3798 }
3799
3800 static void
3801 bnx2_timer(unsigned long data)
3802 {
3803 struct bnx2 *bp = (struct bnx2 *) data;
3804 u32 msg;
3805
3806 if (!netif_running(bp->dev))
3807 return;
3808
3809 if (atomic_read(&bp->intr_sem) != 0)
3810 goto bnx2_restart_timer;
3811
3812 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
3813 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
3814
3815 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
3816 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
3817
3818 spin_lock(&bp->phy_lock);
3819 if (bp->serdes_an_pending) {
3820 bp->serdes_an_pending--;
3821 }
3822 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
3823 u32 bmcr;
3824
3825 bp->current_interval = bp->timer_interval;
3826
3827 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3828
3829 if (bmcr & BMCR_ANENABLE) {
3830 u32 phy1, phy2;
3831
3832 bnx2_write_phy(bp, 0x1c, 0x7c00);
3833 bnx2_read_phy(bp, 0x1c, &phy1);
3834
3835 bnx2_write_phy(bp, 0x17, 0x0f01);
3836 bnx2_read_phy(bp, 0x15, &phy2);
3837 bnx2_write_phy(bp, 0x17, 0x0f01);
3838 bnx2_read_phy(bp, 0x15, &phy2);
3839
3840 if ((phy1 & 0x10) && /* SIGNAL DETECT */
3841 !(phy2 & 0x20)) { /* no CONFIG */
3842
3843 bmcr &= ~BMCR_ANENABLE;
3844 bmcr |= BMCR_SPEED1000 |
3845 BMCR_FULLDPLX;
3846 bnx2_write_phy(bp, MII_BMCR, bmcr);
3847 bp->phy_flags |=
3848 PHY_PARALLEL_DETECT_FLAG;
3849 }
3850 }
3851 }
3852 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
3853 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
3854 u32 phy2;
3855
3856 bnx2_write_phy(bp, 0x17, 0x0f01);
3857 bnx2_read_phy(bp, 0x15, &phy2);
3858 if (phy2 & 0x20) {
3859 u32 bmcr;
3860
3861 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3862 bmcr |= BMCR_ANENABLE;
3863 bnx2_write_phy(bp, MII_BMCR, bmcr);
3864
3865 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
3866
3867 }
3868 }
3869 else
3870 bp->current_interval = bp->timer_interval;
3871
3872 spin_unlock(&bp->phy_lock);
3873 }
3874
3875 bnx2_restart_timer:
3876 mod_timer(&bp->timer, jiffies + bp->current_interval);
3877 }
3878
3879 /* Called with rtnl_lock */
3880 static int
3881 bnx2_open(struct net_device *dev)
3882 {
3883 struct bnx2 *bp = dev->priv;
3884 int rc;
3885
3886 bnx2_set_power_state(bp, PCI_D0);
3887 bnx2_disable_int(bp);
3888
3889 rc = bnx2_alloc_mem(bp);
3890 if (rc)
3891 return rc;
3892
3893 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
3894 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
3895 !disable_msi) {
3896
3897 if (pci_enable_msi(bp->pdev) == 0) {
3898 bp->flags |= USING_MSI_FLAG;
3899 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
3900 dev);
3901 }
3902 else {
3903 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3904 SA_SHIRQ, dev->name, dev);
3905 }
3906 }
3907 else {
3908 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
3909 dev->name, dev);
3910 }
3911 if (rc) {
3912 bnx2_free_mem(bp);
3913 return rc;
3914 }
3915
3916 rc = bnx2_init_nic(bp);
3917
3918 if (rc) {
3919 free_irq(bp->pdev->irq, dev);
3920 if (bp->flags & USING_MSI_FLAG) {
3921 pci_disable_msi(bp->pdev);
3922 bp->flags &= ~USING_MSI_FLAG;
3923 }
3924 bnx2_free_skbs(bp);
3925 bnx2_free_mem(bp);
3926 return rc;
3927 }
3928
3929 mod_timer(&bp->timer, jiffies + bp->current_interval);
3930
3931 atomic_set(&bp->intr_sem, 0);
3932
3933 bnx2_enable_int(bp);
3934
3935 if (bp->flags & USING_MSI_FLAG) {
3936 /* Test MSI to make sure it is working
3937 * If MSI test fails, go back to INTx mode
3938 */
3939 if (bnx2_test_intr(bp) != 0) {
3940 printk(KERN_WARNING PFX "%s: No interrupt was generated"
3941 " using MSI, switching to INTx mode. Please"
3942 " report this failure to the PCI maintainer"
3943 " and include system chipset information.\n",
3944 bp->dev->name);
3945
3946 bnx2_disable_int(bp);
3947 free_irq(bp->pdev->irq, dev);
3948 pci_disable_msi(bp->pdev);
3949 bp->flags &= ~USING_MSI_FLAG;
3950
3951 rc = bnx2_init_nic(bp);
3952
3953 if (!rc) {
3954 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3955 SA_SHIRQ, dev->name, dev);
3956 }
3957 if (rc) {
3958 bnx2_free_skbs(bp);
3959 bnx2_free_mem(bp);
3960 del_timer_sync(&bp->timer);
3961 return rc;
3962 }
3963 bnx2_enable_int(bp);
3964 }
3965 }
3966 if (bp->flags & USING_MSI_FLAG) {
3967 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
3968 }
3969
3970 netif_start_queue(dev);
3971
3972 return 0;
3973 }
3974
3975 static void
3976 bnx2_reset_task(void *data)
3977 {
3978 struct bnx2 *bp = data;
3979
3980 if (!netif_running(bp->dev))
3981 return;
3982
3983 bp->in_reset_task = 1;
3984 bnx2_netif_stop(bp);
3985
3986 bnx2_init_nic(bp);
3987
3988 atomic_set(&bp->intr_sem, 1);
3989 bnx2_netif_start(bp);
3990 bp->in_reset_task = 0;
3991 }
3992
3993 static void
3994 bnx2_tx_timeout(struct net_device *dev)
3995 {
3996 struct bnx2 *bp = dev->priv;
3997
3998 /* This allows the netif to be shutdown gracefully before resetting */
3999 schedule_work(&bp->reset_task);
4000 }
4001
4002 #ifdef BCM_VLAN
4003 /* Called with rtnl_lock */
4004 static void
4005 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4006 {
4007 struct bnx2 *bp = dev->priv;
4008
4009 bnx2_netif_stop(bp);
4010
4011 bp->vlgrp = vlgrp;
4012 bnx2_set_rx_mode(dev);
4013
4014 bnx2_netif_start(bp);
4015 }
4016
4017 /* Called with rtnl_lock */
4018 static void
4019 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4020 {
4021 struct bnx2 *bp = dev->priv;
4022
4023 bnx2_netif_stop(bp);
4024
4025 if (bp->vlgrp)
4026 bp->vlgrp->vlan_devices[vid] = NULL;
4027 bnx2_set_rx_mode(dev);
4028
4029 bnx2_netif_start(bp);
4030 }
4031 #endif
4032
4033 /* Called with dev->xmit_lock.
4034 * hard_start_xmit is pseudo-lockless - a lock is only required when
4035 * the tx queue is full. This way, we get the benefit of lockless
4036 * operations most of the time without the complexities to handle
4037 * netif_stop_queue/wake_queue race conditions.
4038 */
4039 static int
4040 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4041 {
4042 struct bnx2 *bp = dev->priv;
4043 dma_addr_t mapping;
4044 struct tx_bd *txbd;
4045 struct sw_bd *tx_buf;
4046 u32 len, vlan_tag_flags, last_frag, mss;
4047 u16 prod, ring_prod;
4048 int i;
4049
4050 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4051 netif_stop_queue(dev);
4052 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4053 dev->name);
4054
4055 return NETDEV_TX_BUSY;
4056 }
4057 len = skb_headlen(skb);
4058 prod = bp->tx_prod;
4059 ring_prod = TX_RING_IDX(prod);
4060
4061 vlan_tag_flags = 0;
4062 if (skb->ip_summed == CHECKSUM_HW) {
4063 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4064 }
4065
4066 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4067 vlan_tag_flags |=
4068 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4069 }
4070 #ifdef BCM_TSO
4071 if ((mss = skb_shinfo(skb)->tso_size) &&
4072 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4073 u32 tcp_opt_len, ip_tcp_len;
4074
4075 if (skb_header_cloned(skb) &&
4076 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4077 dev_kfree_skb(skb);
4078 return NETDEV_TX_OK;
4079 }
4080
4081 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4082 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4083
4084 tcp_opt_len = 0;
4085 if (skb->h.th->doff > 5) {
4086 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4087 }
4088 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4089
4090 skb->nh.iph->check = 0;
4091 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4092 skb->h.th->check =
4093 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4094 skb->nh.iph->daddr,
4095 0, IPPROTO_TCP, 0);
4096
4097 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4098 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4099 (tcp_opt_len >> 2)) << 8;
4100 }
4101 }
4102 else
4103 #endif
4104 {
4105 mss = 0;
4106 }
4107
4108 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4109
4110 tx_buf = &bp->tx_buf_ring[ring_prod];
4111 tx_buf->skb = skb;
4112 pci_unmap_addr_set(tx_buf, mapping, mapping);
4113
4114 txbd = &bp->tx_desc_ring[ring_prod];
4115
4116 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4117 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4118 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4119 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4120
4121 last_frag = skb_shinfo(skb)->nr_frags;
4122
4123 for (i = 0; i < last_frag; i++) {
4124 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4125
4126 prod = NEXT_TX_BD(prod);
4127 ring_prod = TX_RING_IDX(prod);
4128 txbd = &bp->tx_desc_ring[ring_prod];
4129
4130 len = frag->size;
4131 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4132 len, PCI_DMA_TODEVICE);
4133 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4134 mapping, mapping);
4135
4136 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4137 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4138 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4139 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4140
4141 }
4142 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4143
4144 prod = NEXT_TX_BD(prod);
4145 bp->tx_prod_bseq += skb->len;
4146
4147 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4148 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4149
4150 mmiowb();
4151
4152 bp->tx_prod = prod;
4153 dev->trans_start = jiffies;
4154
4155 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4156 spin_lock(&bp->tx_lock);
4157 netif_stop_queue(dev);
4158
4159 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4160 netif_wake_queue(dev);
4161 spin_unlock(&bp->tx_lock);
4162 }
4163
4164 return NETDEV_TX_OK;
4165 }
4166
4167 /* Called with rtnl_lock */
4168 static int
4169 bnx2_close(struct net_device *dev)
4170 {
4171 struct bnx2 *bp = dev->priv;
4172 u32 reset_code;
4173
4174 /* Calling flush_scheduled_work() may deadlock because
4175 * linkwatch_event() may be on the workqueue and it will try to get
4176 * the rtnl_lock which we are holding.
4177 */
4178 while (bp->in_reset_task)
4179 msleep(1);
4180
4181 bnx2_netif_stop(bp);
4182 del_timer_sync(&bp->timer);
4183 if (bp->wol)
4184 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4185 else
4186 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4187 bnx2_reset_chip(bp, reset_code);
4188 free_irq(bp->pdev->irq, dev);
4189 if (bp->flags & USING_MSI_FLAG) {
4190 pci_disable_msi(bp->pdev);
4191 bp->flags &= ~USING_MSI_FLAG;
4192 }
4193 bnx2_free_skbs(bp);
4194 bnx2_free_mem(bp);
4195 bp->link_up = 0;
4196 netif_carrier_off(bp->dev);
4197 bnx2_set_power_state(bp, PCI_D3hot);
4198 return 0;
4199 }
4200
4201 #define GET_NET_STATS64(ctr) \
4202 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4203 (unsigned long) (ctr##_lo)
4204
4205 #define GET_NET_STATS32(ctr) \
4206 (ctr##_lo)
4207
4208 #if (BITS_PER_LONG == 64)
4209 #define GET_NET_STATS GET_NET_STATS64
4210 #else
4211 #define GET_NET_STATS GET_NET_STATS32
4212 #endif
4213
4214 static struct net_device_stats *
4215 bnx2_get_stats(struct net_device *dev)
4216 {
4217 struct bnx2 *bp = dev->priv;
4218 struct statistics_block *stats_blk = bp->stats_blk;
4219 struct net_device_stats *net_stats = &bp->net_stats;
4220
4221 if (bp->stats_blk == NULL) {
4222 return net_stats;
4223 }
4224 net_stats->rx_packets =
4225 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4226 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4227 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4228
4229 net_stats->tx_packets =
4230 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4231 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4232 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4233
4234 net_stats->rx_bytes =
4235 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4236
4237 net_stats->tx_bytes =
4238 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4239
4240 net_stats->multicast =
4241 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4242
4243 net_stats->collisions =
4244 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4245
4246 net_stats->rx_length_errors =
4247 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4248 stats_blk->stat_EtherStatsOverrsizePkts);
4249
4250 net_stats->rx_over_errors =
4251 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4252
4253 net_stats->rx_frame_errors =
4254 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4255
4256 net_stats->rx_crc_errors =
4257 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4258
4259 net_stats->rx_errors = net_stats->rx_length_errors +
4260 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4261 net_stats->rx_crc_errors;
4262
4263 net_stats->tx_aborted_errors =
4264 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4265 stats_blk->stat_Dot3StatsLateCollisions);
4266
4267 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4268 net_stats->tx_carrier_errors = 0;
4269 else {
4270 net_stats->tx_carrier_errors =
4271 (unsigned long)
4272 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4273 }
4274
4275 net_stats->tx_errors =
4276 (unsigned long)
4277 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4278 +
4279 net_stats->tx_aborted_errors +
4280 net_stats->tx_carrier_errors;
4281
4282 return net_stats;
4283 }
4284
4285 /* All ethtool functions called with rtnl_lock */
4286
4287 static int
4288 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4289 {
4290 struct bnx2 *bp = dev->priv;
4291
4292 cmd->supported = SUPPORTED_Autoneg;
4293 if (bp->phy_flags & PHY_SERDES_FLAG) {
4294 cmd->supported |= SUPPORTED_1000baseT_Full |
4295 SUPPORTED_FIBRE;
4296
4297 cmd->port = PORT_FIBRE;
4298 }
4299 else {
4300 cmd->supported |= SUPPORTED_10baseT_Half |
4301 SUPPORTED_10baseT_Full |
4302 SUPPORTED_100baseT_Half |
4303 SUPPORTED_100baseT_Full |
4304 SUPPORTED_1000baseT_Full |
4305 SUPPORTED_TP;
4306
4307 cmd->port = PORT_TP;
4308 }
4309
4310 cmd->advertising = bp->advertising;
4311
4312 if (bp->autoneg & AUTONEG_SPEED) {
4313 cmd->autoneg = AUTONEG_ENABLE;
4314 }
4315 else {
4316 cmd->autoneg = AUTONEG_DISABLE;
4317 }
4318
4319 if (netif_carrier_ok(dev)) {
4320 cmd->speed = bp->line_speed;
4321 cmd->duplex = bp->duplex;
4322 }
4323 else {
4324 cmd->speed = -1;
4325 cmd->duplex = -1;
4326 }
4327
4328 cmd->transceiver = XCVR_INTERNAL;
4329 cmd->phy_address = bp->phy_addr;
4330
4331 return 0;
4332 }
4333
4334 static int
4335 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4336 {
4337 struct bnx2 *bp = dev->priv;
4338 u8 autoneg = bp->autoneg;
4339 u8 req_duplex = bp->req_duplex;
4340 u16 req_line_speed = bp->req_line_speed;
4341 u32 advertising = bp->advertising;
4342
4343 if (cmd->autoneg == AUTONEG_ENABLE) {
4344 autoneg |= AUTONEG_SPEED;
4345
4346 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4347
4348 /* allow advertising 1 speed */
4349 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4350 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4351 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4352 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4353
4354 if (bp->phy_flags & PHY_SERDES_FLAG)
4355 return -EINVAL;
4356
4357 advertising = cmd->advertising;
4358
4359 }
4360 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4361 advertising = cmd->advertising;
4362 }
4363 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4364 return -EINVAL;
4365 }
4366 else {
4367 if (bp->phy_flags & PHY_SERDES_FLAG) {
4368 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4369 }
4370 else {
4371 advertising = ETHTOOL_ALL_COPPER_SPEED;
4372 }
4373 }
4374 advertising |= ADVERTISED_Autoneg;
4375 }
4376 else {
4377 if (bp->phy_flags & PHY_SERDES_FLAG) {
4378 if ((cmd->speed != SPEED_1000) ||
4379 (cmd->duplex != DUPLEX_FULL)) {
4380 return -EINVAL;
4381 }
4382 }
4383 else if (cmd->speed == SPEED_1000) {
4384 return -EINVAL;
4385 }
4386 autoneg &= ~AUTONEG_SPEED;
4387 req_line_speed = cmd->speed;
4388 req_duplex = cmd->duplex;
4389 advertising = 0;
4390 }
4391
4392 bp->autoneg = autoneg;
4393 bp->advertising = advertising;
4394 bp->req_line_speed = req_line_speed;
4395 bp->req_duplex = req_duplex;
4396
4397 spin_lock_bh(&bp->phy_lock);
4398
4399 bnx2_setup_phy(bp);
4400
4401 spin_unlock_bh(&bp->phy_lock);
4402
4403 return 0;
4404 }
4405
4406 static void
4407 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4408 {
4409 struct bnx2 *bp = dev->priv;
4410
4411 strcpy(info->driver, DRV_MODULE_NAME);
4412 strcpy(info->version, DRV_MODULE_VERSION);
4413 strcpy(info->bus_info, pci_name(bp->pdev));
4414 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4415 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4416 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4417 info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4418 info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4419 info->fw_version[7] = 0;
4420 }
4421
4422 static void
4423 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4424 {
4425 struct bnx2 *bp = dev->priv;
4426
4427 if (bp->flags & NO_WOL_FLAG) {
4428 wol->supported = 0;
4429 wol->wolopts = 0;
4430 }
4431 else {
4432 wol->supported = WAKE_MAGIC;
4433 if (bp->wol)
4434 wol->wolopts = WAKE_MAGIC;
4435 else
4436 wol->wolopts = 0;
4437 }
4438 memset(&wol->sopass, 0, sizeof(wol->sopass));
4439 }
4440
4441 static int
4442 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4443 {
4444 struct bnx2 *bp = dev->priv;
4445
4446 if (wol->wolopts & ~WAKE_MAGIC)
4447 return -EINVAL;
4448
4449 if (wol->wolopts & WAKE_MAGIC) {
4450 if (bp->flags & NO_WOL_FLAG)
4451 return -EINVAL;
4452
4453 bp->wol = 1;
4454 }
4455 else {
4456 bp->wol = 0;
4457 }
4458 return 0;
4459 }
4460
4461 static int
4462 bnx2_nway_reset(struct net_device *dev)
4463 {
4464 struct bnx2 *bp = dev->priv;
4465 u32 bmcr;
4466
4467 if (!(bp->autoneg & AUTONEG_SPEED)) {
4468 return -EINVAL;
4469 }
4470
4471 spin_lock_bh(&bp->phy_lock);
4472
4473 /* Force a link down visible on the other side */
4474 if (bp->phy_flags & PHY_SERDES_FLAG) {
4475 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4476 spin_unlock_bh(&bp->phy_lock);
4477
4478 msleep(20);
4479
4480 spin_lock_bh(&bp->phy_lock);
4481 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4482 bp->current_interval = SERDES_AN_TIMEOUT;
4483 bp->serdes_an_pending = 1;
4484 mod_timer(&bp->timer, jiffies + bp->current_interval);
4485 }
4486 }
4487
4488 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4489 bmcr &= ~BMCR_LOOPBACK;
4490 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4491
4492 spin_unlock_bh(&bp->phy_lock);
4493
4494 return 0;
4495 }
4496
4497 static int
4498 bnx2_get_eeprom_len(struct net_device *dev)
4499 {
4500 struct bnx2 *bp = dev->priv;
4501
4502 if (bp->flash_info == 0)
4503 return 0;
4504
4505 return (int) bp->flash_info->total_size;
4506 }
4507
4508 static int
4509 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4510 u8 *eebuf)
4511 {
4512 struct bnx2 *bp = dev->priv;
4513 int rc;
4514
4515 if (eeprom->offset > bp->flash_info->total_size)
4516 return -EINVAL;
4517
4518 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4519 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4520
4521 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4522
4523 return rc;
4524 }
4525
4526 static int
4527 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4528 u8 *eebuf)
4529 {
4530 struct bnx2 *bp = dev->priv;
4531 int rc;
4532
4533 if (eeprom->offset > bp->flash_info->total_size)
4534 return -EINVAL;
4535
4536 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4537 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4538
4539 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4540
4541 return rc;
4542 }
4543
4544 static int
4545 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4546 {
4547 struct bnx2 *bp = dev->priv;
4548
4549 memset(coal, 0, sizeof(struct ethtool_coalesce));
4550
4551 coal->rx_coalesce_usecs = bp->rx_ticks;
4552 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4553 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4554 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4555
4556 coal->tx_coalesce_usecs = bp->tx_ticks;
4557 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4558 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4559 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4560
4561 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4562
4563 return 0;
4564 }
4565
4566 static int
4567 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4568 {
4569 struct bnx2 *bp = dev->priv;
4570
4571 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4572 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4573
4574 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4575 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4576
4577 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4578 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4579
4580 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4581 if (bp->rx_quick_cons_trip_int > 0xff)
4582 bp->rx_quick_cons_trip_int = 0xff;
4583
4584 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4585 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4586
4587 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4588 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4589
4590 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4591 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4592
4593 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4594 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4595 0xff;
4596
4597 bp->stats_ticks = coal->stats_block_coalesce_usecs;
4598 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4599 bp->stats_ticks &= 0xffff00;
4600
4601 if (netif_running(bp->dev)) {
4602 bnx2_netif_stop(bp);
4603 bnx2_init_nic(bp);
4604 bnx2_netif_start(bp);
4605 }
4606
4607 return 0;
4608 }
4609
4610 static void
4611 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4612 {
4613 struct bnx2 *bp = dev->priv;
4614
4615 ering->rx_max_pending = MAX_RX_DESC_CNT;
4616 ering->rx_mini_max_pending = 0;
4617 ering->rx_jumbo_max_pending = 0;
4618
4619 ering->rx_pending = bp->rx_ring_size;
4620 ering->rx_mini_pending = 0;
4621 ering->rx_jumbo_pending = 0;
4622
4623 ering->tx_max_pending = MAX_TX_DESC_CNT;
4624 ering->tx_pending = bp->tx_ring_size;
4625 }
4626
4627 static int
4628 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4629 {
4630 struct bnx2 *bp = dev->priv;
4631
4632 if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4633 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4634 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4635
4636 return -EINVAL;
4637 }
4638 bp->rx_ring_size = ering->rx_pending;
4639 bp->tx_ring_size = ering->tx_pending;
4640
4641 if (netif_running(bp->dev)) {
4642 bnx2_netif_stop(bp);
4643 bnx2_init_nic(bp);
4644 bnx2_netif_start(bp);
4645 }
4646
4647 return 0;
4648 }
4649
4650 static void
4651 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4652 {
4653 struct bnx2 *bp = dev->priv;
4654
4655 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4656 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4657 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4658 }
4659
4660 static int
4661 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4662 {
4663 struct bnx2 *bp = dev->priv;
4664
4665 bp->req_flow_ctrl = 0;
4666 if (epause->rx_pause)
4667 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4668 if (epause->tx_pause)
4669 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4670
4671 if (epause->autoneg) {
4672 bp->autoneg |= AUTONEG_FLOW_CTRL;
4673 }
4674 else {
4675 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4676 }
4677
4678 spin_lock_bh(&bp->phy_lock);
4679
4680 bnx2_setup_phy(bp);
4681
4682 spin_unlock_bh(&bp->phy_lock);
4683
4684 return 0;
4685 }
4686
4687 static u32
4688 bnx2_get_rx_csum(struct net_device *dev)
4689 {
4690 struct bnx2 *bp = dev->priv;
4691
4692 return bp->rx_csum;
4693 }
4694
4695 static int
4696 bnx2_set_rx_csum(struct net_device *dev, u32 data)
4697 {
4698 struct bnx2 *bp = dev->priv;
4699
4700 bp->rx_csum = data;
4701 return 0;
4702 }
4703
4704 #define BNX2_NUM_STATS 45
4705
4706 static struct {
4707 char string[ETH_GSTRING_LEN];
4708 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4709 { "rx_bytes" },
4710 { "rx_error_bytes" },
4711 { "tx_bytes" },
4712 { "tx_error_bytes" },
4713 { "rx_ucast_packets" },
4714 { "rx_mcast_packets" },
4715 { "rx_bcast_packets" },
4716 { "tx_ucast_packets" },
4717 { "tx_mcast_packets" },
4718 { "tx_bcast_packets" },
4719 { "tx_mac_errors" },
4720 { "tx_carrier_errors" },
4721 { "rx_crc_errors" },
4722 { "rx_align_errors" },
4723 { "tx_single_collisions" },
4724 { "tx_multi_collisions" },
4725 { "tx_deferred" },
4726 { "tx_excess_collisions" },
4727 { "tx_late_collisions" },
4728 { "tx_total_collisions" },
4729 { "rx_fragments" },
4730 { "rx_jabbers" },
4731 { "rx_undersize_packets" },
4732 { "rx_oversize_packets" },
4733 { "rx_64_byte_packets" },
4734 { "rx_65_to_127_byte_packets" },
4735 { "rx_128_to_255_byte_packets" },
4736 { "rx_256_to_511_byte_packets" },
4737 { "rx_512_to_1023_byte_packets" },
4738 { "rx_1024_to_1522_byte_packets" },
4739 { "rx_1523_to_9022_byte_packets" },
4740 { "tx_64_byte_packets" },
4741 { "tx_65_to_127_byte_packets" },
4742 { "tx_128_to_255_byte_packets" },
4743 { "tx_256_to_511_byte_packets" },
4744 { "tx_512_to_1023_byte_packets" },
4745 { "tx_1024_to_1522_byte_packets" },
4746 { "tx_1523_to_9022_byte_packets" },
4747 { "rx_xon_frames" },
4748 { "rx_xoff_frames" },
4749 { "tx_xon_frames" },
4750 { "tx_xoff_frames" },
4751 { "rx_mac_ctrl_frames" },
4752 { "rx_filtered_packets" },
4753 { "rx_discards" },
4754 };
4755
4756 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
4757
4758 static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
4759 STATS_OFFSET32(stat_IfHCInOctets_hi),
4760 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
4761 STATS_OFFSET32(stat_IfHCOutOctets_hi),
4762 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
4763 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
4764 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
4765 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
4766 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
4767 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
4768 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
4769 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
4770 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
4771 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
4772 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
4773 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
4774 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
4775 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
4776 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
4777 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
4778 STATS_OFFSET32(stat_EtherStatsCollisions),
4779 STATS_OFFSET32(stat_EtherStatsFragments),
4780 STATS_OFFSET32(stat_EtherStatsJabbers),
4781 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
4782 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
4783 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
4784 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
4785 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
4786 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
4787 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
4788 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
4789 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
4790 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
4791 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
4792 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
4793 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
4794 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
4795 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
4796 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
4797 STATS_OFFSET32(stat_XonPauseFramesReceived),
4798 STATS_OFFSET32(stat_XoffPauseFramesReceived),
4799 STATS_OFFSET32(stat_OutXonSent),
4800 STATS_OFFSET32(stat_OutXoffSent),
4801 STATS_OFFSET32(stat_MacControlFramesReceived),
4802 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
4803 STATS_OFFSET32(stat_IfInMBUFDiscards),
4804 };
4805
4806 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
4807 * skipped because of errata.
4808 */
4809 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
4810 8,0,8,8,8,8,8,8,8,8,
4811 4,0,4,4,4,4,4,4,4,4,
4812 4,4,4,4,4,4,4,4,4,4,
4813 4,4,4,4,4,4,4,4,4,4,
4814 4,4,4,4,4,
4815 };
4816
4817 #define BNX2_NUM_TESTS 6
4818
4819 static struct {
4820 char string[ETH_GSTRING_LEN];
4821 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
4822 { "register_test (offline)" },
4823 { "memory_test (offline)" },
4824 { "loopback_test (offline)" },
4825 { "nvram_test (online)" },
4826 { "interrupt_test (online)" },
4827 { "link_test (online)" },
4828 };
4829
4830 static int
4831 bnx2_self_test_count(struct net_device *dev)
4832 {
4833 return BNX2_NUM_TESTS;
4834 }
4835
4836 static void
4837 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
4838 {
4839 struct bnx2 *bp = dev->priv;
4840
4841 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
4842 if (etest->flags & ETH_TEST_FL_OFFLINE) {
4843 bnx2_netif_stop(bp);
4844 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
4845 bnx2_free_skbs(bp);
4846
4847 if (bnx2_test_registers(bp) != 0) {
4848 buf[0] = 1;
4849 etest->flags |= ETH_TEST_FL_FAILED;
4850 }
4851 if (bnx2_test_memory(bp) != 0) {
4852 buf[1] = 1;
4853 etest->flags |= ETH_TEST_FL_FAILED;
4854 }
4855 if (bnx2_test_loopback(bp) != 0) {
4856 buf[2] = 1;
4857 etest->flags |= ETH_TEST_FL_FAILED;
4858 }
4859
4860 if (!netif_running(bp->dev)) {
4861 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
4862 }
4863 else {
4864 bnx2_init_nic(bp);
4865 bnx2_netif_start(bp);
4866 }
4867
4868 /* wait for link up */
4869 msleep_interruptible(3000);
4870 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
4871 msleep_interruptible(4000);
4872 }
4873
4874 if (bnx2_test_nvram(bp) != 0) {
4875 buf[3] = 1;
4876 etest->flags |= ETH_TEST_FL_FAILED;
4877 }
4878 if (bnx2_test_intr(bp) != 0) {
4879 buf[4] = 1;
4880 etest->flags |= ETH_TEST_FL_FAILED;
4881 }
4882
4883 if (bnx2_test_link(bp) != 0) {
4884 buf[5] = 1;
4885 etest->flags |= ETH_TEST_FL_FAILED;
4886
4887 }
4888 }
4889
4890 static void
4891 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
4892 {
4893 switch (stringset) {
4894 case ETH_SS_STATS:
4895 memcpy(buf, bnx2_stats_str_arr,
4896 sizeof(bnx2_stats_str_arr));
4897 break;
4898 case ETH_SS_TEST:
4899 memcpy(buf, bnx2_tests_str_arr,
4900 sizeof(bnx2_tests_str_arr));
4901 break;
4902 }
4903 }
4904
4905 static int
4906 bnx2_get_stats_count(struct net_device *dev)
4907 {
4908 return BNX2_NUM_STATS;
4909 }
4910
4911 static void
4912 bnx2_get_ethtool_stats(struct net_device *dev,
4913 struct ethtool_stats *stats, u64 *buf)
4914 {
4915 struct bnx2 *bp = dev->priv;
4916 int i;
4917 u32 *hw_stats = (u32 *) bp->stats_blk;
4918 u8 *stats_len_arr = NULL;
4919
4920 if (hw_stats == NULL) {
4921 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
4922 return;
4923 }
4924
4925 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4926 stats_len_arr = bnx2_5706_stats_len_arr;
4927
4928 for (i = 0; i < BNX2_NUM_STATS; i++) {
4929 if (stats_len_arr[i] == 0) {
4930 /* skip this counter */
4931 buf[i] = 0;
4932 continue;
4933 }
4934 if (stats_len_arr[i] == 4) {
4935 /* 4-byte counter */
4936 buf[i] = (u64)
4937 *(hw_stats + bnx2_stats_offset_arr[i]);
4938 continue;
4939 }
4940 /* 8-byte counter */
4941 buf[i] = (((u64) *(hw_stats +
4942 bnx2_stats_offset_arr[i])) << 32) +
4943 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
4944 }
4945 }
4946
4947 static int
4948 bnx2_phys_id(struct net_device *dev, u32 data)
4949 {
4950 struct bnx2 *bp = dev->priv;
4951 int i;
4952 u32 save;
4953
4954 if (data == 0)
4955 data = 2;
4956
4957 save = REG_RD(bp, BNX2_MISC_CFG);
4958 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
4959
4960 for (i = 0; i < (data * 2); i++) {
4961 if ((i % 2) == 0) {
4962 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
4963 }
4964 else {
4965 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
4966 BNX2_EMAC_LED_1000MB_OVERRIDE |
4967 BNX2_EMAC_LED_100MB_OVERRIDE |
4968 BNX2_EMAC_LED_10MB_OVERRIDE |
4969 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
4970 BNX2_EMAC_LED_TRAFFIC);
4971 }
4972 msleep_interruptible(500);
4973 if (signal_pending(current))
4974 break;
4975 }
4976 REG_WR(bp, BNX2_EMAC_LED, 0);
4977 REG_WR(bp, BNX2_MISC_CFG, save);
4978 return 0;
4979 }
4980
4981 static struct ethtool_ops bnx2_ethtool_ops = {
4982 .get_settings = bnx2_get_settings,
4983 .set_settings = bnx2_set_settings,
4984 .get_drvinfo = bnx2_get_drvinfo,
4985 .get_wol = bnx2_get_wol,
4986 .set_wol = bnx2_set_wol,
4987 .nway_reset = bnx2_nway_reset,
4988 .get_link = ethtool_op_get_link,
4989 .get_eeprom_len = bnx2_get_eeprom_len,
4990 .get_eeprom = bnx2_get_eeprom,
4991 .set_eeprom = bnx2_set_eeprom,
4992 .get_coalesce = bnx2_get_coalesce,
4993 .set_coalesce = bnx2_set_coalesce,
4994 .get_ringparam = bnx2_get_ringparam,
4995 .set_ringparam = bnx2_set_ringparam,
4996 .get_pauseparam = bnx2_get_pauseparam,
4997 .set_pauseparam = bnx2_set_pauseparam,
4998 .get_rx_csum = bnx2_get_rx_csum,
4999 .set_rx_csum = bnx2_set_rx_csum,
5000 .get_tx_csum = ethtool_op_get_tx_csum,
5001 .set_tx_csum = ethtool_op_set_tx_csum,
5002 .get_sg = ethtool_op_get_sg,
5003 .set_sg = ethtool_op_set_sg,
5004 #ifdef BCM_TSO
5005 .get_tso = ethtool_op_get_tso,
5006 .set_tso = ethtool_op_set_tso,
5007 #endif
5008 .self_test_count = bnx2_self_test_count,
5009 .self_test = bnx2_self_test,
5010 .get_strings = bnx2_get_strings,
5011 .phys_id = bnx2_phys_id,
5012 .get_stats_count = bnx2_get_stats_count,
5013 .get_ethtool_stats = bnx2_get_ethtool_stats,
5014 .get_perm_addr = ethtool_op_get_perm_addr,
5015 };
5016
5017 /* Called with rtnl_lock */
5018 static int
5019 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5020 {
5021 struct mii_ioctl_data *data = if_mii(ifr);
5022 struct bnx2 *bp = dev->priv;
5023 int err;
5024
5025 switch(cmd) {
5026 case SIOCGMIIPHY:
5027 data->phy_id = bp->phy_addr;
5028
5029 /* fallthru */
5030 case SIOCGMIIREG: {
5031 u32 mii_regval;
5032
5033 spin_lock_bh(&bp->phy_lock);
5034 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5035 spin_unlock_bh(&bp->phy_lock);
5036
5037 data->val_out = mii_regval;
5038
5039 return err;
5040 }
5041
5042 case SIOCSMIIREG:
5043 if (!capable(CAP_NET_ADMIN))
5044 return -EPERM;
5045
5046 spin_lock_bh(&bp->phy_lock);
5047 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5048 spin_unlock_bh(&bp->phy_lock);
5049
5050 return err;
5051
5052 default:
5053 /* do nothing */
5054 break;
5055 }
5056 return -EOPNOTSUPP;
5057 }
5058
5059 /* Called with rtnl_lock */
5060 static int
5061 bnx2_change_mac_addr(struct net_device *dev, void *p)
5062 {
5063 struct sockaddr *addr = p;
5064 struct bnx2 *bp = dev->priv;
5065
5066 if (!is_valid_ether_addr(addr->sa_data))
5067 return -EINVAL;
5068
5069 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5070 if (netif_running(dev))
5071 bnx2_set_mac_addr(bp);
5072
5073 return 0;
5074 }
5075
5076 /* Called with rtnl_lock */
5077 static int
5078 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5079 {
5080 struct bnx2 *bp = dev->priv;
5081
5082 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5083 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5084 return -EINVAL;
5085
5086 dev->mtu = new_mtu;
5087 if (netif_running(dev)) {
5088 bnx2_netif_stop(bp);
5089
5090 bnx2_init_nic(bp);
5091
5092 bnx2_netif_start(bp);
5093 }
5094 return 0;
5095 }
5096
5097 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5098 static void
5099 poll_bnx2(struct net_device *dev)
5100 {
5101 struct bnx2 *bp = dev->priv;
5102
5103 disable_irq(bp->pdev->irq);
5104 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5105 enable_irq(bp->pdev->irq);
5106 }
5107 #endif
5108
5109 static int __devinit
5110 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5111 {
5112 struct bnx2 *bp;
5113 unsigned long mem_len;
5114 int rc;
5115 u32 reg;
5116
5117 SET_MODULE_OWNER(dev);
5118 SET_NETDEV_DEV(dev, &pdev->dev);
5119 bp = dev->priv;
5120
5121 bp->flags = 0;
5122 bp->phy_flags = 0;
5123
5124 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5125 rc = pci_enable_device(pdev);
5126 if (rc) {
5127 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5128 goto err_out;
5129 }
5130
5131 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5132 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5133 "aborting.\n");
5134 rc = -ENODEV;
5135 goto err_out_disable;
5136 }
5137
5138 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5139 if (rc) {
5140 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5141 goto err_out_disable;
5142 }
5143
5144 pci_set_master(pdev);
5145
5146 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5147 if (bp->pm_cap == 0) {
5148 printk(KERN_ERR PFX "Cannot find power management capability, "
5149 "aborting.\n");
5150 rc = -EIO;
5151 goto err_out_release;
5152 }
5153
5154 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5155 if (bp->pcix_cap == 0) {
5156 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5157 rc = -EIO;
5158 goto err_out_release;
5159 }
5160
5161 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5162 bp->flags |= USING_DAC_FLAG;
5163 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5164 printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5165 "failed, aborting.\n");
5166 rc = -EIO;
5167 goto err_out_release;
5168 }
5169 }
5170 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5171 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5172 rc = -EIO;
5173 goto err_out_release;
5174 }
5175
5176 bp->dev = dev;
5177 bp->pdev = pdev;
5178
5179 spin_lock_init(&bp->phy_lock);
5180 spin_lock_init(&bp->tx_lock);
5181 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5182
5183 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5184 mem_len = MB_GET_CID_ADDR(17);
5185 dev->mem_end = dev->mem_start + mem_len;
5186 dev->irq = pdev->irq;
5187
5188 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5189
5190 if (!bp->regview) {
5191 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5192 rc = -ENOMEM;
5193 goto err_out_release;
5194 }
5195
5196 /* Configure byte swap and enable write to the reg_window registers.
5197 * Rely on CPU to do target byte swapping on big endian systems
5198 * The chip's target access swapping will not swap all accesses
5199 */
5200 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5201 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5202 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5203
5204 bnx2_set_power_state(bp, PCI_D0);
5205
5206 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5207
5208 bp->phy_addr = 1;
5209
5210 /* Get bus information. */
5211 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5212 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5213 u32 clkreg;
5214
5215 bp->flags |= PCIX_FLAG;
5216
5217 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5218
5219 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5220 switch (clkreg) {
5221 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5222 bp->bus_speed_mhz = 133;
5223 break;
5224
5225 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5226 bp->bus_speed_mhz = 100;
5227 break;
5228
5229 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5230 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5231 bp->bus_speed_mhz = 66;
5232 break;
5233
5234 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5235 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5236 bp->bus_speed_mhz = 50;
5237 break;
5238
5239 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5240 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5241 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5242 bp->bus_speed_mhz = 33;
5243 break;
5244 }
5245 }
5246 else {
5247 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5248 bp->bus_speed_mhz = 66;
5249 else
5250 bp->bus_speed_mhz = 33;
5251 }
5252
5253 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5254 bp->flags |= PCI_32BIT_FLAG;
5255
5256 /* 5706A0 may falsely detect SERR and PERR. */
5257 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5258 reg = REG_RD(bp, PCI_COMMAND);
5259 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5260 REG_WR(bp, PCI_COMMAND, reg);
5261 }
5262 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5263 !(bp->flags & PCIX_FLAG)) {
5264
5265 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5266 "aborting.\n");
5267 goto err_out_unmap;
5268 }
5269
5270 bnx2_init_nvram(bp);
5271
5272 /* Get the permanent MAC address. First we need to make sure the
5273 * firmware is actually running.
5274 */
5275 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
5276
5277 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5278 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5279 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5280 rc = -ENODEV;
5281 goto err_out_unmap;
5282 }
5283
5284 bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5285 BNX2_DEV_INFO_BC_REV);
5286
5287 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
5288 bp->mac_addr[0] = (u8) (reg >> 8);
5289 bp->mac_addr[1] = (u8) reg;
5290
5291 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
5292 bp->mac_addr[2] = (u8) (reg >> 24);
5293 bp->mac_addr[3] = (u8) (reg >> 16);
5294 bp->mac_addr[4] = (u8) (reg >> 8);
5295 bp->mac_addr[5] = (u8) reg;
5296
5297 bp->tx_ring_size = MAX_TX_DESC_CNT;
5298 bp->rx_ring_size = 100;
5299
5300 bp->rx_csum = 1;
5301
5302 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5303
5304 bp->tx_quick_cons_trip_int = 20;
5305 bp->tx_quick_cons_trip = 20;
5306 bp->tx_ticks_int = 80;
5307 bp->tx_ticks = 80;
5308
5309 bp->rx_quick_cons_trip_int = 6;
5310 bp->rx_quick_cons_trip = 6;
5311 bp->rx_ticks_int = 18;
5312 bp->rx_ticks = 18;
5313
5314 bp->stats_ticks = 1000000 & 0xffff00;
5315
5316 bp->timer_interval = HZ;
5317 bp->current_interval = HZ;
5318
5319 /* Disable WOL support if we are running on a SERDES chip. */
5320 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5321 bp->phy_flags |= PHY_SERDES_FLAG;
5322 bp->flags |= NO_WOL_FLAG;
5323 }
5324
5325 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5326 bp->tx_quick_cons_trip_int =
5327 bp->tx_quick_cons_trip;
5328 bp->tx_ticks_int = bp->tx_ticks;
5329 bp->rx_quick_cons_trip_int =
5330 bp->rx_quick_cons_trip;
5331 bp->rx_ticks_int = bp->rx_ticks;
5332 bp->comp_prod_trip_int = bp->comp_prod_trip;
5333 bp->com_ticks_int = bp->com_ticks;
5334 bp->cmd_ticks_int = bp->cmd_ticks;
5335 }
5336
5337 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5338 bp->req_line_speed = 0;
5339 if (bp->phy_flags & PHY_SERDES_FLAG) {
5340 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5341
5342 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5343 BNX2_PORT_HW_CFG_CONFIG);
5344 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5345 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5346 bp->autoneg = 0;
5347 bp->req_line_speed = bp->line_speed = SPEED_1000;
5348 bp->req_duplex = DUPLEX_FULL;
5349 }
5350 }
5351 else {
5352 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5353 }
5354
5355 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5356
5357 init_timer(&bp->timer);
5358 bp->timer.expires = RUN_AT(bp->timer_interval);
5359 bp->timer.data = (unsigned long) bp;
5360 bp->timer.function = bnx2_timer;
5361
5362 return 0;
5363
5364 err_out_unmap:
5365 if (bp->regview) {
5366 iounmap(bp->regview);
5367 bp->regview = NULL;
5368 }
5369
5370 err_out_release:
5371 pci_release_regions(pdev);
5372
5373 err_out_disable:
5374 pci_disable_device(pdev);
5375 pci_set_drvdata(pdev, NULL);
5376
5377 err_out:
5378 return rc;
5379 }
5380
5381 static int __devinit
5382 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5383 {
5384 static int version_printed = 0;
5385 struct net_device *dev = NULL;
5386 struct bnx2 *bp;
5387 int rc, i;
5388
5389 if (version_printed++ == 0)
5390 printk(KERN_INFO "%s", version);
5391
5392 /* dev zeroed in init_etherdev */
5393 dev = alloc_etherdev(sizeof(*bp));
5394
5395 if (!dev)
5396 return -ENOMEM;
5397
5398 rc = bnx2_init_board(pdev, dev);
5399 if (rc < 0) {
5400 free_netdev(dev);
5401 return rc;
5402 }
5403
5404 dev->open = bnx2_open;
5405 dev->hard_start_xmit = bnx2_start_xmit;
5406 dev->stop = bnx2_close;
5407 dev->get_stats = bnx2_get_stats;
5408 dev->set_multicast_list = bnx2_set_rx_mode;
5409 dev->do_ioctl = bnx2_ioctl;
5410 dev->set_mac_address = bnx2_change_mac_addr;
5411 dev->change_mtu = bnx2_change_mtu;
5412 dev->tx_timeout = bnx2_tx_timeout;
5413 dev->watchdog_timeo = TX_TIMEOUT;
5414 #ifdef BCM_VLAN
5415 dev->vlan_rx_register = bnx2_vlan_rx_register;
5416 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5417 #endif
5418 dev->poll = bnx2_poll;
5419 dev->ethtool_ops = &bnx2_ethtool_ops;
5420 dev->weight = 64;
5421
5422 bp = dev->priv;
5423
5424 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5425 dev->poll_controller = poll_bnx2;
5426 #endif
5427
5428 if ((rc = register_netdev(dev))) {
5429 printk(KERN_ERR PFX "Cannot register net device\n");
5430 if (bp->regview)
5431 iounmap(bp->regview);
5432 pci_release_regions(pdev);
5433 pci_disable_device(pdev);
5434 pci_set_drvdata(pdev, NULL);
5435 free_netdev(dev);
5436 return rc;
5437 }
5438
5439 pci_set_drvdata(pdev, dev);
5440
5441 memcpy(dev->dev_addr, bp->mac_addr, 6);
5442 memcpy(dev->perm_addr, bp->mac_addr, 6);
5443 bp->name = board_info[ent->driver_data].name,
5444 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5445 "IRQ %d, ",
5446 dev->name,
5447 bp->name,
5448 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5449 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5450 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5451 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5452 bp->bus_speed_mhz,
5453 dev->base_addr,
5454 bp->pdev->irq);
5455
5456 printk("node addr ");
5457 for (i = 0; i < 6; i++)
5458 printk("%2.2x", dev->dev_addr[i]);
5459 printk("\n");
5460
5461 dev->features |= NETIF_F_SG;
5462 if (bp->flags & USING_DAC_FLAG)
5463 dev->features |= NETIF_F_HIGHDMA;
5464 dev->features |= NETIF_F_IP_CSUM;
5465 #ifdef BCM_VLAN
5466 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5467 #endif
5468 #ifdef BCM_TSO
5469 dev->features |= NETIF_F_TSO;
5470 #endif
5471
5472 netif_carrier_off(bp->dev);
5473
5474 return 0;
5475 }
5476
5477 static void __devexit
5478 bnx2_remove_one(struct pci_dev *pdev)
5479 {
5480 struct net_device *dev = pci_get_drvdata(pdev);
5481 struct bnx2 *bp = dev->priv;
5482
5483 flush_scheduled_work();
5484
5485 unregister_netdev(dev);
5486
5487 if (bp->regview)
5488 iounmap(bp->regview);
5489
5490 free_netdev(dev);
5491 pci_release_regions(pdev);
5492 pci_disable_device(pdev);
5493 pci_set_drvdata(pdev, NULL);
5494 }
5495
5496 static int
5497 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5498 {
5499 struct net_device *dev = pci_get_drvdata(pdev);
5500 struct bnx2 *bp = dev->priv;
5501 u32 reset_code;
5502
5503 if (!netif_running(dev))
5504 return 0;
5505
5506 bnx2_netif_stop(bp);
5507 netif_device_detach(dev);
5508 del_timer_sync(&bp->timer);
5509 if (bp->wol)
5510 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5511 else
5512 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5513 bnx2_reset_chip(bp, reset_code);
5514 bnx2_free_skbs(bp);
5515 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
5516 return 0;
5517 }
5518
5519 static int
5520 bnx2_resume(struct pci_dev *pdev)
5521 {
5522 struct net_device *dev = pci_get_drvdata(pdev);
5523 struct bnx2 *bp = dev->priv;
5524
5525 if (!netif_running(dev))
5526 return 0;
5527
5528 bnx2_set_power_state(bp, PCI_D0);
5529 netif_device_attach(dev);
5530 bnx2_init_nic(bp);
5531 bnx2_netif_start(bp);
5532 return 0;
5533 }
5534
5535 static struct pci_driver bnx2_pci_driver = {
5536 .name = DRV_MODULE_NAME,
5537 .id_table = bnx2_pci_tbl,
5538 .probe = bnx2_init_one,
5539 .remove = __devexit_p(bnx2_remove_one),
5540 .suspend = bnx2_suspend,
5541 .resume = bnx2_resume,
5542 };
5543
5544 static int __init bnx2_init(void)
5545 {
5546 return pci_module_init(&bnx2_pci_driver);
5547 }
5548
5549 static void __exit bnx2_cleanup(void)
5550 {
5551 pci_unregister_driver(&bnx2_pci_driver);
5552 }
5553
5554 module_init(bnx2_init);
5555 module_exit(bnx2_cleanup);
5556
5557
5558
WandBoard kernel