2 * Atheros AR9170 driver
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, see
20 * http://www.gnu.org/licenses/.
22 * This file incorporates work covered by the following copyright and
24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
26 * Permission to use, copy, modify, and/or distribute this software for any
27 * purpose with or without fee is hereby granted, provided that the above
28 * copyright notice and this permission notice appear in all copies.
30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
41 int ar9170_set_qos(struct ar9170
*ar
)
43 ar9170_regwrite_begin(ar
);
45 ar9170_regwrite(AR9170_MAC_REG_AC0_CW
, ar
->edcf
[0].cw_min
|
46 (ar
->edcf
[0].cw_max
<< 16));
47 ar9170_regwrite(AR9170_MAC_REG_AC1_CW
, ar
->edcf
[1].cw_min
|
48 (ar
->edcf
[1].cw_max
<< 16));
49 ar9170_regwrite(AR9170_MAC_REG_AC2_CW
, ar
->edcf
[2].cw_min
|
50 (ar
->edcf
[2].cw_max
<< 16));
51 ar9170_regwrite(AR9170_MAC_REG_AC3_CW
, ar
->edcf
[3].cw_min
|
52 (ar
->edcf
[3].cw_max
<< 16));
53 ar9170_regwrite(AR9170_MAC_REG_AC4_CW
, ar
->edcf
[4].cw_min
|
54 (ar
->edcf
[4].cw_max
<< 16));
56 ar9170_regwrite(AR9170_MAC_REG_AC1_AC0_AIFS
,
57 ((ar
->edcf
[0].aifs
* 9 + 10)) |
58 ((ar
->edcf
[1].aifs
* 9 + 10) << 12) |
59 ((ar
->edcf
[2].aifs
* 9 + 10) << 24));
60 ar9170_regwrite(AR9170_MAC_REG_AC3_AC2_AIFS
,
61 ((ar
->edcf
[2].aifs
* 9 + 10) >> 8) |
62 ((ar
->edcf
[3].aifs
* 9 + 10) << 4) |
63 ((ar
->edcf
[4].aifs
* 9 + 10) << 16));
65 ar9170_regwrite(AR9170_MAC_REG_AC1_AC0_TXOP
,
66 ar
->edcf
[0].txop
| ar
->edcf
[1].txop
<< 16);
67 ar9170_regwrite(AR9170_MAC_REG_AC3_AC2_TXOP
,
68 ar
->edcf
[1].txop
| ar
->edcf
[3].txop
<< 16);
70 ar9170_regwrite_finish();
72 return ar9170_regwrite_result();
75 int ar9170_init_mac(struct ar9170
*ar
)
77 ar9170_regwrite_begin(ar
);
79 ar9170_regwrite(AR9170_MAC_REG_ACK_EXTENSION
, 0x40);
81 ar9170_regwrite(AR9170_MAC_REG_RETRY_MAX
, 0);
84 ar9170_regwrite(AR9170_MAC_REG_SNIFFER
,
85 AR9170_MAC_REG_SNIFFER_DEFAULTS
);
87 ar9170_regwrite(AR9170_MAC_REG_RX_THRESHOLD
, 0xc1f80);
89 ar9170_regwrite(AR9170_MAC_REG_RX_PE_DELAY
, 0x70);
90 ar9170_regwrite(AR9170_MAC_REG_EIFS_AND_SIFS
, 0xa144000);
91 ar9170_regwrite(AR9170_MAC_REG_SLOT_TIME
, 9 << 10);
94 ar9170_regwrite(0x1c3b2c, 0x19000000);
96 /* NAV protects ACK only (in TXOP) */
97 ar9170_regwrite(0x1c3b38, 0x201);
99 /* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */
100 /* OTUS set AM to 0x1 */
101 ar9170_regwrite(AR9170_MAC_REG_BCN_HT1
, 0x8000170);
103 ar9170_regwrite(AR9170_MAC_REG_BACKOFF_PROTECT
, 0x105);
106 /* Aggregation MAX number and timeout */
107 ar9170_regwrite(0x1c3b9c, 0x10000a);
109 ar9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER
,
110 AR9170_MAC_REG_FTF_DEFAULTS
);
112 /* Enable deaggregator, response in sniffer mode */
113 ar9170_regwrite(0x1c3c40, 0x1 | 1<<30);
116 ar9170_regwrite(AR9170_MAC_REG_BASIC_RATE
, 0x150f);
117 ar9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE
, 0x150f);
118 ar9170_regwrite(AR9170_MAC_REG_RTS_CTS_RATE
, 0x10b01bb);
120 /* MIMO response control */
121 ar9170_regwrite(0x1c3694, 0x4003C1E);/* bit 26~28 otus-AM */
123 /* switch MAC to OTUS interface */
124 ar9170_regwrite(0x1c3600, 0x3);
126 ar9170_regwrite(AR9170_MAC_REG_AMPDU_RX_THRESH
, 0xffff);
128 /* set PHY register read timeout (??) */
129 ar9170_regwrite(AR9170_MAC_REG_MISC_680
, 0xf00008);
131 /* Disable Rx TimeOut, workaround for BB. */
132 ar9170_regwrite(AR9170_MAC_REG_RX_TIMEOUT
, 0x0);
134 /* Set CPU clock frequency to 88/80MHz */
135 ar9170_regwrite(AR9170_PWR_REG_CLOCK_SEL
,
136 AR9170_PWR_CLK_AHB_80_88MHZ
|
137 AR9170_PWR_CLK_DAC_160_INV_DLY
);
139 /* Set WLAN DMA interrupt mode: generate int per packet */
140 ar9170_regwrite(AR9170_MAC_REG_TXRX_MPI
, 0x110011);
142 ar9170_regwrite(AR9170_MAC_REG_FCS_SELECT
,
143 AR9170_MAC_FCS_FIFO_PROT
);
145 /* Disables the CF_END frame, undocumented register */
146 ar9170_regwrite(AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND
,
149 ar9170_regwrite_finish();
151 return ar9170_regwrite_result();
154 static int ar9170_set_mac_reg(struct ar9170
*ar
, const u32 reg
, const u8
*mac
)
156 static const u8 zero
[ETH_ALEN
] = { 0 };
161 ar9170_regwrite_begin(ar
);
164 (mac
[3] << 24) | (mac
[2] << 16) |
165 (mac
[1] << 8) | mac
[0]);
167 ar9170_regwrite(reg
+ 4, (mac
[5] << 8) | mac
[4]);
169 ar9170_regwrite_finish();
171 return ar9170_regwrite_result();
174 int ar9170_update_multicast(struct ar9170
*ar
)
178 ar9170_regwrite_begin(ar
);
179 ar9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H
,
180 ar
->want_mc_hash
>> 32);
181 ar9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L
,
184 ar9170_regwrite_finish();
185 err
= ar9170_regwrite_result();
190 ar
->cur_mc_hash
= ar
->want_mc_hash
;
195 int ar9170_update_frame_filter(struct ar9170
*ar
)
199 err
= ar9170_write_reg(ar
, AR9170_MAC_REG_FRAMETYPE_FILTER
,
205 ar
->cur_filter
= ar
->want_filter
;
210 static int ar9170_set_promiscouous(struct ar9170
*ar
)
212 u32 encr_mode
, sniffer
;
215 err
= ar9170_read_reg(ar
, AR9170_MAC_REG_SNIFFER
, &sniffer
);
219 err
= ar9170_read_reg(ar
, AR9170_MAC_REG_ENCRYPTION
, &encr_mode
);
223 if (ar
->sniffer_enabled
) {
224 sniffer
|= AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC
;
227 * Rx decryption works in place.
229 * If we don't disable it, the hardware will render all
230 * encrypted frames which are encrypted with an unknown
234 encr_mode
|= AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE
;
235 ar
->sniffer_enabled
= true;
237 sniffer
&= ~AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC
;
239 if (ar
->rx_software_decryption
)
240 encr_mode
|= AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE
;
242 encr_mode
&= ~AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE
;
245 ar9170_regwrite_begin(ar
);
246 ar9170_regwrite(AR9170_MAC_REG_ENCRYPTION
, encr_mode
);
247 ar9170_regwrite(AR9170_MAC_REG_SNIFFER
, sniffer
);
248 ar9170_regwrite_finish();
250 return ar9170_regwrite_result();
253 int ar9170_set_operating_mode(struct ar9170
*ar
)
255 u32 pm_mode
= AR9170_MAC_REG_POWERMGT_DEFAULTS
;
256 u8
*mac_addr
, *bssid
;
260 mac_addr
= ar
->mac_addr
;
263 switch (ar
->vif
->type
) {
264 case NL80211_IFTYPE_MESH_POINT
:
265 case NL80211_IFTYPE_ADHOC
:
266 pm_mode
|= AR9170_MAC_REG_POWERMGT_IBSS
;
268 /* case NL80211_IFTYPE_AP:
269 pm_mode |= AR9170_MAC_REG_POWERMGT_AP;
271 case NL80211_IFTYPE_WDS
:
272 pm_mode
|= AR9170_MAC_REG_POWERMGT_AP_WDS
;
274 case NL80211_IFTYPE_MONITOR
:
275 ar
->sniffer_enabled
= true;
276 ar
->rx_software_decryption
= true;
279 pm_mode
|= AR9170_MAC_REG_POWERMGT_STA
;
287 err
= ar9170_set_mac_reg(ar
, AR9170_MAC_REG_MAC_ADDR_L
, mac_addr
);
291 err
= ar9170_set_mac_reg(ar
, AR9170_MAC_REG_BSSID_L
, bssid
);
295 err
= ar9170_set_promiscouous(ar
);
299 ar9170_regwrite_begin(ar
);
301 ar9170_regwrite(AR9170_MAC_REG_POWERMANAGEMENT
, pm_mode
);
302 ar9170_regwrite_finish();
304 return ar9170_regwrite_result();
307 int ar9170_set_hwretry_limit(struct ar9170
*ar
, unsigned int max_retry
)
309 u32 tmp
= min_t(u32
, 0x33333, max_retry
* 0x11111);
311 return ar9170_write_reg(ar
, AR9170_MAC_REG_RETRY_MAX
, tmp
);
314 int ar9170_set_beacon_timers(struct ar9170
*ar
)
319 v
|= ar
->hw
->conf
.beacon_int
;
322 switch (ar
->vif
->type
) {
323 case NL80211_IFTYPE_MESH_POINT
:
324 case NL80211_IFTYPE_ADHOC
:
327 case NL80211_IFTYPE_AP
:
329 pretbtt
= (ar
->hw
->conf
.beacon_int
- 6) << 16;
335 v
|= ar
->vif
->bss_conf
.dtim_period
<< 16;
338 ar9170_regwrite_begin(ar
);
340 ar9170_regwrite(AR9170_MAC_REG_PRETBTT
, pretbtt
);
341 ar9170_regwrite(AR9170_MAC_REG_BCN_PERIOD
, v
);
342 ar9170_regwrite_finish();
343 return ar9170_regwrite_result();
346 int ar9170_update_beacon(struct ar9170
*ar
)
349 __le32
*data
, *old
= NULL
;
353 skb
= ieee80211_beacon_get(ar
->hw
, ar
->vif
);
357 data
= (__le32
*)skb
->data
;
359 old
= (__le32
*)ar
->beacon
->data
;
361 ar9170_regwrite_begin(ar
);
362 for (i
= 0; i
< DIV_ROUND_UP(skb
->len
, 4); i
++) {
364 * XXX: This accesses beyond skb data for up
365 * to the last 3 bytes!!
368 if (old
&& (data
[i
] == old
[i
]))
371 word
= le32_to_cpu(data
[i
]);
372 ar9170_regwrite(AR9170_BEACON_BUFFER_ADDRESS
+ 4 * i
, word
);
375 /* XXX: use skb->cb info */
376 if (ar
->hw
->conf
.channel
->band
== IEEE80211_BAND_2GHZ
)
377 ar9170_regwrite(AR9170_MAC_REG_BCN_PLCP
,
378 ((skb
->len
+ 4) << (3+16)) + 0x0400);
380 ar9170_regwrite(AR9170_MAC_REG_BCN_PLCP
,
381 ((skb
->len
+ 4) << (3+16)) + 0x0400);
383 ar9170_regwrite(AR9170_MAC_REG_BCN_LENGTH
, skb
->len
+ 4);
384 ar9170_regwrite(AR9170_MAC_REG_BCN_ADDR
, AR9170_BEACON_BUFFER_ADDRESS
);
385 ar9170_regwrite(AR9170_MAC_REG_BCN_CTRL
, 1);
387 ar9170_regwrite_finish();
389 dev_kfree_skb(ar
->beacon
);
392 return ar9170_regwrite_result();
395 void ar9170_new_beacon(struct work_struct
*work
)
397 struct ar9170
*ar
= container_of(work
, struct ar9170
,
401 if (unlikely(!IS_STARTED(ar
)))
404 mutex_lock(&ar
->mutex
);
409 ar9170_update_beacon(ar
);
412 while ((skb
= ieee80211_get_buffered_bc(ar
->hw
, ar
->vif
)))
413 ar9170_op_tx(ar
->hw
, skb
);
418 mutex_unlock(&ar
->mutex
);
421 int ar9170_upload_key(struct ar9170
*ar
, u8 id
, const u8
*mac
, u8 ktype
,
422 u8 keyidx
, u8
*keydata
, int keylen
)
425 static const u8 bcast
[ETH_ALEN
] =
426 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
431 vals
[0] = cpu_to_le32((keyidx
<< 16) + id
);
432 vals
[1] = cpu_to_le32(mac
[1] << 24 | mac
[0] << 16 | ktype
);
433 vals
[2] = cpu_to_le32(mac
[5] << 24 | mac
[4] << 16 |
434 mac
[3] << 8 | mac
[2]);
435 memset(&vals
[3], 0, 16);
437 memcpy(&vals
[3], keydata
, keylen
);
439 return ar
->exec_cmd(ar
, AR9170_CMD_EKEY
,
440 sizeof(vals
), (u8
*)vals
,
444 int ar9170_disable_key(struct ar9170
*ar
, u8 id
)
446 __le32 val
= cpu_to_le32(id
);
449 return ar
->exec_cmd(ar
, AR9170_CMD_EKEY
,
450 sizeof(val
), (u8
*)&val
,