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tracehook: vfork-done
[wandboard.git] / drivers / char / agp / amd64-agp.c
blob481ffe87c716472548d99c7d79bde85872bb0c0e
1 /*
2 * Copyright 2001-2003 SuSE Labs.
3 * Distributed under the GNU public license, v2.
4 *
5 * This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
6 * It also includes support for the AMD 8151 AGP bridge,
7 * although it doesn't actually do much, as all the real
8 * work is done in the northbridge(s).
9 */
10
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/init.h>
14 #include <linux/agp_backend.h>
15 #include <linux/mmzone.h>
16 #include <asm/page.h> /* PAGE_SIZE */
17 #include <asm/e820.h>
18 #include <asm/k8.h>
19 #include <asm/gart.h>
20 #include "agp.h"
21
22 /* NVIDIA K8 registers */
23 #define NVIDIA_X86_64_0_APBASE 0x10
24 #define NVIDIA_X86_64_1_APBASE1 0x50
25 #define NVIDIA_X86_64_1_APLIMIT1 0x54
26 #define NVIDIA_X86_64_1_APSIZE 0xa8
27 #define NVIDIA_X86_64_1_APBASE2 0xd8
28 #define NVIDIA_X86_64_1_APLIMIT2 0xdc
29
30 /* ULi K8 registers */
31 #define ULI_X86_64_BASE_ADDR 0x10
32 #define ULI_X86_64_HTT_FEA_REG 0x50
33 #define ULI_X86_64_ENU_SCR_REG 0x54
34
35 static struct resource *aperture_resource;
36 static int __initdata agp_try_unsupported = 1;
37
38 static void amd64_tlbflush(struct agp_memory *temp)
39 {
40 k8_flush_garts();
41 }
42
43 static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
44 {
45 int i, j, num_entries;
46 long long tmp;
47 int mask_type;
48 struct agp_bridge_data *bridge = mem->bridge;
49 u32 pte;
50
51 num_entries = agp_num_entries();
52
53 if (type != mem->type)
54 return -EINVAL;
55 mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
56 if (mask_type != 0)
57 return -EINVAL;
58
59
60 /* Make sure we can fit the range in the gatt table. */
61 /* FIXME: could wrap */
62 if (((unsigned long)pg_start + mem->page_count) > num_entries)
63 return -EINVAL;
64
65 j = pg_start;
66
67 /* gatt table should be empty. */
68 while (j < (pg_start + mem->page_count)) {
69 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
70 return -EBUSY;
71 j++;
72 }
73
74 if (!mem->is_flushed) {
75 global_cache_flush();
76 mem->is_flushed = true;
77 }
78
79 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
80 tmp = agp_bridge->driver->mask_memory(agp_bridge,
81 mem->memory[i], mask_type);
82
83 BUG_ON(tmp & 0xffffff0000000ffcULL);
84 pte = (tmp & 0x000000ff00000000ULL) >> 28;
85 pte |=(tmp & 0x00000000fffff000ULL);
86 pte |= GPTE_VALID | GPTE_COHERENT;
87
88 writel(pte, agp_bridge->gatt_table+j);
89 readl(agp_bridge->gatt_table+j); /* PCI Posting. */
90 }
91 amd64_tlbflush(mem);
92 return 0;
93 }
94
95 /*
96 * This hack alters the order element according
97 * to the size of a long. It sucks. I totally disown this, even
98 * though it does appear to work for the most part.
99 */
100 static struct aper_size_info_32 amd64_aperture_sizes[7] =
101 {
102 {32, 8192, 3+(sizeof(long)/8), 0 },
103 {64, 16384, 4+(sizeof(long)/8), 1<<1 },
104 {128, 32768, 5+(sizeof(long)/8), 1<<2 },
105 {256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
106 {512, 131072, 7+(sizeof(long)/8), 1<<3 },
107 {1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
108 {2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
109 };
110
111
112 /*
113 * Get the current Aperture size from the x86-64.
114 * Note, that there may be multiple x86-64's, but we just return
115 * the value from the first one we find. The set_size functions
116 * keep the rest coherent anyway. Or at least should do.
117 */
118 static int amd64_fetch_size(void)
119 {
120 struct pci_dev *dev;
121 int i;
122 u32 temp;
123 struct aper_size_info_32 *values;
124
125 dev = k8_northbridges[0];
126 if (dev==NULL)
127 return 0;
128
129 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
130 temp = (temp & 0xe);
131 values = A_SIZE_32(amd64_aperture_sizes);
132
133 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
134 if (temp == values[i].size_value) {
135 agp_bridge->previous_size =
136 agp_bridge->current_size = (void *) (values + i);
137
138 agp_bridge->aperture_size_idx = i;
139 return values[i].size;
140 }
141 }
142 return 0;
143 }
144
145 /*
146 * In a multiprocessor x86-64 system, this function gets
147 * called once for each CPU.
148 */
149 static u64 amd64_configure(struct pci_dev *hammer, u64 gatt_table)
150 {
151 u64 aperturebase;
152 u32 tmp;
153 u64 aper_base;
154
155 /* Address to map to */
156 pci_read_config_dword(hammer, AMD64_GARTAPERTUREBASE, &tmp);
157 aperturebase = tmp << 25;
158 aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
159
160 enable_gart_translation(hammer, gatt_table);
161
162 return aper_base;
163 }
164
165
166 static const struct aper_size_info_32 amd_8151_sizes[7] =
167 {
168 {2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
169 {1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
170 {512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
171 {256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
172 {128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
173 {64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
174 {32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
175 };
176
177 static int amd_8151_configure(void)
178 {
179 unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real);
180 int i;
181
182 /* Configure AGP regs in each x86-64 host bridge. */
183 for (i = 0; i < num_k8_northbridges; i++) {
184 agp_bridge->gart_bus_addr =
185 amd64_configure(k8_northbridges[i], gatt_bus);
186 }
187 k8_flush_garts();
188 return 0;
189 }
190
191
192 static void amd64_cleanup(void)
193 {
194 u32 tmp;
195 int i;
196 for (i = 0; i < num_k8_northbridges; i++) {
197 struct pci_dev *dev = k8_northbridges[i];
198 /* disable gart translation */
199 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &tmp);
200 tmp &= ~AMD64_GARTEN;
201 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, tmp);
202 }
203 }
204
205
206 static const struct agp_bridge_driver amd_8151_driver = {
207 .owner = THIS_MODULE,
208 .aperture_sizes = amd_8151_sizes,
209 .size_type = U32_APER_SIZE,
210 .num_aperture_sizes = 7,
211 .configure = amd_8151_configure,
212 .fetch_size = amd64_fetch_size,
213 .cleanup = amd64_cleanup,
214 .tlb_flush = amd64_tlbflush,
215 .mask_memory = agp_generic_mask_memory,
216 .masks = NULL,
217 .agp_enable = agp_generic_enable,
218 .cache_flush = global_cache_flush,
219 .create_gatt_table = agp_generic_create_gatt_table,
220 .free_gatt_table = agp_generic_free_gatt_table,
221 .insert_memory = amd64_insert_memory,
222 .remove_memory = agp_generic_remove_memory,
223 .alloc_by_type = agp_generic_alloc_by_type,
224 .free_by_type = agp_generic_free_by_type,
225 .agp_alloc_page = agp_generic_alloc_page,
226 .agp_destroy_page = agp_generic_destroy_page,
227 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
228 };
229
230 /* Some basic sanity checks for the aperture. */
231 static int __devinit agp_aperture_valid(u64 aper, u32 size)
232 {
233 if (!aperture_valid(aper, size, 32*1024*1024))
234 return 0;
235
236 /* Request the Aperture. This catches cases when someone else
237 already put a mapping in there - happens with some very broken BIOS
238
239 Maybe better to use pci_assign_resource/pci_enable_device instead
240 trusting the bridges? */
241 if (!aperture_resource &&
242 !(aperture_resource = request_mem_region(aper, size, "aperture"))) {
243 printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
244 return 0;
245 }
246 return 1;
247 }
248
249 /*
250 * W*s centric BIOS sometimes only set up the aperture in the AGP
251 * bridge, not the northbridge. On AMD64 this is handled early
252 * in aperture.c, but when IOMMU is not enabled or we run
253 * on a 32bit kernel this needs to be redone.
254 * Unfortunately it is impossible to fix the aperture here because it's too late
255 * to allocate that much memory. But at least error out cleanly instead of
256 * crashing.
257 */
258 static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
259 u16 cap)
260 {
261 u32 aper_low, aper_hi;
262 u64 aper, nb_aper;
263 int order = 0;
264 u32 nb_order, nb_base;
265 u16 apsize;
266
267 pci_read_config_dword(nb, AMD64_GARTAPERTURECTL, &nb_order);
268 nb_order = (nb_order >> 1) & 7;
269 pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base);
270 nb_aper = nb_base << 25;
271 if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
272 return 0;
273 }
274
275 /* Northbridge seems to contain crap. Try the AGP bridge. */
276
277 pci_read_config_word(agp, cap+0x14, &apsize);
278 if (apsize == 0xffff)
279 return -1;
280
281 apsize &= 0xfff;
282 /* Some BIOS use weird encodings not in the AGPv3 table. */
283 if (apsize & 0xff)
284 apsize |= 0xf00;
285 order = 7 - hweight16(apsize);
286
287 pci_read_config_dword(agp, 0x10, &aper_low);
288 pci_read_config_dword(agp, 0x14, &aper_hi);
289 aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
290
291 /*
292 * On some sick chips APSIZE is 0. This means it wants 4G
293 * so let double check that order, and lets trust the AMD NB settings
294 */
295 if (order >=0 && aper + (32ULL<<(20 + order)) > 0x100000000ULL) {
296 printk(KERN_INFO "Aperture size %u MB is not right, using settings from NB\n",
297 32 << order);
298 order = nb_order;
299 }
300
301 printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order);
302 if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order))
303 return -1;
304
305 pci_write_config_dword(nb, AMD64_GARTAPERTURECTL, order << 1);
306 pci_write_config_dword(nb, AMD64_GARTAPERTUREBASE, aper >> 25);
307
308 return 0;
309 }
310
311 static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
312 {
313 int i;
314
315 if (cache_k8_northbridges() < 0)
316 return -ENODEV;
317
318 i = 0;
319 for (i = 0; i < num_k8_northbridges; i++) {
320 struct pci_dev *dev = k8_northbridges[i];
321 if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
322 printk(KERN_ERR PFX "No usable aperture found.\n");
323 #ifdef __x86_64__
324 /* should port this to i386 */
325 printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n");
326 #endif
327 return -1;
328 }
329 }
330 return 0;
331 }
332
333 /* Handle AMD 8151 quirks */
334 static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
335 {
336 char *revstring;
337
338 switch (pdev->revision) {
339 case 0x01: revstring="A0"; break;
340 case 0x02: revstring="A1"; break;
341 case 0x11: revstring="B0"; break;
342 case 0x12: revstring="B1"; break;
343 case 0x13: revstring="B2"; break;
344 case 0x14: revstring="B3"; break;
345 default: revstring="??"; break;
346 }
347
348 printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring);
349
350 /*
351 * Work around errata.
352 * Chips before B2 stepping incorrectly reporting v3.5
353 */
354 if (pdev->revision < 0x13) {
355 printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n");
356 bridge->major_version = 3;
357 bridge->minor_version = 0;
358 }
359 }
360
361
362 static const struct aper_size_info_32 uli_sizes[7] =
363 {
364 {256, 65536, 6, 10},
365 {128, 32768, 5, 9},
366 {64, 16384, 4, 8},
367 {32, 8192, 3, 7},
368 {16, 4096, 2, 6},
369 {8, 2048, 1, 4},
370 {4, 1024, 0, 3}
371 };
372 static int __devinit uli_agp_init(struct pci_dev *pdev)
373 {
374 u32 httfea,baseaddr,enuscr;
375 struct pci_dev *dev1;
376 int i;
377 unsigned size = amd64_fetch_size();
378 printk(KERN_INFO "Setting up ULi AGP.\n");
379 dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
380 if (dev1 == NULL) {
381 printk(KERN_INFO PFX "Detected a ULi chipset, "
382 "but could not fine the secondary device.\n");
383 return -ENODEV;
384 }
385
386 for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
387 if (uli_sizes[i].size == size)
388 break;
389
390 if (i == ARRAY_SIZE(uli_sizes)) {
391 printk(KERN_INFO PFX "No ULi size found for %d\n", size);
392 return -ENODEV;
393 }
394
395 /* shadow x86-64 registers into ULi registers */
396 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
397
398 /* if x86-64 aperture base is beyond 4G, exit here */
399 if ((httfea & 0x7fff) >> (32 - 25))
400 return -ENODEV;
401
402 httfea = (httfea& 0x7fff) << 25;
403
404 pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
405 baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
406 baseaddr|= httfea;
407 pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
408
409 enuscr= httfea+ (size * 1024 * 1024) - 1;
410 pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
411 pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
412
413 pci_dev_put(dev1);
414 return 0;
415 }
416
417
418 static const struct aper_size_info_32 nforce3_sizes[5] =
419 {
420 {512, 131072, 7, 0x00000000 },
421 {256, 65536, 6, 0x00000008 },
422 {128, 32768, 5, 0x0000000C },
423 {64, 16384, 4, 0x0000000E },
424 {32, 8192, 3, 0x0000000F }
425 };
426
427 /* Handle shadow device of the Nvidia NForce3 */
428 /* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
429 static int nforce3_agp_init(struct pci_dev *pdev)
430 {
431 u32 tmp, apbase, apbar, aplimit;
432 struct pci_dev *dev1;
433 int i;
434 unsigned size = amd64_fetch_size();
435
436 printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n");
437
438 dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
439 if (dev1 == NULL) {
440 printk(KERN_INFO PFX "agpgart: Detected an NVIDIA "
441 "nForce3 chipset, but could not find "
442 "the secondary device.\n");
443 return -ENODEV;
444 }
445
446 for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
447 if (nforce3_sizes[i].size == size)
448 break;
449
450 if (i == ARRAY_SIZE(nforce3_sizes)) {
451 printk(KERN_INFO PFX "No NForce3 size found for %d\n", size);
452 return -ENODEV;
453 }
454
455 pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
456 tmp &= ~(0xf);
457 tmp |= nforce3_sizes[i].size_value;
458 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
459
460 /* shadow x86-64 registers into NVIDIA registers */
461 pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
462
463 /* if x86-64 aperture base is beyond 4G, exit here */
464 if ( (apbase & 0x7fff) >> (32 - 25) ) {
465 printk(KERN_INFO PFX "aperture base > 4G\n");
466 return -ENODEV;
467 }
468
469 apbase = (apbase & 0x7fff) << 25;
470
471 pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
472 apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
473 apbar |= apbase;
474 pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
475
476 aplimit = apbase + (size * 1024 * 1024) - 1;
477 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
478 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
479 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
480 pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
481
482 pci_dev_put(dev1);
483
484 return 0;
485 }
486
487 static int __devinit agp_amd64_probe(struct pci_dev *pdev,
488 const struct pci_device_id *ent)
489 {
490 struct agp_bridge_data *bridge;
491 u8 cap_ptr;
492
493 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
494 if (!cap_ptr)
495 return -ENODEV;
496
497 /* Could check for AGPv3 here */
498
499 bridge = agp_alloc_bridge();
500 if (!bridge)
501 return -ENOMEM;
502
503 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
504 pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
505 amd8151_init(pdev, bridge);
506 } else {
507 printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn);
508 }
509
510 bridge->driver = &amd_8151_driver;
511 bridge->dev = pdev;
512 bridge->capndx = cap_ptr;
513
514 /* Fill in the mode register */
515 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
516
517 if (cache_nbs(pdev, cap_ptr) == -1) {
518 agp_put_bridge(bridge);
519 return -ENODEV;
520 }
521
522 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
523 int ret = nforce3_agp_init(pdev);
524 if (ret) {
525 agp_put_bridge(bridge);
526 return ret;
527 }
528 }
529
530 if (pdev->vendor == PCI_VENDOR_ID_AL) {
531 int ret = uli_agp_init(pdev);
532 if (ret) {
533 agp_put_bridge(bridge);
534 return ret;
535 }
536 }
537
538 pci_set_drvdata(pdev, bridge);
539 return agp_add_bridge(bridge);
540 }
541
542 static void __devexit agp_amd64_remove(struct pci_dev *pdev)
543 {
544 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
545
546 release_mem_region(virt_to_gart(bridge->gatt_table_real),
547 amd64_aperture_sizes[bridge->aperture_size_idx].size);
548 agp_remove_bridge(bridge);
549 agp_put_bridge(bridge);
550 }
551
552 #ifdef CONFIG_PM
553
554 static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
555 {
556 pci_save_state(pdev);
557 pci_set_power_state(pdev, pci_choose_state(pdev, state));
558
559 return 0;
560 }
561
562 static int agp_amd64_resume(struct pci_dev *pdev)
563 {
564 pci_set_power_state(pdev, PCI_D0);
565 pci_restore_state(pdev);
566
567 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
568 nforce3_agp_init(pdev);
569
570 return amd_8151_configure();
571 }
572
573 #endif /* CONFIG_PM */
574
575 static struct pci_device_id agp_amd64_pci_table[] = {
576 {
577 .class = (PCI_CLASS_BRIDGE_HOST << 8),
578 .class_mask = ~0,
579 .vendor = PCI_VENDOR_ID_AMD,
580 .device = PCI_DEVICE_ID_AMD_8151_0,
581 .subvendor = PCI_ANY_ID,
582 .subdevice = PCI_ANY_ID,
583 },
584 /* ULi M1689 */
585 {
586 .class = (PCI_CLASS_BRIDGE_HOST << 8),
587 .class_mask = ~0,
588 .vendor = PCI_VENDOR_ID_AL,
589 .device = PCI_DEVICE_ID_AL_M1689,
590 .subvendor = PCI_ANY_ID,
591 .subdevice = PCI_ANY_ID,
592 },
593 /* VIA K8T800Pro */
594 {
595 .class = (PCI_CLASS_BRIDGE_HOST << 8),
596 .class_mask = ~0,
597 .vendor = PCI_VENDOR_ID_VIA,
598 .device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
599 .subvendor = PCI_ANY_ID,
600 .subdevice = PCI_ANY_ID,
601 },
602 /* VIA K8T800 */
603 {
604 .class = (PCI_CLASS_BRIDGE_HOST << 8),
605 .class_mask = ~0,
606 .vendor = PCI_VENDOR_ID_VIA,
607 .device = PCI_DEVICE_ID_VIA_8385_0,
608 .subvendor = PCI_ANY_ID,
609 .subdevice = PCI_ANY_ID,
610 },
611 /* VIA K8M800 / K8N800 */
612 {
613 .class = (PCI_CLASS_BRIDGE_HOST << 8),
614 .class_mask = ~0,
615 .vendor = PCI_VENDOR_ID_VIA,
616 .device = PCI_DEVICE_ID_VIA_8380_0,
617 .subvendor = PCI_ANY_ID,
618 .subdevice = PCI_ANY_ID,
619 },
620 /* VIA K8M890 / K8N890 */
621 {
622 .class = (PCI_CLASS_BRIDGE_HOST << 8),
623 .class_mask = ~0,
624 .vendor = PCI_VENDOR_ID_VIA,
625 .device = PCI_DEVICE_ID_VIA_VT3336,
626 .subvendor = PCI_ANY_ID,
627 .subdevice = PCI_ANY_ID,
628 },
629 /* VIA K8T890 */
630 {
631 .class = (PCI_CLASS_BRIDGE_HOST << 8),
632 .class_mask = ~0,
633 .vendor = PCI_VENDOR_ID_VIA,
634 .device = PCI_DEVICE_ID_VIA_3238_0,
635 .subvendor = PCI_ANY_ID,
636 .subdevice = PCI_ANY_ID,
637 },
638 /* VIA K8T800/K8M800/K8N800 */
639 {
640 .class = (PCI_CLASS_BRIDGE_HOST << 8),
641 .class_mask = ~0,
642 .vendor = PCI_VENDOR_ID_VIA,
643 .device = PCI_DEVICE_ID_VIA_838X_1,
644 .subvendor = PCI_ANY_ID,
645 .subdevice = PCI_ANY_ID,
646 },
647 /* NForce3 */
648 {
649 .class = (PCI_CLASS_BRIDGE_HOST << 8),
650 .class_mask = ~0,
651 .vendor = PCI_VENDOR_ID_NVIDIA,
652 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
653 .subvendor = PCI_ANY_ID,
654 .subdevice = PCI_ANY_ID,
655 },
656 {
657 .class = (PCI_CLASS_BRIDGE_HOST << 8),
658 .class_mask = ~0,
659 .vendor = PCI_VENDOR_ID_NVIDIA,
660 .device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
661 .subvendor = PCI_ANY_ID,
662 .subdevice = PCI_ANY_ID,
663 },
664 /* SIS 755 */
665 {
666 .class = (PCI_CLASS_BRIDGE_HOST << 8),
667 .class_mask = ~0,
668 .vendor = PCI_VENDOR_ID_SI,
669 .device = PCI_DEVICE_ID_SI_755,
670 .subvendor = PCI_ANY_ID,
671 .subdevice = PCI_ANY_ID,
672 },
673 /* SIS 760 */
674 {
675 .class = (PCI_CLASS_BRIDGE_HOST << 8),
676 .class_mask = ~0,
677 .vendor = PCI_VENDOR_ID_SI,
678 .device = PCI_DEVICE_ID_SI_760,
679 .subvendor = PCI_ANY_ID,
680 .subdevice = PCI_ANY_ID,
681 },
682 /* ALI/ULI M1695 */
683 {
684 .class = (PCI_CLASS_BRIDGE_HOST << 8),
685 .class_mask = ~0,
686 .vendor = PCI_VENDOR_ID_AL,
687 .device = 0x1695,
688 .subvendor = PCI_ANY_ID,
689 .subdevice = PCI_ANY_ID,
690 },
691
692 { }
693 };
694
695 MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
696
697 static struct pci_driver agp_amd64_pci_driver = {
698 .name = "agpgart-amd64",
699 .id_table = agp_amd64_pci_table,
700 .probe = agp_amd64_probe,
701 .remove = agp_amd64_remove,
702 #ifdef CONFIG_PM
703 .suspend = agp_amd64_suspend,
704 .resume = agp_amd64_resume,
705 #endif
706 };
707
708
709 /* Not static due to IOMMU code calling it early. */
710 int __init agp_amd64_init(void)
711 {
712 int err = 0;
713
714 if (agp_off)
715 return -EINVAL;
716 if (pci_register_driver(&agp_amd64_pci_driver) < 0) {
717 struct pci_dev *dev;
718 if (!agp_try_unsupported && !agp_try_unsupported_boot) {
719 printk(KERN_INFO PFX "No supported AGP bridge found.\n");
720 #ifdef MODULE
721 printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
722 #else
723 printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
724 #endif
725 return -ENODEV;
726 }
727
728 /* First check that we have at least one AMD64 NB */
729 if (!pci_dev_present(k8_nb_ids))
730 return -ENODEV;
731
732 /* Look for any AGP bridge */
733 dev = NULL;
734 err = -ENODEV;
735 for_each_pci_dev(dev) {
736 if (!pci_find_capability(dev, PCI_CAP_ID_AGP))
737 continue;
738 /* Only one bridge supported right now */
739 if (agp_amd64_probe(dev, NULL) == 0) {
740 err = 0;
741 break;
742 }
743 }
744 }
745 return err;
746 }
747
748 static void __exit agp_amd64_cleanup(void)
749 {
750 if (aperture_resource)
751 release_resource(aperture_resource);
752 pci_unregister_driver(&agp_amd64_pci_driver);
753 }
754
755 /* On AMD64 the PCI driver needs to initialize this driver early
756 for the IOMMU, so it has to be called via a backdoor. */
757 #ifndef CONFIG_GART_IOMMU
758 module_init(agp_amd64_init);
759 module_exit(agp_amd64_cleanup);
760 #endif
761
762 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen");
763 module_param(agp_try_unsupported, bool, 0);
764 MODULE_LICENSE("GPL");
WandBoard kernel