2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
29 * Allocates a generic ring segment from the ring pool, sets the dma address,
30 * initializes the segment to zero, and sets the private next pointer to NULL.
33 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
35 static struct xhci_segment
*xhci_segment_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
37 struct xhci_segment
*seg
;
40 seg
= kzalloc(sizeof *seg
, flags
);
43 xhci_dbg(xhci
, "Allocating priv segment structure at 0x%x\n",
46 seg
->trbs
= dma_pool_alloc(xhci
->segment_pool
, flags
, &dma
);
51 xhci_dbg(xhci
, "// Allocating segment at 0x%x (virtual) 0x%x (DMA)\n",
52 (unsigned int) seg
->trbs
, (u32
) dma
);
54 memset(seg
->trbs
, 0, SEGMENT_SIZE
);
61 static void xhci_segment_free(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
)
66 xhci_dbg(xhci
, "Freeing DMA segment at 0x%x"
67 " (virtual) 0x%x (DMA)\n",
68 (unsigned int) seg
->trbs
, (u32
) seg
->dma
);
69 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, seg
->dma
);
72 xhci_dbg(xhci
, "Freeing priv segment structure at 0x%x\n",
78 * Make the prev segment point to the next segment.
80 * Change the last TRB in the prev segment to be a Link TRB which points to the
81 * DMA address of the next segment. The caller needs to set any Link TRB
82 * related flags, such as End TRB, Toggle Cycle, and no snoop.
84 static void xhci_link_segments(struct xhci_hcd
*xhci
, struct xhci_segment
*prev
,
85 struct xhci_segment
*next
, bool link_trbs
)
93 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.segment_ptr
[0] = next
->dma
;
95 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
96 val
= prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
;
97 val
&= ~TRB_TYPE_BITMASK
;
98 val
|= TRB_TYPE(TRB_LINK
);
99 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
= val
;
101 xhci_dbg(xhci
, "Linking segment 0x%x to segment 0x%x (DMA)\n",
102 prev
->dma
, next
->dma
);
105 /* XXX: Do we need the hcd structure in all these functions? */
106 static void xhci_ring_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
108 struct xhci_segment
*seg
;
109 struct xhci_segment
*first_seg
;
111 if (!ring
|| !ring
->first_seg
)
113 first_seg
= ring
->first_seg
;
114 seg
= first_seg
->next
;
115 xhci_dbg(xhci
, "Freeing ring at 0x%x\n", (unsigned int) ring
);
116 while (seg
!= first_seg
) {
117 struct xhci_segment
*next
= seg
->next
;
118 xhci_segment_free(xhci
, seg
);
121 xhci_segment_free(xhci
, first_seg
);
122 ring
->first_seg
= NULL
;
127 * Create a new ring with zero or more segments.
129 * Link each segment together into a ring.
130 * Set the end flag and the cycle toggle bit on the last segment.
131 * See section 4.9.1 and figures 15 and 16.
133 static struct xhci_ring
*xhci_ring_alloc(struct xhci_hcd
*xhci
,
134 unsigned int num_segs
, bool link_trbs
, gfp_t flags
)
136 struct xhci_ring
*ring
;
137 struct xhci_segment
*prev
;
139 ring
= kzalloc(sizeof *(ring
), flags
);
140 xhci_dbg(xhci
, "Allocating ring at 0x%x\n", (unsigned int) ring
);
144 INIT_LIST_HEAD(&ring
->td_list
);
148 ring
->first_seg
= xhci_segment_alloc(xhci
, flags
);
149 if (!ring
->first_seg
)
153 prev
= ring
->first_seg
;
154 while (num_segs
> 0) {
155 struct xhci_segment
*next
;
157 next
= xhci_segment_alloc(xhci
, flags
);
160 xhci_link_segments(xhci
, prev
, next
, link_trbs
);
165 xhci_link_segments(xhci
, prev
, ring
->first_seg
, link_trbs
);
168 /* See section 4.9.2.1 and 6.4.4.1 */
169 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
|= (LINK_TOGGLE
);
170 xhci_dbg(xhci
, "Wrote link toggle flag to"
171 " segment 0x%x (virtual), 0x%x (DMA)\n",
172 (unsigned int) prev
, (u32
) prev
->dma
);
174 /* The ring is empty, so the enqueue pointer == dequeue pointer */
175 ring
->enqueue
= ring
->first_seg
->trbs
;
176 ring
->enq_seg
= ring
->first_seg
;
177 ring
->dequeue
= ring
->enqueue
;
178 ring
->deq_seg
= ring
->first_seg
;
179 /* The ring is initialized to 0. The producer must write 1 to the cycle
180 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
181 * compare CCS to the cycle bit to check ownership, so CCS = 1.
183 ring
->cycle_state
= 1;
188 xhci_ring_free(xhci
, ring
);
192 /* All the xhci_tds in the ring's TD list should be freed at this point */
193 void xhci_free_virt_device(struct xhci_hcd
*xhci
, int slot_id
)
195 struct xhci_virt_device
*dev
;
198 /* Slot ID 0 is reserved */
199 if (slot_id
== 0 || !xhci
->devs
[slot_id
])
202 dev
= xhci
->devs
[slot_id
];
203 xhci
->dcbaa
->dev_context_ptrs
[2*slot_id
] = 0;
204 xhci
->dcbaa
->dev_context_ptrs
[2*slot_id
+ 1] = 0;
208 for (i
= 0; i
< 31; ++i
)
209 if (dev
->ep_rings
[i
])
210 xhci_ring_free(xhci
, dev
->ep_rings
[i
]);
213 dma_pool_free(xhci
->device_pool
,
214 dev
->in_ctx
, dev
->in_ctx_dma
);
216 dma_pool_free(xhci
->device_pool
,
217 dev
->out_ctx
, dev
->out_ctx_dma
);
218 kfree(xhci
->devs
[slot_id
]);
219 xhci
->devs
[slot_id
] = 0;
222 int xhci_alloc_virt_device(struct xhci_hcd
*xhci
, int slot_id
,
223 struct usb_device
*udev
, gfp_t flags
)
226 struct xhci_virt_device
*dev
;
228 /* Slot ID 0 is reserved */
229 if (slot_id
== 0 || xhci
->devs
[slot_id
]) {
230 xhci_warn(xhci
, "Bad Slot ID %d\n", slot_id
);
234 xhci
->devs
[slot_id
] = kzalloc(sizeof(*xhci
->devs
[slot_id
]), flags
);
235 if (!xhci
->devs
[slot_id
])
237 dev
= xhci
->devs
[slot_id
];
239 /* Allocate the (output) device context that will be used in the HC */
240 dev
->out_ctx
= dma_pool_alloc(xhci
->device_pool
, flags
, &dma
);
243 dev
->out_ctx_dma
= dma
;
244 xhci_dbg(xhci
, "Slot %d output ctx = 0x%x (dma)\n", slot_id
, dma
);
245 memset(dev
->out_ctx
, 0, sizeof(*dev
->out_ctx
));
247 /* Allocate the (input) device context for address device command */
248 dev
->in_ctx
= dma_pool_alloc(xhci
->device_pool
, flags
, &dma
);
251 dev
->in_ctx_dma
= dma
;
252 xhci_dbg(xhci
, "Slot %d input ctx = 0x%x (dma)\n", slot_id
, dma
);
253 memset(dev
->in_ctx
, 0, sizeof(*dev
->in_ctx
));
255 /* Allocate endpoint 0 ring */
256 dev
->ep_rings
[0] = xhci_ring_alloc(xhci
, 1, true, flags
);
257 if (!dev
->ep_rings
[0])
261 * Point to output device context in dcbaa; skip the output control
262 * context, which is eight 32 bit fields (or 32 bytes long)
264 xhci
->dcbaa
->dev_context_ptrs
[2*slot_id
] =
265 (u32
) dev
->out_ctx_dma
+ (32);
266 xhci_dbg(xhci
, "Set slot id %d dcbaa entry 0x%x to 0x%x\n",
268 (unsigned int) &xhci
->dcbaa
->dev_context_ptrs
[2*slot_id
],
270 xhci
->dcbaa
->dev_context_ptrs
[2*slot_id
+ 1] = 0;
274 xhci_free_virt_device(xhci
, slot_id
);
278 /* Setup an xHCI virtual device for a Set Address command */
279 int xhci_setup_addressable_virt_dev(struct xhci_hcd
*xhci
, struct usb_device
*udev
)
281 struct xhci_virt_device
*dev
;
282 struct xhci_ep_ctx
*ep0_ctx
;
283 struct usb_device
*top_dev
;
285 dev
= xhci
->devs
[udev
->slot_id
];
286 /* Slot ID 0 is reserved */
287 if (udev
->slot_id
== 0 || !dev
) {
288 xhci_warn(xhci
, "Slot ID %d is not assigned to this device\n",
292 ep0_ctx
= &dev
->in_ctx
->ep
[0];
294 /* 2) New slot context and endpoint 0 context are valid*/
295 dev
->in_ctx
->add_flags
= SLOT_FLAG
| EP0_FLAG
;
297 /* 3) Only the control endpoint is valid - one endpoint context */
298 dev
->in_ctx
->slot
.dev_info
|= LAST_CTX(1);
300 switch (udev
->speed
) {
301 case USB_SPEED_SUPER
:
302 dev
->in_ctx
->slot
.dev_info
|= (u32
) udev
->route
;
303 dev
->in_ctx
->slot
.dev_info
|= (u32
) SLOT_SPEED_SS
;
306 dev
->in_ctx
->slot
.dev_info
|= (u32
) SLOT_SPEED_HS
;
309 dev
->in_ctx
->slot
.dev_info
|= (u32
) SLOT_SPEED_FS
;
312 dev
->in_ctx
->slot
.dev_info
|= (u32
) SLOT_SPEED_LS
;
314 case USB_SPEED_VARIABLE
:
315 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
319 /* Speed was set earlier, this shouldn't happen. */
322 /* Find the root hub port this device is under */
323 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
324 top_dev
= top_dev
->parent
)
325 /* Found device below root hub */;
326 dev
->in_ctx
->slot
.dev_info2
|= (u32
) ROOT_HUB_PORT(top_dev
->portnum
);
327 xhci_dbg(xhci
, "Set root hub portnum to %d\n", top_dev
->portnum
);
329 /* Is this a LS/FS device under a HS hub? */
331 * FIXME: I don't think this is right, where does the TT info for the
332 * roothub or parent hub come from?
334 if ((udev
->speed
== USB_SPEED_LOW
|| udev
->speed
== USB_SPEED_FULL
) &&
336 dev
->in_ctx
->slot
.tt_info
= udev
->tt
->hub
->slot_id
;
337 dev
->in_ctx
->slot
.tt_info
|= udev
->ttport
<< 8;
339 xhci_dbg(xhci
, "udev->tt = 0x%x\n", (unsigned int) udev
->tt
);
340 xhci_dbg(xhci
, "udev->ttport = 0x%x\n", udev
->ttport
);
342 /* Step 4 - ring already allocated */
344 ep0_ctx
->ep_info2
= EP_TYPE(CTRL_EP
);
346 * See section 4.3 bullet 6:
347 * The default Max Packet size for ep0 is "8 bytes for a USB2
348 * LS/FS/HS device or 512 bytes for a USB3 SS device"
349 * XXX: Not sure about wireless USB devices.
351 if (udev
->speed
== USB_SPEED_SUPER
)
352 ep0_ctx
->ep_info2
|= MAX_PACKET(512);
354 ep0_ctx
->ep_info2
|= MAX_PACKET(8);
355 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
356 ep0_ctx
->ep_info2
|= MAX_BURST(0);
357 ep0_ctx
->ep_info2
|= ERROR_COUNT(3);
360 dev
->ep_rings
[0]->first_seg
->dma
;
361 ep0_ctx
->deq
[0] |= dev
->ep_rings
[0]->cycle_state
;
364 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
369 void xhci_mem_cleanup(struct xhci_hcd
*xhci
)
371 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
375 /* Free the Event Ring Segment Table and the actual Event Ring */
376 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_size
);
377 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_base
[1]);
378 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_base
[0]);
379 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_dequeue
[1]);
380 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_dequeue
[0]);
381 size
= sizeof(struct xhci_erst_entry
)*(xhci
->erst
.num_entries
);
382 if (xhci
->erst
.entries
)
383 pci_free_consistent(pdev
, size
,
384 xhci
->erst
.entries
, xhci
->erst
.erst_dma_addr
);
385 xhci
->erst
.entries
= NULL
;
386 xhci_dbg(xhci
, "Freed ERST\n");
387 if (xhci
->event_ring
)
388 xhci_ring_free(xhci
, xhci
->event_ring
);
389 xhci
->event_ring
= NULL
;
390 xhci_dbg(xhci
, "Freed event ring\n");
392 xhci_writel(xhci
, 0, &xhci
->op_regs
->cmd_ring
[1]);
393 xhci_writel(xhci
, 0, &xhci
->op_regs
->cmd_ring
[0]);
395 xhci_ring_free(xhci
, xhci
->cmd_ring
);
396 xhci
->cmd_ring
= NULL
;
397 xhci_dbg(xhci
, "Freed command ring\n");
399 for (i
= 1; i
< MAX_HC_SLOTS
; ++i
)
400 xhci_free_virt_device(xhci
, i
);
402 if (xhci
->segment_pool
)
403 dma_pool_destroy(xhci
->segment_pool
);
404 xhci
->segment_pool
= NULL
;
405 xhci_dbg(xhci
, "Freed segment pool\n");
407 if (xhci
->device_pool
)
408 dma_pool_destroy(xhci
->device_pool
);
409 xhci
->device_pool
= NULL
;
410 xhci_dbg(xhci
, "Freed device context pool\n");
412 xhci_writel(xhci
, 0, &xhci
->op_regs
->dcbaa_ptr
[1]);
413 xhci_writel(xhci
, 0, &xhci
->op_regs
->dcbaa_ptr
[0]);
415 pci_free_consistent(pdev
, sizeof(*xhci
->dcbaa
),
416 xhci
->dcbaa
, xhci
->dcbaa
->dma
);
420 xhci
->page_shift
= 0;
423 int xhci_mem_init(struct xhci_hcd
*xhci
, gfp_t flags
)
426 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
427 unsigned int val
, val2
;
428 struct xhci_segment
*seg
;
432 page_size
= xhci_readl(xhci
, &xhci
->op_regs
->page_size
);
433 xhci_dbg(xhci
, "Supported page size register = 0x%x\n", page_size
);
434 for (i
= 0; i
< 16; i
++) {
435 if ((0x1 & page_size
) != 0)
437 page_size
= page_size
>> 1;
440 xhci_dbg(xhci
, "Supported page size of %iK\n", (1 << (i
+12)) / 1024);
442 xhci_warn(xhci
, "WARN: no supported page size\n");
443 /* Use 4K pages, since that's common and the minimum the HC supports */
444 xhci
->page_shift
= 12;
445 xhci
->page_size
= 1 << xhci
->page_shift
;
446 xhci_dbg(xhci
, "HCD page size set to %iK\n", xhci
->page_size
/ 1024);
449 * Program the Number of Device Slots Enabled field in the CONFIG
450 * register with the max value of slots the HC can handle.
452 val
= HCS_MAX_SLOTS(xhci_readl(xhci
, &xhci
->cap_regs
->hcs_params1
));
453 xhci_dbg(xhci
, "// xHC can handle at most %d device slots.\n",
455 val2
= xhci_readl(xhci
, &xhci
->op_regs
->config_reg
);
456 val
|= (val2
& ~HCS_SLOTS_MASK
);
457 xhci_dbg(xhci
, "// Setting Max device slots reg = 0x%x.\n",
459 xhci_writel(xhci
, val
, &xhci
->op_regs
->config_reg
);
462 * Section 5.4.8 - doorbell array must be
463 * "physically contiguous and 64-byte (cache line) aligned".
465 xhci
->dcbaa
= pci_alloc_consistent(to_pci_dev(dev
),
466 sizeof(*xhci
->dcbaa
), &dma
);
469 memset(xhci
->dcbaa
, 0, sizeof *(xhci
->dcbaa
));
470 xhci
->dcbaa
->dma
= dma
;
471 xhci_dbg(xhci
, "// Device context base array address = 0x%x (DMA), 0x%x (virt)\n",
472 xhci
->dcbaa
->dma
, (unsigned int) xhci
->dcbaa
);
473 xhci_writel(xhci
, (u32
) 0, &xhci
->op_regs
->dcbaa_ptr
[1]);
474 xhci_writel(xhci
, dma
, &xhci
->op_regs
->dcbaa_ptr
[0]);
477 * Initialize the ring segment pool. The ring must be a contiguous
478 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
479 * however, the command ring segment needs 64-byte aligned segments,
480 * so we pick the greater alignment need.
482 xhci
->segment_pool
= dma_pool_create("xHCI ring segments", dev
,
483 SEGMENT_SIZE
, 64, xhci
->page_size
);
484 /* See Table 46 and Note on Figure 55 */
485 /* FIXME support 64-byte contexts */
486 xhci
->device_pool
= dma_pool_create("xHCI input/output contexts", dev
,
487 sizeof(struct xhci_device_control
),
488 64, xhci
->page_size
);
489 if (!xhci
->segment_pool
|| !xhci
->device_pool
)
492 /* Set up the command ring to have one segments for now. */
493 xhci
->cmd_ring
= xhci_ring_alloc(xhci
, 1, true, flags
);
496 xhci_dbg(xhci
, "Allocated command ring at 0x%x\n", (unsigned int) xhci
->cmd_ring
);
497 xhci_dbg(xhci
, "First segment DMA is 0x%x\n", (unsigned int) xhci
->cmd_ring
->first_seg
->dma
);
499 /* Set the address in the Command Ring Control register */
500 val
= xhci_readl(xhci
, &xhci
->op_regs
->cmd_ring
[0]);
501 val
= (val
& ~CMD_RING_ADDR_MASK
) |
502 (xhci
->cmd_ring
->first_seg
->dma
& CMD_RING_ADDR_MASK
) |
503 xhci
->cmd_ring
->cycle_state
;
504 xhci_dbg(xhci
, "// Setting command ring address high bits to 0x0\n");
505 xhci_writel(xhci
, (u32
) 0, &xhci
->op_regs
->cmd_ring
[1]);
506 xhci_dbg(xhci
, "// Setting command ring address low bits to 0x%x\n", val
);
507 xhci_writel(xhci
, val
, &xhci
->op_regs
->cmd_ring
[0]);
508 xhci_dbg_cmd_ptrs(xhci
);
510 val
= xhci_readl(xhci
, &xhci
->cap_regs
->db_off
);
512 xhci_dbg(xhci
, "// Doorbell array is located at offset 0x%x"
513 " from cap regs base addr\n", val
);
514 xhci
->dba
= (void *) xhci
->cap_regs
+ val
;
516 xhci_print_run_regs(xhci
);
517 /* Set ir_set to interrupt register set 0 */
518 xhci
->ir_set
= (void *) xhci
->run_regs
->ir_set
;
521 * Event ring setup: Allocate a normal ring, but also setup
522 * the event ring segment table (ERST). Section 4.9.3.
524 xhci_dbg(xhci
, "// Allocating event ring\n");
525 xhci
->event_ring
= xhci_ring_alloc(xhci
, ERST_NUM_SEGS
, false, flags
);
526 if (!xhci
->event_ring
)
529 xhci
->erst
.entries
= pci_alloc_consistent(to_pci_dev(dev
),
530 sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
, &dma
);
531 if (!xhci
->erst
.entries
)
533 xhci_dbg(xhci
, "// Allocated event ring segment table at 0x%x\n", dma
);
535 memset(xhci
->erst
.entries
, 0, sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
);
536 xhci
->erst
.num_entries
= ERST_NUM_SEGS
;
537 xhci
->erst
.erst_dma_addr
= dma
;
538 xhci_dbg(xhci
, "Set ERST to 0; private num segs = %i, virt addr = 0x%x, dma addr = 0x%x\n",
539 xhci
->erst
.num_entries
,
540 (unsigned int) xhci
->erst
.entries
,
541 xhci
->erst
.erst_dma_addr
);
543 /* set ring base address and size for each segment table entry */
544 for (val
= 0, seg
= xhci
->event_ring
->first_seg
; val
< ERST_NUM_SEGS
; val
++) {
545 struct xhci_erst_entry
*entry
= &xhci
->erst
.entries
[val
];
546 entry
->seg_addr
[1] = 0;
547 entry
->seg_addr
[0] = seg
->dma
;
548 entry
->seg_size
= TRBS_PER_SEGMENT
;
553 /* set ERST count with the number of entries in the segment table */
554 val
= xhci_readl(xhci
, &xhci
->ir_set
->erst_size
);
555 val
&= ERST_SIZE_MASK
;
556 val
|= ERST_NUM_SEGS
;
557 xhci_dbg(xhci
, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
559 xhci_writel(xhci
, val
, &xhci
->ir_set
->erst_size
);
561 xhci_dbg(xhci
, "// Set ERST entries to point to event ring.\n");
562 /* set the segment table base address */
563 xhci_dbg(xhci
, "// Set ERST base address for ir_set 0 = 0x%x\n",
564 xhci
->erst
.erst_dma_addr
);
565 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_base
[1]);
566 val
= xhci_readl(xhci
, &xhci
->ir_set
->erst_base
[0]);
567 val
&= ERST_PTR_MASK
;
568 val
|= (xhci
->erst
.erst_dma_addr
& ~ERST_PTR_MASK
);
569 xhci_writel(xhci
, val
, &xhci
->ir_set
->erst_base
[0]);
571 /* Set the event ring dequeue address */
572 set_hc_event_deq(xhci
);
573 xhci_dbg(xhci
, "Wrote ERST address to ir_set 0.\n");
574 xhci_print_ir_set(xhci
, xhci
->ir_set
, 0);
577 * XXX: Might need to set the Interrupter Moderation Register to
578 * something other than the default (~1ms minimum between interrupts).
579 * See section 5.5.1.2.
581 init_completion(&xhci
->addr_dev
);
582 for (i
= 0; i
< MAX_HC_SLOTS
; ++i
)
587 xhci_warn(xhci
, "Couldn't initialize memory\n");
588 xhci_mem_cleanup(xhci
);