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[SPARC64]: Do not call winfix_dax blindly
[wandboard.git] / arch / sparc64 / kernel / traps.c
blob210b3e321c29babd47cfbb7fda4ece1c42fe8357
1 /* $Id: traps.c,v 1.85 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/kernel/traps.c
3 *
4 * Copyright (C) 1995,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997,1999,2000 Jakub Jelinek (jakub@redhat.com)
6 */
7
8 /*
9 * I like traps on v9, :))))
10 */
11
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/sched.h> /* for jiffies */
15 #include <linux/kernel.h>
16 #include <linux/kallsyms.h>
17 #include <linux/signal.h>
18 #include <linux/smp.h>
19 #include <linux/smp_lock.h>
20 #include <linux/mm.h>
21 #include <linux/init.h>
22
23 #include <asm/delay.h>
24 #include <asm/system.h>
25 #include <asm/ptrace.h>
26 #include <asm/oplib.h>
27 #include <asm/page.h>
28 #include <asm/pgtable.h>
29 #include <asm/unistd.h>
30 #include <asm/uaccess.h>
31 #include <asm/fpumacro.h>
32 #include <asm/lsu.h>
33 #include <asm/dcu.h>
34 #include <asm/estate.h>
35 #include <asm/chafsr.h>
36 #include <asm/psrcompat.h>
37 #include <asm/processor.h>
38 #include <asm/timer.h>
39 #include <asm/kdebug.h>
40 #ifdef CONFIG_KMOD
41 #include <linux/kmod.h>
42 #endif
43
44 struct notifier_block *sparc64die_chain;
45 static DEFINE_SPINLOCK(die_notifier_lock);
46
47 int register_die_notifier(struct notifier_block *nb)
48 {
49 int err = 0;
50 unsigned long flags;
51 spin_lock_irqsave(&die_notifier_lock, flags);
52 err = notifier_chain_register(&sparc64die_chain, nb);
53 spin_unlock_irqrestore(&die_notifier_lock, flags);
54 return err;
55 }
56
57 /* When an irrecoverable trap occurs at tl > 0, the trap entry
58 * code logs the trap state registers at every level in the trap
59 * stack. It is found at (pt_regs + sizeof(pt_regs)) and the layout
60 * is as follows:
61 */
62 struct tl1_traplog {
63 struct {
64 unsigned long tstate;
65 unsigned long tpc;
66 unsigned long tnpc;
67 unsigned long tt;
68 } trapstack[4];
69 unsigned long tl;
70 };
71
72 static void dump_tl1_traplog(struct tl1_traplog *p)
73 {
74 int i;
75
76 printk("TRAPLOG: Error at trap level 0x%lx, dumping track stack.\n",
77 p->tl);
78 for (i = 0; i < 4; i++) {
79 printk(KERN_CRIT
80 "TRAPLOG: Trap level %d TSTATE[%016lx] TPC[%016lx] "
81 "TNPC[%016lx] TT[%lx]\n",
82 i + 1,
83 p->trapstack[i].tstate, p->trapstack[i].tpc,
84 p->trapstack[i].tnpc, p->trapstack[i].tt);
85 }
86 }
87
88 void do_call_debug(struct pt_regs *regs)
89 {
90 notify_die(DIE_CALL, "debug call", regs, 0, 255, SIGINT);
91 }
92
93 void bad_trap(struct pt_regs *regs, long lvl)
94 {
95 char buffer[32];
96 siginfo_t info;
97
98 if (notify_die(DIE_TRAP, "bad trap", regs,
99 0, lvl, SIGTRAP) == NOTIFY_STOP)
100 return;
101
102 if (lvl < 0x100) {
103 sprintf(buffer, "Bad hw trap %lx at tl0\n", lvl);
104 die_if_kernel(buffer, regs);
105 }
106
107 lvl -= 0x100;
108 if (regs->tstate & TSTATE_PRIV) {
109 sprintf(buffer, "Kernel bad sw trap %lx", lvl);
110 die_if_kernel(buffer, regs);
111 }
112 if (test_thread_flag(TIF_32BIT)) {
113 regs->tpc &= 0xffffffff;
114 regs->tnpc &= 0xffffffff;
115 }
116 info.si_signo = SIGILL;
117 info.si_errno = 0;
118 info.si_code = ILL_ILLTRP;
119 info.si_addr = (void __user *)regs->tpc;
120 info.si_trapno = lvl;
121 force_sig_info(SIGILL, &info, current);
122 }
123
124 void bad_trap_tl1(struct pt_regs *regs, long lvl)
125 {
126 char buffer[32];
127
128 if (notify_die(DIE_TRAP_TL1, "bad trap tl1", regs,
129 0, lvl, SIGTRAP) == NOTIFY_STOP)
130 return;
131
132 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
133
134 sprintf (buffer, "Bad trap %lx at tl>0", lvl);
135 die_if_kernel (buffer, regs);
136 }
137
138 #ifdef CONFIG_DEBUG_BUGVERBOSE
139 void do_BUG(const char *file, int line)
140 {
141 bust_spinlocks(1);
142 printk("kernel BUG at %s:%d!\n", file, line);
143 }
144 #endif
145
146 void instruction_access_exception(struct pt_regs *regs,
147 unsigned long sfsr, unsigned long sfar)
148 {
149 siginfo_t info;
150
151 if (notify_die(DIE_TRAP, "instruction access exception", regs,
152 0, 0x8, SIGTRAP) == NOTIFY_STOP)
153 return;
154
155 if (regs->tstate & TSTATE_PRIV) {
156 printk("instruction_access_exception: SFSR[%016lx] SFAR[%016lx], going.\n",
157 sfsr, sfar);
158 die_if_kernel("Iax", regs);
159 }
160 if (test_thread_flag(TIF_32BIT)) {
161 regs->tpc &= 0xffffffff;
162 regs->tnpc &= 0xffffffff;
163 }
164 info.si_signo = SIGSEGV;
165 info.si_errno = 0;
166 info.si_code = SEGV_MAPERR;
167 info.si_addr = (void __user *)regs->tpc;
168 info.si_trapno = 0;
169 force_sig_info(SIGSEGV, &info, current);
170 }
171
172 void instruction_access_exception_tl1(struct pt_regs *regs,
173 unsigned long sfsr, unsigned long sfar)
174 {
175 if (notify_die(DIE_TRAP_TL1, "instruction access exception tl1", regs,
176 0, 0x8, SIGTRAP) == NOTIFY_STOP)
177 return;
178
179 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
180 instruction_access_exception(regs, sfsr, sfar);
181 }
182
183 void data_access_exception(struct pt_regs *regs,
184 unsigned long sfsr, unsigned long sfar)
185 {
186 siginfo_t info;
187
188 if (notify_die(DIE_TRAP, "data access exception", regs,
189 0, 0x30, SIGTRAP) == NOTIFY_STOP)
190 return;
191
192 if (regs->tstate & TSTATE_PRIV) {
193 /* Test if this comes from uaccess places. */
194 unsigned long fixup;
195 unsigned long g2 = regs->u_regs[UREG_G2];
196
197 if ((fixup = search_extables_range(regs->tpc, &g2))) {
198 /* Ouch, somebody is trying ugly VM hole tricks on us... */
199 #ifdef DEBUG_EXCEPTIONS
200 printk("Exception: PC<%016lx> faddr<UNKNOWN>\n", regs->tpc);
201 printk("EX_TABLE: insn<%016lx> fixup<%016lx> "
202 "g2<%016lx>\n", regs->tpc, fixup, g2);
203 #endif
204 regs->tpc = fixup;
205 regs->tnpc = regs->tpc + 4;
206 regs->u_regs[UREG_G2] = g2;
207 return;
208 }
209 /* Shit... */
210 printk("data_access_exception: SFSR[%016lx] SFAR[%016lx], going.\n",
211 sfsr, sfar);
212 die_if_kernel("Dax", regs);
213 }
214
215 info.si_signo = SIGSEGV;
216 info.si_errno = 0;
217 info.si_code = SEGV_MAPERR;
218 info.si_addr = (void __user *)sfar;
219 info.si_trapno = 0;
220 force_sig_info(SIGSEGV, &info, current);
221 }
222
223 void data_access_exception_tl1(struct pt_regs *regs,
224 unsigned long sfsr, unsigned long sfar)
225 {
226 if (notify_die(DIE_TRAP_TL1, "data access exception tl1", regs,
227 0, 0x30, SIGTRAP) == NOTIFY_STOP)
228 return;
229
230 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
231 data_access_exception(regs, sfsr, sfar);
232 }
233
234 #ifdef CONFIG_PCI
235 /* This is really pathetic... */
236 extern volatile int pci_poke_in_progress;
237 extern volatile int pci_poke_cpu;
238 extern volatile int pci_poke_faulted;
239 #endif
240
241 /* When access exceptions happen, we must do this. */
242 static void spitfire_clean_and_reenable_l1_caches(void)
243 {
244 unsigned long va;
245
246 if (tlb_type != spitfire)
247 BUG();
248
249 /* Clean 'em. */
250 for (va = 0; va < (PAGE_SIZE << 1); va += 32) {
251 spitfire_put_icache_tag(va, 0x0);
252 spitfire_put_dcache_tag(va, 0x0);
253 }
254
255 /* Re-enable in LSU. */
256 __asm__ __volatile__("flush %%g6\n\t"
257 "membar #Sync\n\t"
258 "stxa %0, [%%g0] %1\n\t"
259 "membar #Sync"
260 : /* no outputs */
261 : "r" (LSU_CONTROL_IC | LSU_CONTROL_DC |
262 LSU_CONTROL_IM | LSU_CONTROL_DM),
263 "i" (ASI_LSU_CONTROL)
264 : "memory");
265 }
266
267 void do_iae(struct pt_regs *regs)
268 {
269 siginfo_t info;
270
271 spitfire_clean_and_reenable_l1_caches();
272
273 if (notify_die(DIE_TRAP, "instruction access exception", regs,
274 0, 0x8, SIGTRAP) == NOTIFY_STOP)
275 return;
276
277 info.si_signo = SIGBUS;
278 info.si_errno = 0;
279 info.si_code = BUS_OBJERR;
280 info.si_addr = (void *)0;
281 info.si_trapno = 0;
282 force_sig_info(SIGBUS, &info, current);
283 }
284
285 void do_dae(struct pt_regs *regs)
286 {
287 siginfo_t info;
288
289 #ifdef CONFIG_PCI
290 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
291 spitfire_clean_and_reenable_l1_caches();
292
293 pci_poke_faulted = 1;
294
295 /* Why the fuck did they have to change this? */
296 if (tlb_type == cheetah || tlb_type == cheetah_plus)
297 regs->tpc += 4;
298
299 regs->tnpc = regs->tpc + 4;
300 return;
301 }
302 #endif
303 spitfire_clean_and_reenable_l1_caches();
304
305 if (notify_die(DIE_TRAP, "data access exception", regs,
306 0, 0x30, SIGTRAP) == NOTIFY_STOP)
307 return;
308
309 info.si_signo = SIGBUS;
310 info.si_errno = 0;
311 info.si_code = BUS_OBJERR;
312 info.si_addr = (void *)0;
313 info.si_trapno = 0;
314 force_sig_info(SIGBUS, &info, current);
315 }
316
317 static char ecc_syndrome_table[] = {
318 0x4c, 0x40, 0x41, 0x48, 0x42, 0x48, 0x48, 0x49,
319 0x43, 0x48, 0x48, 0x49, 0x48, 0x49, 0x49, 0x4a,
320 0x44, 0x48, 0x48, 0x20, 0x48, 0x39, 0x4b, 0x48,
321 0x48, 0x25, 0x31, 0x48, 0x28, 0x48, 0x48, 0x2c,
322 0x45, 0x48, 0x48, 0x21, 0x48, 0x3d, 0x04, 0x48,
323 0x48, 0x4b, 0x35, 0x48, 0x2d, 0x48, 0x48, 0x29,
324 0x48, 0x00, 0x01, 0x48, 0x0a, 0x48, 0x48, 0x4b,
325 0x0f, 0x48, 0x48, 0x4b, 0x48, 0x49, 0x49, 0x48,
326 0x46, 0x48, 0x48, 0x2a, 0x48, 0x3b, 0x27, 0x48,
327 0x48, 0x4b, 0x33, 0x48, 0x22, 0x48, 0x48, 0x2e,
328 0x48, 0x19, 0x1d, 0x48, 0x1b, 0x4a, 0x48, 0x4b,
329 0x1f, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
330 0x48, 0x4b, 0x24, 0x48, 0x07, 0x48, 0x48, 0x36,
331 0x4b, 0x48, 0x48, 0x3e, 0x48, 0x30, 0x38, 0x48,
332 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x16, 0x48,
333 0x48, 0x12, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
334 0x47, 0x48, 0x48, 0x2f, 0x48, 0x3f, 0x4b, 0x48,
335 0x48, 0x06, 0x37, 0x48, 0x23, 0x48, 0x48, 0x2b,
336 0x48, 0x05, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x32,
337 0x26, 0x48, 0x48, 0x3a, 0x48, 0x34, 0x3c, 0x48,
338 0x48, 0x11, 0x15, 0x48, 0x13, 0x4a, 0x48, 0x4b,
339 0x17, 0x48, 0x4a, 0x4b, 0x48, 0x4b, 0x4b, 0x48,
340 0x49, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x1e, 0x48,
341 0x48, 0x1a, 0x4b, 0x48, 0x49, 0x48, 0x48, 0x4b,
342 0x48, 0x08, 0x0d, 0x48, 0x02, 0x48, 0x48, 0x49,
343 0x03, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x4b, 0x48,
344 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x10, 0x48,
345 0x48, 0x14, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
346 0x49, 0x48, 0x48, 0x49, 0x48, 0x4b, 0x18, 0x48,
347 0x48, 0x1c, 0x4b, 0x48, 0x4b, 0x48, 0x48, 0x4b,
348 0x4a, 0x0c, 0x09, 0x48, 0x0e, 0x48, 0x48, 0x4b,
349 0x0b, 0x48, 0x48, 0x4b, 0x48, 0x4b, 0x4b, 0x4a
350 };
351
352 /* cee_trap in entry.S encodes AFSR/UDBH/UDBL error status
353 * in the following format. The AFAR is left as is, with
354 * reserved bits cleared, and is a raw 40-bit physical
355 * address.
356 */
357 #define CE_STATUS_UDBH_UE (1UL << (43 + 9))
358 #define CE_STATUS_UDBH_CE (1UL << (43 + 8))
359 #define CE_STATUS_UDBH_ESYNDR (0xffUL << 43)
360 #define CE_STATUS_UDBH_SHIFT 43
361 #define CE_STATUS_UDBL_UE (1UL << (33 + 9))
362 #define CE_STATUS_UDBL_CE (1UL << (33 + 8))
363 #define CE_STATUS_UDBL_ESYNDR (0xffUL << 33)
364 #define CE_STATUS_UDBL_SHIFT 33
365 #define CE_STATUS_AFSR_MASK (0x1ffffffffUL)
366 #define CE_STATUS_AFSR_ME (1UL << 32)
367 #define CE_STATUS_AFSR_PRIV (1UL << 31)
368 #define CE_STATUS_AFSR_ISAP (1UL << 30)
369 #define CE_STATUS_AFSR_ETP (1UL << 29)
370 #define CE_STATUS_AFSR_IVUE (1UL << 28)
371 #define CE_STATUS_AFSR_TO (1UL << 27)
372 #define CE_STATUS_AFSR_BERR (1UL << 26)
373 #define CE_STATUS_AFSR_LDP (1UL << 25)
374 #define CE_STATUS_AFSR_CP (1UL << 24)
375 #define CE_STATUS_AFSR_WP (1UL << 23)
376 #define CE_STATUS_AFSR_EDP (1UL << 22)
377 #define CE_STATUS_AFSR_UE (1UL << 21)
378 #define CE_STATUS_AFSR_CE (1UL << 20)
379 #define CE_STATUS_AFSR_ETS (0xfUL << 16)
380 #define CE_STATUS_AFSR_ETS_SHIFT 16
381 #define CE_STATUS_AFSR_PSYND (0xffffUL << 0)
382 #define CE_STATUS_AFSR_PSYND_SHIFT 0
383
384 /* Layout of Ecache TAG Parity Syndrome of AFSR */
385 #define AFSR_ETSYNDROME_7_0 0x1UL /* E$-tag bus bits <7:0> */
386 #define AFSR_ETSYNDROME_15_8 0x2UL /* E$-tag bus bits <15:8> */
387 #define AFSR_ETSYNDROME_21_16 0x4UL /* E$-tag bus bits <21:16> */
388 #define AFSR_ETSYNDROME_24_22 0x8UL /* E$-tag bus bits <24:22> */
389
390 static char *syndrome_unknown = "<Unknown>";
391
392 asmlinkage void cee_log(unsigned long ce_status,
393 unsigned long afar,
394 struct pt_regs *regs)
395 {
396 char memmod_str[64];
397 char *p;
398 unsigned short scode, udb_reg;
399
400 printk(KERN_WARNING "CPU[%d]: Correctable ECC Error "
401 "AFSR[%lx] AFAR[%016lx] UDBL[%lx] UDBH[%lx]\n",
402 smp_processor_id(),
403 (ce_status & CE_STATUS_AFSR_MASK),
404 afar,
405 ((ce_status >> CE_STATUS_UDBL_SHIFT) & 0x3ffUL),
406 ((ce_status >> CE_STATUS_UDBH_SHIFT) & 0x3ffUL));
407
408 udb_reg = ((ce_status >> CE_STATUS_UDBL_SHIFT) & 0x3ffUL);
409 if (udb_reg & (1 << 8)) {
410 scode = ecc_syndrome_table[udb_reg & 0xff];
411 if (prom_getunumber(scode, afar,
412 memmod_str, sizeof(memmod_str)) == -1)
413 p = syndrome_unknown;
414 else
415 p = memmod_str;
416 printk(KERN_WARNING "CPU[%d]: UDBL Syndrome[%x] "
417 "Memory Module \"%s\"\n",
418 smp_processor_id(), scode, p);
419 }
420
421 udb_reg = ((ce_status >> CE_STATUS_UDBH_SHIFT) & 0x3ffUL);
422 if (udb_reg & (1 << 8)) {
423 scode = ecc_syndrome_table[udb_reg & 0xff];
424 if (prom_getunumber(scode, afar,
425 memmod_str, sizeof(memmod_str)) == -1)
426 p = syndrome_unknown;
427 else
428 p = memmod_str;
429 printk(KERN_WARNING "CPU[%d]: UDBH Syndrome[%x] "
430 "Memory Module \"%s\"\n",
431 smp_processor_id(), scode, p);
432 }
433 }
434
435 int cheetah_pcache_forced_on;
436
437 void cheetah_enable_pcache(void)
438 {
439 unsigned long dcr;
440
441 printk("CHEETAH: Enabling P-Cache on cpu %d.\n",
442 smp_processor_id());
443
444 __asm__ __volatile__("ldxa [%%g0] %1, %0"
445 : "=r" (dcr)
446 : "i" (ASI_DCU_CONTROL_REG));
447 dcr |= (DCU_PE | DCU_HPE | DCU_SPE | DCU_SL);
448 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
449 "membar #Sync"
450 : /* no outputs */
451 : "r" (dcr), "i" (ASI_DCU_CONTROL_REG));
452 }
453
454 /* Cheetah error trap handling. */
455 static unsigned long ecache_flush_physbase;
456 static unsigned long ecache_flush_linesize;
457 static unsigned long ecache_flush_size;
458
459 /* WARNING: The error trap handlers in assembly know the precise
460 * layout of the following structure.
461 *
462 * C-level handlers below use this information to log the error
463 * and then determine how to recover (if possible).
464 */
465 struct cheetah_err_info {
466 /*0x00*/u64 afsr;
467 /*0x08*/u64 afar;
468
469 /* D-cache state */
470 /*0x10*/u64 dcache_data[4]; /* The actual data */
471 /*0x30*/u64 dcache_index; /* D-cache index */
472 /*0x38*/u64 dcache_tag; /* D-cache tag/valid */
473 /*0x40*/u64 dcache_utag; /* D-cache microtag */
474 /*0x48*/u64 dcache_stag; /* D-cache snooptag */
475
476 /* I-cache state */
477 /*0x50*/u64 icache_data[8]; /* The actual insns + predecode */
478 /*0x90*/u64 icache_index; /* I-cache index */
479 /*0x98*/u64 icache_tag; /* I-cache phys tag */
480 /*0xa0*/u64 icache_utag; /* I-cache microtag */
481 /*0xa8*/u64 icache_stag; /* I-cache snooptag */
482 /*0xb0*/u64 icache_upper; /* I-cache upper-tag */
483 /*0xb8*/u64 icache_lower; /* I-cache lower-tag */
484
485 /* E-cache state */
486 /*0xc0*/u64 ecache_data[4]; /* 32 bytes from staging registers */
487 /*0xe0*/u64 ecache_index; /* E-cache index */
488 /*0xe8*/u64 ecache_tag; /* E-cache tag/state */
489
490 /*0xf0*/u64 __pad[32 - 30];
491 };
492 #define CHAFSR_INVALID ((u64)-1L)
493
494 /* This table is ordered in priority of errors and matches the
495 * AFAR overwrite policy as well.
496 */
497
498 struct afsr_error_table {
499 unsigned long mask;
500 const char *name;
501 };
502
503 static const char CHAFSR_PERR_msg[] =
504 "System interface protocol error";
505 static const char CHAFSR_IERR_msg[] =
506 "Internal processor error";
507 static const char CHAFSR_ISAP_msg[] =
508 "System request parity error on incoming addresss";
509 static const char CHAFSR_UCU_msg[] =
510 "Uncorrectable E-cache ECC error for ifetch/data";
511 static const char CHAFSR_UCC_msg[] =
512 "SW Correctable E-cache ECC error for ifetch/data";
513 static const char CHAFSR_UE_msg[] =
514 "Uncorrectable system bus data ECC error for read";
515 static const char CHAFSR_EDU_msg[] =
516 "Uncorrectable E-cache ECC error for stmerge/blkld";
517 static const char CHAFSR_EMU_msg[] =
518 "Uncorrectable system bus MTAG error";
519 static const char CHAFSR_WDU_msg[] =
520 "Uncorrectable E-cache ECC error for writeback";
521 static const char CHAFSR_CPU_msg[] =
522 "Uncorrectable ECC error for copyout";
523 static const char CHAFSR_CE_msg[] =
524 "HW corrected system bus data ECC error for read";
525 static const char CHAFSR_EDC_msg[] =
526 "HW corrected E-cache ECC error for stmerge/blkld";
527 static const char CHAFSR_EMC_msg[] =
528 "HW corrected system bus MTAG ECC error";
529 static const char CHAFSR_WDC_msg[] =
530 "HW corrected E-cache ECC error for writeback";
531 static const char CHAFSR_CPC_msg[] =
532 "HW corrected ECC error for copyout";
533 static const char CHAFSR_TO_msg[] =
534 "Unmapped error from system bus";
535 static const char CHAFSR_BERR_msg[] =
536 "Bus error response from system bus";
537 static const char CHAFSR_IVC_msg[] =
538 "HW corrected system bus data ECC error for ivec read";
539 static const char CHAFSR_IVU_msg[] =
540 "Uncorrectable system bus data ECC error for ivec read";
541 static struct afsr_error_table __cheetah_error_table[] = {
542 { CHAFSR_PERR, CHAFSR_PERR_msg },
543 { CHAFSR_IERR, CHAFSR_IERR_msg },
544 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
545 { CHAFSR_UCU, CHAFSR_UCU_msg },
546 { CHAFSR_UCC, CHAFSR_UCC_msg },
547 { CHAFSR_UE, CHAFSR_UE_msg },
548 { CHAFSR_EDU, CHAFSR_EDU_msg },
549 { CHAFSR_EMU, CHAFSR_EMU_msg },
550 { CHAFSR_WDU, CHAFSR_WDU_msg },
551 { CHAFSR_CPU, CHAFSR_CPU_msg },
552 { CHAFSR_CE, CHAFSR_CE_msg },
553 { CHAFSR_EDC, CHAFSR_EDC_msg },
554 { CHAFSR_EMC, CHAFSR_EMC_msg },
555 { CHAFSR_WDC, CHAFSR_WDC_msg },
556 { CHAFSR_CPC, CHAFSR_CPC_msg },
557 { CHAFSR_TO, CHAFSR_TO_msg },
558 { CHAFSR_BERR, CHAFSR_BERR_msg },
559 /* These two do not update the AFAR. */
560 { CHAFSR_IVC, CHAFSR_IVC_msg },
561 { CHAFSR_IVU, CHAFSR_IVU_msg },
562 { 0, NULL },
563 };
564 static const char CHPAFSR_DTO_msg[] =
565 "System bus unmapped error for prefetch/storequeue-read";
566 static const char CHPAFSR_DBERR_msg[] =
567 "System bus error for prefetch/storequeue-read";
568 static const char CHPAFSR_THCE_msg[] =
569 "Hardware corrected E-cache Tag ECC error";
570 static const char CHPAFSR_TSCE_msg[] =
571 "SW handled correctable E-cache Tag ECC error";
572 static const char CHPAFSR_TUE_msg[] =
573 "Uncorrectable E-cache Tag ECC error";
574 static const char CHPAFSR_DUE_msg[] =
575 "System bus uncorrectable data ECC error due to prefetch/store-fill";
576 static struct afsr_error_table __cheetah_plus_error_table[] = {
577 { CHAFSR_PERR, CHAFSR_PERR_msg },
578 { CHAFSR_IERR, CHAFSR_IERR_msg },
579 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
580 { CHAFSR_UCU, CHAFSR_UCU_msg },
581 { CHAFSR_UCC, CHAFSR_UCC_msg },
582 { CHAFSR_UE, CHAFSR_UE_msg },
583 { CHAFSR_EDU, CHAFSR_EDU_msg },
584 { CHAFSR_EMU, CHAFSR_EMU_msg },
585 { CHAFSR_WDU, CHAFSR_WDU_msg },
586 { CHAFSR_CPU, CHAFSR_CPU_msg },
587 { CHAFSR_CE, CHAFSR_CE_msg },
588 { CHAFSR_EDC, CHAFSR_EDC_msg },
589 { CHAFSR_EMC, CHAFSR_EMC_msg },
590 { CHAFSR_WDC, CHAFSR_WDC_msg },
591 { CHAFSR_CPC, CHAFSR_CPC_msg },
592 { CHAFSR_TO, CHAFSR_TO_msg },
593 { CHAFSR_BERR, CHAFSR_BERR_msg },
594 { CHPAFSR_DTO, CHPAFSR_DTO_msg },
595 { CHPAFSR_DBERR, CHPAFSR_DBERR_msg },
596 { CHPAFSR_THCE, CHPAFSR_THCE_msg },
597 { CHPAFSR_TSCE, CHPAFSR_TSCE_msg },
598 { CHPAFSR_TUE, CHPAFSR_TUE_msg },
599 { CHPAFSR_DUE, CHPAFSR_DUE_msg },
600 /* These two do not update the AFAR. */
601 { CHAFSR_IVC, CHAFSR_IVC_msg },
602 { CHAFSR_IVU, CHAFSR_IVU_msg },
603 { 0, NULL },
604 };
605 static const char JPAFSR_JETO_msg[] =
606 "System interface protocol error, hw timeout caused";
607 static const char JPAFSR_SCE_msg[] =
608 "Parity error on system snoop results";
609 static const char JPAFSR_JEIC_msg[] =
610 "System interface protocol error, illegal command detected";
611 static const char JPAFSR_JEIT_msg[] =
612 "System interface protocol error, illegal ADTYPE detected";
613 static const char JPAFSR_OM_msg[] =
614 "Out of range memory error has occurred";
615 static const char JPAFSR_ETP_msg[] =
616 "Parity error on L2 cache tag SRAM";
617 static const char JPAFSR_UMS_msg[] =
618 "Error due to unsupported store";
619 static const char JPAFSR_RUE_msg[] =
620 "Uncorrectable ECC error from remote cache/memory";
621 static const char JPAFSR_RCE_msg[] =
622 "Correctable ECC error from remote cache/memory";
623 static const char JPAFSR_BP_msg[] =
624 "JBUS parity error on returned read data";
625 static const char JPAFSR_WBP_msg[] =
626 "JBUS parity error on data for writeback or block store";
627 static const char JPAFSR_FRC_msg[] =
628 "Foreign read to DRAM incurring correctable ECC error";
629 static const char JPAFSR_FRU_msg[] =
630 "Foreign read to DRAM incurring uncorrectable ECC error";
631 static struct afsr_error_table __jalapeno_error_table[] = {
632 { JPAFSR_JETO, JPAFSR_JETO_msg },
633 { JPAFSR_SCE, JPAFSR_SCE_msg },
634 { JPAFSR_JEIC, JPAFSR_JEIC_msg },
635 { JPAFSR_JEIT, JPAFSR_JEIT_msg },
636 { CHAFSR_PERR, CHAFSR_PERR_msg },
637 { CHAFSR_IERR, CHAFSR_IERR_msg },
638 { CHAFSR_ISAP, CHAFSR_ISAP_msg },
639 { CHAFSR_UCU, CHAFSR_UCU_msg },
640 { CHAFSR_UCC, CHAFSR_UCC_msg },
641 { CHAFSR_UE, CHAFSR_UE_msg },
642 { CHAFSR_EDU, CHAFSR_EDU_msg },
643 { JPAFSR_OM, JPAFSR_OM_msg },
644 { CHAFSR_WDU, CHAFSR_WDU_msg },
645 { CHAFSR_CPU, CHAFSR_CPU_msg },
646 { CHAFSR_CE, CHAFSR_CE_msg },
647 { CHAFSR_EDC, CHAFSR_EDC_msg },
648 { JPAFSR_ETP, JPAFSR_ETP_msg },
649 { CHAFSR_WDC, CHAFSR_WDC_msg },
650 { CHAFSR_CPC, CHAFSR_CPC_msg },
651 { CHAFSR_TO, CHAFSR_TO_msg },
652 { CHAFSR_BERR, CHAFSR_BERR_msg },
653 { JPAFSR_UMS, JPAFSR_UMS_msg },
654 { JPAFSR_RUE, JPAFSR_RUE_msg },
655 { JPAFSR_RCE, JPAFSR_RCE_msg },
656 { JPAFSR_BP, JPAFSR_BP_msg },
657 { JPAFSR_WBP, JPAFSR_WBP_msg },
658 { JPAFSR_FRC, JPAFSR_FRC_msg },
659 { JPAFSR_FRU, JPAFSR_FRU_msg },
660 /* These two do not update the AFAR. */
661 { CHAFSR_IVU, CHAFSR_IVU_msg },
662 { 0, NULL },
663 };
664 static struct afsr_error_table *cheetah_error_table;
665 static unsigned long cheetah_afsr_errors;
666
667 /* This is allocated at boot time based upon the largest hardware
668 * cpu ID in the system. We allocate two entries per cpu, one for
669 * TL==0 logging and one for TL >= 1 logging.
670 */
671 struct cheetah_err_info *cheetah_error_log;
672
673 static __inline__ struct cheetah_err_info *cheetah_get_error_log(unsigned long afsr)
674 {
675 struct cheetah_err_info *p;
676 int cpu = smp_processor_id();
677
678 if (!cheetah_error_log)
679 return NULL;
680
681 p = cheetah_error_log + (cpu * 2);
682 if ((afsr & CHAFSR_TL1) != 0UL)
683 p++;
684
685 return p;
686 }
687
688 extern unsigned int tl0_icpe[], tl1_icpe[];
689 extern unsigned int tl0_dcpe[], tl1_dcpe[];
690 extern unsigned int tl0_fecc[], tl1_fecc[];
691 extern unsigned int tl0_cee[], tl1_cee[];
692 extern unsigned int tl0_iae[], tl1_iae[];
693 extern unsigned int tl0_dae[], tl1_dae[];
694 extern unsigned int cheetah_plus_icpe_trap_vector[], cheetah_plus_icpe_trap_vector_tl1[];
695 extern unsigned int cheetah_plus_dcpe_trap_vector[], cheetah_plus_dcpe_trap_vector_tl1[];
696 extern unsigned int cheetah_fecc_trap_vector[], cheetah_fecc_trap_vector_tl1[];
697 extern unsigned int cheetah_cee_trap_vector[], cheetah_cee_trap_vector_tl1[];
698 extern unsigned int cheetah_deferred_trap_vector[], cheetah_deferred_trap_vector_tl1[];
699
700 void __init cheetah_ecache_flush_init(void)
701 {
702 unsigned long largest_size, smallest_linesize, order, ver;
703 int node, i, instance;
704
705 /* Scan all cpu device tree nodes, note two values:
706 * 1) largest E-cache size
707 * 2) smallest E-cache line size
708 */
709 largest_size = 0UL;
710 smallest_linesize = ~0UL;
711
712 instance = 0;
713 while (!cpu_find_by_instance(instance, &node, NULL)) {
714 unsigned long val;
715
716 val = prom_getintdefault(node, "ecache-size",
717 (2 * 1024 * 1024));
718 if (val > largest_size)
719 largest_size = val;
720 val = prom_getintdefault(node, "ecache-line-size", 64);
721 if (val < smallest_linesize)
722 smallest_linesize = val;
723 instance++;
724 }
725
726 if (largest_size == 0UL || smallest_linesize == ~0UL) {
727 prom_printf("cheetah_ecache_flush_init: Cannot probe cpu E-cache "
728 "parameters.\n");
729 prom_halt();
730 }
731
732 ecache_flush_size = (2 * largest_size);
733 ecache_flush_linesize = smallest_linesize;
734
735 /* Discover a physically contiguous chunk of physical
736 * memory in 'sp_banks' of size ecache_flush_size calculated
737 * above. Store the physical base of this area at
738 * ecache_flush_physbase.
739 */
740 for (node = 0; ; node++) {
741 if (sp_banks[node].num_bytes == 0)
742 break;
743 if (sp_banks[node].num_bytes >= ecache_flush_size) {
744 ecache_flush_physbase = sp_banks[node].base_addr;
745 break;
746 }
747 }
748
749 /* Note: Zero would be a valid value of ecache_flush_physbase so
750 * don't use that as the success test. :-)
751 */
752 if (sp_banks[node].num_bytes == 0) {
753 prom_printf("cheetah_ecache_flush_init: Cannot find %d byte "
754 "contiguous physical memory.\n", ecache_flush_size);
755 prom_halt();
756 }
757
758 /* Now allocate error trap reporting scoreboard. */
759 node = NR_CPUS * (2 * sizeof(struct cheetah_err_info));
760 for (order = 0; order < MAX_ORDER; order++) {
761 if ((PAGE_SIZE << order) >= node)
762 break;
763 }
764 cheetah_error_log = (struct cheetah_err_info *)
765 __get_free_pages(GFP_KERNEL, order);
766 if (!cheetah_error_log) {
767 prom_printf("cheetah_ecache_flush_init: Failed to allocate "
768 "error logging scoreboard (%d bytes).\n", node);
769 prom_halt();
770 }
771 memset(cheetah_error_log, 0, PAGE_SIZE << order);
772
773 /* Mark all AFSRs as invalid so that the trap handler will
774 * log new new information there.
775 */
776 for (i = 0; i < 2 * NR_CPUS; i++)
777 cheetah_error_log[i].afsr = CHAFSR_INVALID;
778
779 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
780 if ((ver >> 32) == 0x003e0016) {
781 cheetah_error_table = &__jalapeno_error_table[0];
782 cheetah_afsr_errors = JPAFSR_ERRORS;
783 } else if ((ver >> 32) == 0x003e0015) {
784 cheetah_error_table = &__cheetah_plus_error_table[0];
785 cheetah_afsr_errors = CHPAFSR_ERRORS;
786 } else {
787 cheetah_error_table = &__cheetah_error_table[0];
788 cheetah_afsr_errors = CHAFSR_ERRORS;
789 }
790
791 /* Now patch trap tables. */
792 memcpy(tl0_fecc, cheetah_fecc_trap_vector, (8 * 4));
793 memcpy(tl1_fecc, cheetah_fecc_trap_vector_tl1, (8 * 4));
794 memcpy(tl0_cee, cheetah_cee_trap_vector, (8 * 4));
795 memcpy(tl1_cee, cheetah_cee_trap_vector_tl1, (8 * 4));
796 memcpy(tl0_iae, cheetah_deferred_trap_vector, (8 * 4));
797 memcpy(tl1_iae, cheetah_deferred_trap_vector_tl1, (8 * 4));
798 memcpy(tl0_dae, cheetah_deferred_trap_vector, (8 * 4));
799 memcpy(tl1_dae, cheetah_deferred_trap_vector_tl1, (8 * 4));
800 if (tlb_type == cheetah_plus) {
801 memcpy(tl0_dcpe, cheetah_plus_dcpe_trap_vector, (8 * 4));
802 memcpy(tl1_dcpe, cheetah_plus_dcpe_trap_vector_tl1, (8 * 4));
803 memcpy(tl0_icpe, cheetah_plus_icpe_trap_vector, (8 * 4));
804 memcpy(tl1_icpe, cheetah_plus_icpe_trap_vector_tl1, (8 * 4));
805 }
806 flushi(PAGE_OFFSET);
807 }
808
809 static void cheetah_flush_ecache(void)
810 {
811 unsigned long flush_base = ecache_flush_physbase;
812 unsigned long flush_linesize = ecache_flush_linesize;
813 unsigned long flush_size = ecache_flush_size;
814
815 __asm__ __volatile__("1: subcc %0, %4, %0\n\t"
816 " bne,pt %%xcc, 1b\n\t"
817 " ldxa [%2 + %0] %3, %%g0\n\t"
818 : "=&r" (flush_size)
819 : "0" (flush_size), "r" (flush_base),
820 "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
821 }
822
823 static void cheetah_flush_ecache_line(unsigned long physaddr)
824 {
825 unsigned long alias;
826
827 physaddr &= ~(8UL - 1UL);
828 physaddr = (ecache_flush_physbase +
829 (physaddr & ((ecache_flush_size>>1UL) - 1UL)));
830 alias = physaddr + (ecache_flush_size >> 1UL);
831 __asm__ __volatile__("ldxa [%0] %2, %%g0\n\t"
832 "ldxa [%1] %2, %%g0\n\t"
833 "membar #Sync"
834 : /* no outputs */
835 : "r" (physaddr), "r" (alias),
836 "i" (ASI_PHYS_USE_EC));
837 }
838
839 /* Unfortunately, the diagnostic access to the I-cache tags we need to
840 * use to clear the thing interferes with I-cache coherency transactions.
841 *
842 * So we must only flush the I-cache when it is disabled.
843 */
844 static void __cheetah_flush_icache(void)
845 {
846 unsigned long i;
847
848 /* Clear the valid bits in all the tags. */
849 for (i = 0; i < (1 << 15); i += (1 << 5)) {
850 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
851 "membar #Sync"
852 : /* no outputs */
853 : "r" (i | (2 << 3)), "i" (ASI_IC_TAG));
854 }
855 }
856
857 static void cheetah_flush_icache(void)
858 {
859 unsigned long dcu_save;
860
861 /* Save current DCU, disable I-cache. */
862 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
863 "or %0, %2, %%g1\n\t"
864 "stxa %%g1, [%%g0] %1\n\t"
865 "membar #Sync"
866 : "=r" (dcu_save)
867 : "i" (ASI_DCU_CONTROL_REG), "i" (DCU_IC)
868 : "g1");
869
870 __cheetah_flush_icache();
871
872 /* Restore DCU register */
873 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
874 "membar #Sync"
875 : /* no outputs */
876 : "r" (dcu_save), "i" (ASI_DCU_CONTROL_REG));
877 }
878
879 static void cheetah_flush_dcache(void)
880 {
881 unsigned long i;
882
883 for (i = 0; i < (1 << 16); i += (1 << 5)) {
884 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
885 "membar #Sync"
886 : /* no outputs */
887 : "r" (i), "i" (ASI_DCACHE_TAG));
888 }
889 }
890
891 /* In order to make the even parity correct we must do two things.
892 * First, we clear DC_data_parity and set DC_utag to an appropriate value.
893 * Next, we clear out all 32-bytes of data for that line. Data of
894 * all-zero + tag parity value of zero == correct parity.
895 */
896 static void cheetah_plus_zap_dcache_parity(void)
897 {
898 unsigned long i;
899
900 for (i = 0; i < (1 << 16); i += (1 << 5)) {
901 unsigned long tag = (i >> 14);
902 unsigned long j;
903
904 __asm__ __volatile__("membar #Sync\n\t"
905 "stxa %0, [%1] %2\n\t"
906 "membar #Sync"
907 : /* no outputs */
908 : "r" (tag), "r" (i),
909 "i" (ASI_DCACHE_UTAG));
910 for (j = i; j < i + (1 << 5); j += (1 << 3))
911 __asm__ __volatile__("membar #Sync\n\t"
912 "stxa %%g0, [%0] %1\n\t"
913 "membar #Sync"
914 : /* no outputs */
915 : "r" (j), "i" (ASI_DCACHE_DATA));
916 }
917 }
918
919 /* Conversion tables used to frob Cheetah AFSR syndrome values into
920 * something palatable to the memory controller driver get_unumber
921 * routine.
922 */
923 #define MT0 137
924 #define MT1 138
925 #define MT2 139
926 #define NONE 254
927 #define MTC0 140
928 #define MTC1 141
929 #define MTC2 142
930 #define MTC3 143
931 #define C0 128
932 #define C1 129
933 #define C2 130
934 #define C3 131
935 #define C4 132
936 #define C5 133
937 #define C6 134
938 #define C7 135
939 #define C8 136
940 #define M2 144
941 #define M3 145
942 #define M4 146
943 #define M 147
944 static unsigned char cheetah_ecc_syntab[] = {
945 /*00*/NONE, C0, C1, M2, C2, M2, M3, 47, C3, M2, M2, 53, M2, 41, 29, M,
946 /*01*/C4, M, M, 50, M2, 38, 25, M2, M2, 33, 24, M2, 11, M, M2, 16,
947 /*02*/C5, M, M, 46, M2, 37, 19, M2, M, 31, 32, M, 7, M2, M2, 10,
948 /*03*/M2, 40, 13, M2, 59, M, M2, 66, M, M2, M2, 0, M2, 67, 71, M,
949 /*04*/C6, M, M, 43, M, 36, 18, M, M2, 49, 15, M, 63, M2, M2, 6,
950 /*05*/M2, 44, 28, M2, M, M2, M2, 52, 68, M2, M2, 62, M2, M3, M3, M4,
951 /*06*/M2, 26, 106, M2, 64, M, M2, 2, 120, M, M2, M3, M, M3, M3, M4,
952 /*07*/116, M2, M2, M3, M2, M3, M, M4, M2, 58, 54, M2, M, M4, M4, M3,
953 /*08*/C7, M2, M, 42, M, 35, 17, M2, M, 45, 14, M2, 21, M2, M2, 5,
954 /*09*/M, 27, M, M, 99, M, M, 3, 114, M2, M2, 20, M2, M3, M3, M,
955 /*0a*/M2, 23, 113, M2, 112, M2, M, 51, 95, M, M2, M3, M2, M3, M3, M2,
956 /*0b*/103, M, M2, M3, M2, M3, M3, M4, M2, 48, M, M, 73, M2, M, M3,
957 /*0c*/M2, 22, 110, M2, 109, M2, M, 9, 108, M2, M, M3, M2, M3, M3, M,
958 /*0d*/102, M2, M, M, M2, M3, M3, M, M2, M3, M3, M2, M, M4, M, M3,
959 /*0e*/98, M, M2, M3, M2, M, M3, M4, M2, M3, M3, M4, M3, M, M, M,
960 /*0f*/M2, M3, M3, M, M3, M, M, M, 56, M4, M, M3, M4, M, M, M,
961 /*10*/C8, M, M2, 39, M, 34, 105, M2, M, 30, 104, M, 101, M, M, 4,
962 /*11*/M, M, 100, M, 83, M, M2, 12, 87, M, M, 57, M2, M, M3, M,
963 /*12*/M2, 97, 82, M2, 78, M2, M2, 1, 96, M, M, M, M, M, M3, M2,
964 /*13*/94, M, M2, M3, M2, M, M3, M, M2, M, 79, M, 69, M, M4, M,
965 /*14*/M2, 93, 92, M, 91, M, M2, 8, 90, M2, M2, M, M, M, M, M4,
966 /*15*/89, M, M, M3, M2, M3, M3, M, M, M, M3, M2, M3, M2, M, M3,
967 /*16*/86, M, M2, M3, M2, M, M3, M, M2, M, M3, M, M3, M, M, M3,
968 /*17*/M, M, M3, M2, M3, M2, M4, M, 60, M, M2, M3, M4, M, M, M2,
969 /*18*/M2, 88, 85, M2, 84, M, M2, 55, 81, M2, M2, M3, M2, M3, M3, M4,
970 /*19*/77, M, M, M, M2, M3, M, M, M2, M3, M3, M4, M3, M2, M, M,
971 /*1a*/74, M, M2, M3, M, M, M3, M, M, M, M3, M, M3, M, M4, M3,
972 /*1b*/M2, 70, 107, M4, 65, M2, M2, M, 127, M, M, M, M2, M3, M3, M,
973 /*1c*/80, M2, M2, 72, M, 119, 118, M, M2, 126, 76, M, 125, M, M4, M3,
974 /*1d*/M2, 115, 124, M, 75, M, M, M3, 61, M, M4, M, M4, M, M, M,
975 /*1e*/M, 123, 122, M4, 121, M4, M, M3, 117, M2, M2, M3, M4, M3, M, M,
976 /*1f*/111, M, M, M, M4, M3, M3, M, M, M, M3, M, M3, M2, M, M
977 };
978 static unsigned char cheetah_mtag_syntab[] = {
979 NONE, MTC0,
980 MTC1, NONE,
981 MTC2, NONE,
982 NONE, MT0,
983 MTC3, NONE,
984 NONE, MT1,
985 NONE, MT2,
986 NONE, NONE
987 };
988
989 /* Return the highest priority error conditon mentioned. */
990 static __inline__ unsigned long cheetah_get_hipri(unsigned long afsr)
991 {
992 unsigned long tmp = 0;
993 int i;
994
995 for (i = 0; cheetah_error_table[i].mask; i++) {
996 if ((tmp = (afsr & cheetah_error_table[i].mask)) != 0UL)
997 return tmp;
998 }
999 return tmp;
1000 }
1001
1002 static const char *cheetah_get_string(unsigned long bit)
1003 {
1004 int i;
1005
1006 for (i = 0; cheetah_error_table[i].mask; i++) {
1007 if ((bit & cheetah_error_table[i].mask) != 0UL)
1008 return cheetah_error_table[i].name;
1009 }
1010 return "???";
1011 }
1012
1013 extern int chmc_getunumber(int, unsigned long, char *, int);
1014
1015 static void cheetah_log_errors(struct pt_regs *regs, struct cheetah_err_info *info,
1016 unsigned long afsr, unsigned long afar, int recoverable)
1017 {
1018 unsigned long hipri;
1019 char unum[256];
1020
1021 printk("%s" "ERROR(%d): Cheetah error trap taken afsr[%016lx] afar[%016lx] TL1(%d)\n",
1022 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1023 afsr, afar,
1024 (afsr & CHAFSR_TL1) ? 1 : 0);
1025 printk("%s" "ERROR(%d): TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1026 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1027 regs->tpc, regs->tnpc, regs->tstate);
1028 printk("%s" "ERROR(%d): M_SYND(%lx), E_SYND(%lx)%s%s\n",
1029 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1030 (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT,
1031 (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT,
1032 (afsr & CHAFSR_ME) ? ", Multiple Errors" : "",
1033 (afsr & CHAFSR_PRIV) ? ", Privileged" : "");
1034 hipri = cheetah_get_hipri(afsr);
1035 printk("%s" "ERROR(%d): Highest priority error (%016lx) \"%s\"\n",
1036 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1037 hipri, cheetah_get_string(hipri));
1038
1039 /* Try to get unumber if relevant. */
1040 #define ESYND_ERRORS (CHAFSR_IVC | CHAFSR_IVU | \
1041 CHAFSR_CPC | CHAFSR_CPU | \
1042 CHAFSR_UE | CHAFSR_CE | \
1043 CHAFSR_EDC | CHAFSR_EDU | \
1044 CHAFSR_UCC | CHAFSR_UCU | \
1045 CHAFSR_WDU | CHAFSR_WDC)
1046 #define MSYND_ERRORS (CHAFSR_EMC | CHAFSR_EMU)
1047 if (afsr & ESYND_ERRORS) {
1048 int syndrome;
1049 int ret;
1050
1051 syndrome = (afsr & CHAFSR_E_SYNDROME) >> CHAFSR_E_SYNDROME_SHIFT;
1052 syndrome = cheetah_ecc_syntab[syndrome];
1053 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1054 if (ret != -1)
1055 printk("%s" "ERROR(%d): AFAR E-syndrome [%s]\n",
1056 (recoverable ? KERN_WARNING : KERN_CRIT),
1057 smp_processor_id(), unum);
1058 } else if (afsr & MSYND_ERRORS) {
1059 int syndrome;
1060 int ret;
1061
1062 syndrome = (afsr & CHAFSR_M_SYNDROME) >> CHAFSR_M_SYNDROME_SHIFT;
1063 syndrome = cheetah_mtag_syntab[syndrome];
1064 ret = chmc_getunumber(syndrome, afar, unum, sizeof(unum));
1065 if (ret != -1)
1066 printk("%s" "ERROR(%d): AFAR M-syndrome [%s]\n",
1067 (recoverable ? KERN_WARNING : KERN_CRIT),
1068 smp_processor_id(), unum);
1069 }
1070
1071 /* Now dump the cache snapshots. */
1072 printk("%s" "ERROR(%d): D-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx]\n",
1073 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1074 (int) info->dcache_index,
1075 info->dcache_tag,
1076 info->dcache_utag,
1077 info->dcache_stag);
1078 printk("%s" "ERROR(%d): D-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1079 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1080 info->dcache_data[0],
1081 info->dcache_data[1],
1082 info->dcache_data[2],
1083 info->dcache_data[3]);
1084 printk("%s" "ERROR(%d): I-cache idx[%x] tag[%016lx] utag[%016lx] stag[%016lx] "
1085 "u[%016lx] l[%016lx]\n",
1086 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1087 (int) info->icache_index,
1088 info->icache_tag,
1089 info->icache_utag,
1090 info->icache_stag,
1091 info->icache_upper,
1092 info->icache_lower);
1093 printk("%s" "ERROR(%d): I-cache INSN0[%016lx] INSN1[%016lx] INSN2[%016lx] INSN3[%016lx]\n",
1094 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1095 info->icache_data[0],
1096 info->icache_data[1],
1097 info->icache_data[2],
1098 info->icache_data[3]);
1099 printk("%s" "ERROR(%d): I-cache INSN4[%016lx] INSN5[%016lx] INSN6[%016lx] INSN7[%016lx]\n",
1100 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1101 info->icache_data[4],
1102 info->icache_data[5],
1103 info->icache_data[6],
1104 info->icache_data[7]);
1105 printk("%s" "ERROR(%d): E-cache idx[%x] tag[%016lx]\n",
1106 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1107 (int) info->ecache_index, info->ecache_tag);
1108 printk("%s" "ERROR(%d): E-cache data0[%016lx] data1[%016lx] data2[%016lx] data3[%016lx]\n",
1109 (recoverable ? KERN_WARNING : KERN_CRIT), smp_processor_id(),
1110 info->ecache_data[0],
1111 info->ecache_data[1],
1112 info->ecache_data[2],
1113 info->ecache_data[3]);
1114
1115 afsr = (afsr & ~hipri) & cheetah_afsr_errors;
1116 while (afsr != 0UL) {
1117 unsigned long bit = cheetah_get_hipri(afsr);
1118
1119 printk("%s" "ERROR: Multiple-error (%016lx) \"%s\"\n",
1120 (recoverable ? KERN_WARNING : KERN_CRIT),
1121 bit, cheetah_get_string(bit));
1122
1123 afsr &= ~bit;
1124 }
1125
1126 if (!recoverable)
1127 printk(KERN_CRIT "ERROR: This condition is not recoverable.\n");
1128 }
1129
1130 static int cheetah_recheck_errors(struct cheetah_err_info *logp)
1131 {
1132 unsigned long afsr, afar;
1133 int ret = 0;
1134
1135 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1136 : "=r" (afsr)
1137 : "i" (ASI_AFSR));
1138 if ((afsr & cheetah_afsr_errors) != 0) {
1139 if (logp != NULL) {
1140 __asm__ __volatile__("ldxa [%%g0] %1, %0\n\t"
1141 : "=r" (afar)
1142 : "i" (ASI_AFAR));
1143 logp->afsr = afsr;
1144 logp->afar = afar;
1145 }
1146 ret = 1;
1147 }
1148 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1149 "membar #Sync\n\t"
1150 : : "r" (afsr), "i" (ASI_AFSR));
1151
1152 return ret;
1153 }
1154
1155 void cheetah_fecc_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1156 {
1157 struct cheetah_err_info local_snapshot, *p;
1158 int recoverable;
1159
1160 /* Flush E-cache */
1161 cheetah_flush_ecache();
1162
1163 p = cheetah_get_error_log(afsr);
1164 if (!p) {
1165 prom_printf("ERROR: Early Fast-ECC error afsr[%016lx] afar[%016lx]\n",
1166 afsr, afar);
1167 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1168 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1169 prom_halt();
1170 }
1171
1172 /* Grab snapshot of logged error. */
1173 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1174
1175 /* If the current trap snapshot does not match what the
1176 * trap handler passed along into our args, big trouble.
1177 * In such a case, mark the local copy as invalid.
1178 *
1179 * Else, it matches and we mark the afsr in the non-local
1180 * copy as invalid so we may log new error traps there.
1181 */
1182 if (p->afsr != afsr || p->afar != afar)
1183 local_snapshot.afsr = CHAFSR_INVALID;
1184 else
1185 p->afsr = CHAFSR_INVALID;
1186
1187 cheetah_flush_icache();
1188 cheetah_flush_dcache();
1189
1190 /* Re-enable I-cache/D-cache */
1191 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1192 "or %%g1, %1, %%g1\n\t"
1193 "stxa %%g1, [%%g0] %0\n\t"
1194 "membar #Sync"
1195 : /* no outputs */
1196 : "i" (ASI_DCU_CONTROL_REG),
1197 "i" (DCU_DC | DCU_IC)
1198 : "g1");
1199
1200 /* Re-enable error reporting */
1201 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1202 "or %%g1, %1, %%g1\n\t"
1203 "stxa %%g1, [%%g0] %0\n\t"
1204 "membar #Sync"
1205 : /* no outputs */
1206 : "i" (ASI_ESTATE_ERROR_EN),
1207 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1208 : "g1");
1209
1210 /* Decide if we can continue after handling this trap and
1211 * logging the error.
1212 */
1213 recoverable = 1;
1214 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1215 recoverable = 0;
1216
1217 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1218 * error was logged while we had error reporting traps disabled.
1219 */
1220 if (cheetah_recheck_errors(&local_snapshot)) {
1221 unsigned long new_afsr = local_snapshot.afsr;
1222
1223 /* If we got a new asynchronous error, die... */
1224 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1225 CHAFSR_WDU | CHAFSR_CPU |
1226 CHAFSR_IVU | CHAFSR_UE |
1227 CHAFSR_BERR | CHAFSR_TO))
1228 recoverable = 0;
1229 }
1230
1231 /* Log errors. */
1232 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1233
1234 if (!recoverable)
1235 panic("Irrecoverable Fast-ECC error trap.\n");
1236
1237 /* Flush E-cache to kick the error trap handlers out. */
1238 cheetah_flush_ecache();
1239 }
1240
1241 /* Try to fix a correctable error by pushing the line out from
1242 * the E-cache. Recheck error reporting registers to see if the
1243 * problem is intermittent.
1244 */
1245 static int cheetah_fix_ce(unsigned long physaddr)
1246 {
1247 unsigned long orig_estate;
1248 unsigned long alias1, alias2;
1249 int ret;
1250
1251 /* Make sure correctable error traps are disabled. */
1252 __asm__ __volatile__("ldxa [%%g0] %2, %0\n\t"
1253 "andn %0, %1, %%g1\n\t"
1254 "stxa %%g1, [%%g0] %2\n\t"
1255 "membar #Sync"
1256 : "=&r" (orig_estate)
1257 : "i" (ESTATE_ERROR_CEEN),
1258 "i" (ASI_ESTATE_ERROR_EN)
1259 : "g1");
1260
1261 /* We calculate alias addresses that will force the
1262 * cache line in question out of the E-cache. Then
1263 * we bring it back in with an atomic instruction so
1264 * that we get it in some modified/exclusive state,
1265 * then we displace it again to try and get proper ECC
1266 * pushed back into the system.
1267 */
1268 physaddr &= ~(8UL - 1UL);
1269 alias1 = (ecache_flush_physbase +
1270 (physaddr & ((ecache_flush_size >> 1) - 1)));
1271 alias2 = alias1 + (ecache_flush_size >> 1);
1272 __asm__ __volatile__("ldxa [%0] %3, %%g0\n\t"
1273 "ldxa [%1] %3, %%g0\n\t"
1274 "casxa [%2] %3, %%g0, %%g0\n\t"
1275 "membar #StoreLoad | #StoreStore\n\t"
1276 "ldxa [%0] %3, %%g0\n\t"
1277 "ldxa [%1] %3, %%g0\n\t"
1278 "membar #Sync"
1279 : /* no outputs */
1280 : "r" (alias1), "r" (alias2),
1281 "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1282
1283 /* Did that trigger another error? */
1284 if (cheetah_recheck_errors(NULL)) {
1285 /* Try one more time. */
1286 __asm__ __volatile__("ldxa [%0] %1, %%g0\n\t"
1287 "membar #Sync"
1288 : : "r" (physaddr), "i" (ASI_PHYS_USE_EC));
1289 if (cheetah_recheck_errors(NULL))
1290 ret = 2;
1291 else
1292 ret = 1;
1293 } else {
1294 /* No new error, intermittent problem. */
1295 ret = 0;
1296 }
1297
1298 /* Restore error enables. */
1299 __asm__ __volatile__("stxa %0, [%%g0] %1\n\t"
1300 "membar #Sync"
1301 : : "r" (orig_estate), "i" (ASI_ESTATE_ERROR_EN));
1302
1303 return ret;
1304 }
1305
1306 /* Return non-zero if PADDR is a valid physical memory address. */
1307 static int cheetah_check_main_memory(unsigned long paddr)
1308 {
1309 int i;
1310
1311 for (i = 0; ; i++) {
1312 if (sp_banks[i].num_bytes == 0)
1313 break;
1314 if (paddr >= sp_banks[i].base_addr &&
1315 paddr < (sp_banks[i].base_addr + sp_banks[i].num_bytes))
1316 return 1;
1317 }
1318 return 0;
1319 }
1320
1321 void cheetah_cee_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1322 {
1323 struct cheetah_err_info local_snapshot, *p;
1324 int recoverable, is_memory;
1325
1326 p = cheetah_get_error_log(afsr);
1327 if (!p) {
1328 prom_printf("ERROR: Early CEE error afsr[%016lx] afar[%016lx]\n",
1329 afsr, afar);
1330 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1331 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1332 prom_halt();
1333 }
1334
1335 /* Grab snapshot of logged error. */
1336 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1337
1338 /* If the current trap snapshot does not match what the
1339 * trap handler passed along into our args, big trouble.
1340 * In such a case, mark the local copy as invalid.
1341 *
1342 * Else, it matches and we mark the afsr in the non-local
1343 * copy as invalid so we may log new error traps there.
1344 */
1345 if (p->afsr != afsr || p->afar != afar)
1346 local_snapshot.afsr = CHAFSR_INVALID;
1347 else
1348 p->afsr = CHAFSR_INVALID;
1349
1350 is_memory = cheetah_check_main_memory(afar);
1351
1352 if (is_memory && (afsr & CHAFSR_CE) != 0UL) {
1353 /* XXX Might want to log the results of this operation
1354 * XXX somewhere... -DaveM
1355 */
1356 cheetah_fix_ce(afar);
1357 }
1358
1359 {
1360 int flush_all, flush_line;
1361
1362 flush_all = flush_line = 0;
1363 if ((afsr & CHAFSR_EDC) != 0UL) {
1364 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDC)
1365 flush_line = 1;
1366 else
1367 flush_all = 1;
1368 } else if ((afsr & CHAFSR_CPC) != 0UL) {
1369 if ((afsr & cheetah_afsr_errors) == CHAFSR_CPC)
1370 flush_line = 1;
1371 else
1372 flush_all = 1;
1373 }
1374
1375 /* Trap handler only disabled I-cache, flush it. */
1376 cheetah_flush_icache();
1377
1378 /* Re-enable I-cache */
1379 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1380 "or %%g1, %1, %%g1\n\t"
1381 "stxa %%g1, [%%g0] %0\n\t"
1382 "membar #Sync"
1383 : /* no outputs */
1384 : "i" (ASI_DCU_CONTROL_REG),
1385 "i" (DCU_IC)
1386 : "g1");
1387
1388 if (flush_all)
1389 cheetah_flush_ecache();
1390 else if (flush_line)
1391 cheetah_flush_ecache_line(afar);
1392 }
1393
1394 /* Re-enable error reporting */
1395 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1396 "or %%g1, %1, %%g1\n\t"
1397 "stxa %%g1, [%%g0] %0\n\t"
1398 "membar #Sync"
1399 : /* no outputs */
1400 : "i" (ASI_ESTATE_ERROR_EN),
1401 "i" (ESTATE_ERROR_CEEN)
1402 : "g1");
1403
1404 /* Decide if we can continue after handling this trap and
1405 * logging the error.
1406 */
1407 recoverable = 1;
1408 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1409 recoverable = 0;
1410
1411 /* Re-check AFSR/AFAR */
1412 (void) cheetah_recheck_errors(&local_snapshot);
1413
1414 /* Log errors. */
1415 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1416
1417 if (!recoverable)
1418 panic("Irrecoverable Correctable-ECC error trap.\n");
1419 }
1420
1421 void cheetah_deferred_handler(struct pt_regs *regs, unsigned long afsr, unsigned long afar)
1422 {
1423 struct cheetah_err_info local_snapshot, *p;
1424 int recoverable, is_memory;
1425
1426 #ifdef CONFIG_PCI
1427 /* Check for the special PCI poke sequence. */
1428 if (pci_poke_in_progress && pci_poke_cpu == smp_processor_id()) {
1429 cheetah_flush_icache();
1430 cheetah_flush_dcache();
1431
1432 /* Re-enable I-cache/D-cache */
1433 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1434 "or %%g1, %1, %%g1\n\t"
1435 "stxa %%g1, [%%g0] %0\n\t"
1436 "membar #Sync"
1437 : /* no outputs */
1438 : "i" (ASI_DCU_CONTROL_REG),
1439 "i" (DCU_DC | DCU_IC)
1440 : "g1");
1441
1442 /* Re-enable error reporting */
1443 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1444 "or %%g1, %1, %%g1\n\t"
1445 "stxa %%g1, [%%g0] %0\n\t"
1446 "membar #Sync"
1447 : /* no outputs */
1448 : "i" (ASI_ESTATE_ERROR_EN),
1449 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1450 : "g1");
1451
1452 (void) cheetah_recheck_errors(NULL);
1453
1454 pci_poke_faulted = 1;
1455 regs->tpc += 4;
1456 regs->tnpc = regs->tpc + 4;
1457 return;
1458 }
1459 #endif
1460
1461 p = cheetah_get_error_log(afsr);
1462 if (!p) {
1463 prom_printf("ERROR: Early deferred error afsr[%016lx] afar[%016lx]\n",
1464 afsr, afar);
1465 prom_printf("ERROR: CPU(%d) TPC[%016lx] TNPC[%016lx] TSTATE[%016lx]\n",
1466 smp_processor_id(), regs->tpc, regs->tnpc, regs->tstate);
1467 prom_halt();
1468 }
1469
1470 /* Grab snapshot of logged error. */
1471 memcpy(&local_snapshot, p, sizeof(local_snapshot));
1472
1473 /* If the current trap snapshot does not match what the
1474 * trap handler passed along into our args, big trouble.
1475 * In such a case, mark the local copy as invalid.
1476 *
1477 * Else, it matches and we mark the afsr in the non-local
1478 * copy as invalid so we may log new error traps there.
1479 */
1480 if (p->afsr != afsr || p->afar != afar)
1481 local_snapshot.afsr = CHAFSR_INVALID;
1482 else
1483 p->afsr = CHAFSR_INVALID;
1484
1485 is_memory = cheetah_check_main_memory(afar);
1486
1487 {
1488 int flush_all, flush_line;
1489
1490 flush_all = flush_line = 0;
1491 if ((afsr & CHAFSR_EDU) != 0UL) {
1492 if ((afsr & cheetah_afsr_errors) == CHAFSR_EDU)
1493 flush_line = 1;
1494 else
1495 flush_all = 1;
1496 } else if ((afsr & CHAFSR_BERR) != 0UL) {
1497 if ((afsr & cheetah_afsr_errors) == CHAFSR_BERR)
1498 flush_line = 1;
1499 else
1500 flush_all = 1;
1501 }
1502
1503 cheetah_flush_icache();
1504 cheetah_flush_dcache();
1505
1506 /* Re-enable I/D caches */
1507 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1508 "or %%g1, %1, %%g1\n\t"
1509 "stxa %%g1, [%%g0] %0\n\t"
1510 "membar #Sync"
1511 : /* no outputs */
1512 : "i" (ASI_DCU_CONTROL_REG),
1513 "i" (DCU_IC | DCU_DC)
1514 : "g1");
1515
1516 if (flush_all)
1517 cheetah_flush_ecache();
1518 else if (flush_line)
1519 cheetah_flush_ecache_line(afar);
1520 }
1521
1522 /* Re-enable error reporting */
1523 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1524 "or %%g1, %1, %%g1\n\t"
1525 "stxa %%g1, [%%g0] %0\n\t"
1526 "membar #Sync"
1527 : /* no outputs */
1528 : "i" (ASI_ESTATE_ERROR_EN),
1529 "i" (ESTATE_ERROR_NCEEN | ESTATE_ERROR_CEEN)
1530 : "g1");
1531
1532 /* Decide if we can continue after handling this trap and
1533 * logging the error.
1534 */
1535 recoverable = 1;
1536 if (afsr & (CHAFSR_PERR | CHAFSR_IERR | CHAFSR_ISAP))
1537 recoverable = 0;
1538
1539 /* Re-check AFSR/AFAR. What we are looking for here is whether a new
1540 * error was logged while we had error reporting traps disabled.
1541 */
1542 if (cheetah_recheck_errors(&local_snapshot)) {
1543 unsigned long new_afsr = local_snapshot.afsr;
1544
1545 /* If we got a new asynchronous error, die... */
1546 if (new_afsr & (CHAFSR_EMU | CHAFSR_EDU |
1547 CHAFSR_WDU | CHAFSR_CPU |
1548 CHAFSR_IVU | CHAFSR_UE |
1549 CHAFSR_BERR | CHAFSR_TO))
1550 recoverable = 0;
1551 }
1552
1553 /* Log errors. */
1554 cheetah_log_errors(regs, &local_snapshot, afsr, afar, recoverable);
1555
1556 /* "Recoverable" here means we try to yank the page from ever
1557 * being newly used again. This depends upon a few things:
1558 * 1) Must be main memory, and AFAR must be valid.
1559 * 2) If we trapped from user, OK.
1560 * 3) Else, if we trapped from kernel we must find exception
1561 * table entry (ie. we have to have been accessing user
1562 * space).
1563 *
1564 * If AFAR is not in main memory, or we trapped from kernel
1565 * and cannot find an exception table entry, it is unacceptable
1566 * to try and continue.
1567 */
1568 if (recoverable && is_memory) {
1569 if ((regs->tstate & TSTATE_PRIV) == 0UL) {
1570 /* OK, usermode access. */
1571 recoverable = 1;
1572 } else {
1573 unsigned long g2 = regs->u_regs[UREG_G2];
1574 unsigned long fixup = search_extables_range(regs->tpc, &g2);
1575
1576 if (fixup != 0UL) {
1577 /* OK, kernel access to userspace. */
1578 recoverable = 1;
1579
1580 } else {
1581 /* BAD, privileged state is corrupted. */
1582 recoverable = 0;
1583 }
1584
1585 if (recoverable) {
1586 if (pfn_valid(afar >> PAGE_SHIFT))
1587 get_page(pfn_to_page(afar >> PAGE_SHIFT));
1588 else
1589 recoverable = 0;
1590
1591 /* Only perform fixup if we still have a
1592 * recoverable condition.
1593 */
1594 if (recoverable) {
1595 regs->tpc = fixup;
1596 regs->tnpc = regs->tpc + 4;
1597 regs->u_regs[UREG_G2] = g2;
1598 }
1599 }
1600 }
1601 } else {
1602 recoverable = 0;
1603 }
1604
1605 if (!recoverable)
1606 panic("Irrecoverable deferred error trap.\n");
1607 }
1608
1609 /* Handle a D/I cache parity error trap. TYPE is encoded as:
1610 *
1611 * Bit0: 0=dcache,1=icache
1612 * Bit1: 0=recoverable,1=unrecoverable
1613 *
1614 * The hardware has disabled both the I-cache and D-cache in
1615 * the %dcr register.
1616 */
1617 void cheetah_plus_parity_error(int type, struct pt_regs *regs)
1618 {
1619 if (type & 0x1)
1620 __cheetah_flush_icache();
1621 else
1622 cheetah_plus_zap_dcache_parity();
1623 cheetah_flush_dcache();
1624
1625 /* Re-enable I-cache/D-cache */
1626 __asm__ __volatile__("ldxa [%%g0] %0, %%g1\n\t"
1627 "or %%g1, %1, %%g1\n\t"
1628 "stxa %%g1, [%%g0] %0\n\t"
1629 "membar #Sync"
1630 : /* no outputs */
1631 : "i" (ASI_DCU_CONTROL_REG),
1632 "i" (DCU_DC | DCU_IC)
1633 : "g1");
1634
1635 if (type & 0x2) {
1636 printk(KERN_EMERG "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1637 smp_processor_id(),
1638 (type & 0x1) ? 'I' : 'D',
1639 regs->tpc);
1640 panic("Irrecoverable Cheetah+ parity error.");
1641 }
1642
1643 printk(KERN_WARNING "CPU[%d]: Cheetah+ %c-cache parity error at TPC[%016lx]\n",
1644 smp_processor_id(),
1645 (type & 0x1) ? 'I' : 'D',
1646 regs->tpc);
1647 }
1648
1649 void do_fpe_common(struct pt_regs *regs)
1650 {
1651 if (regs->tstate & TSTATE_PRIV) {
1652 regs->tpc = regs->tnpc;
1653 regs->tnpc += 4;
1654 } else {
1655 unsigned long fsr = current_thread_info()->xfsr[0];
1656 siginfo_t info;
1657
1658 if (test_thread_flag(TIF_32BIT)) {
1659 regs->tpc &= 0xffffffff;
1660 regs->tnpc &= 0xffffffff;
1661 }
1662 info.si_signo = SIGFPE;
1663 info.si_errno = 0;
1664 info.si_addr = (void __user *)regs->tpc;
1665 info.si_trapno = 0;
1666 info.si_code = __SI_FAULT;
1667 if ((fsr & 0x1c000) == (1 << 14)) {
1668 if (fsr & 0x10)
1669 info.si_code = FPE_FLTINV;
1670 else if (fsr & 0x08)
1671 info.si_code = FPE_FLTOVF;
1672 else if (fsr & 0x04)
1673 info.si_code = FPE_FLTUND;
1674 else if (fsr & 0x02)
1675 info.si_code = FPE_FLTDIV;
1676 else if (fsr & 0x01)
1677 info.si_code = FPE_FLTRES;
1678 }
1679 force_sig_info(SIGFPE, &info, current);
1680 }
1681 }
1682
1683 void do_fpieee(struct pt_regs *regs)
1684 {
1685 if (notify_die(DIE_TRAP, "fpu exception ieee", regs,
1686 0, 0x24, SIGFPE) == NOTIFY_STOP)
1687 return;
1688
1689 do_fpe_common(regs);
1690 }
1691
1692 extern int do_mathemu(struct pt_regs *, struct fpustate *);
1693
1694 void do_fpother(struct pt_regs *regs)
1695 {
1696 struct fpustate *f = FPUSTATE;
1697 int ret = 0;
1698
1699 if (notify_die(DIE_TRAP, "fpu exception other", regs,
1700 0, 0x25, SIGFPE) == NOTIFY_STOP)
1701 return;
1702
1703 switch ((current_thread_info()->xfsr[0] & 0x1c000)) {
1704 case (2 << 14): /* unfinished_FPop */
1705 case (3 << 14): /* unimplemented_FPop */
1706 ret = do_mathemu(regs, f);
1707 break;
1708 }
1709 if (ret)
1710 return;
1711 do_fpe_common(regs);
1712 }
1713
1714 void do_tof(struct pt_regs *regs)
1715 {
1716 siginfo_t info;
1717
1718 if (notify_die(DIE_TRAP, "tagged arithmetic overflow", regs,
1719 0, 0x26, SIGEMT) == NOTIFY_STOP)
1720 return;
1721
1722 if (regs->tstate & TSTATE_PRIV)
1723 die_if_kernel("Penguin overflow trap from kernel mode", regs);
1724 if (test_thread_flag(TIF_32BIT)) {
1725 regs->tpc &= 0xffffffff;
1726 regs->tnpc &= 0xffffffff;
1727 }
1728 info.si_signo = SIGEMT;
1729 info.si_errno = 0;
1730 info.si_code = EMT_TAGOVF;
1731 info.si_addr = (void __user *)regs->tpc;
1732 info.si_trapno = 0;
1733 force_sig_info(SIGEMT, &info, current);
1734 }
1735
1736 void do_div0(struct pt_regs *regs)
1737 {
1738 siginfo_t info;
1739
1740 if (notify_die(DIE_TRAP, "integer division by zero", regs,
1741 0, 0x28, SIGFPE) == NOTIFY_STOP)
1742 return;
1743
1744 if (regs->tstate & TSTATE_PRIV)
1745 die_if_kernel("TL0: Kernel divide by zero.", regs);
1746 if (test_thread_flag(TIF_32BIT)) {
1747 regs->tpc &= 0xffffffff;
1748 regs->tnpc &= 0xffffffff;
1749 }
1750 info.si_signo = SIGFPE;
1751 info.si_errno = 0;
1752 info.si_code = FPE_INTDIV;
1753 info.si_addr = (void __user *)regs->tpc;
1754 info.si_trapno = 0;
1755 force_sig_info(SIGFPE, &info, current);
1756 }
1757
1758 void instruction_dump (unsigned int *pc)
1759 {
1760 int i;
1761
1762 if ((((unsigned long) pc) & 3))
1763 return;
1764
1765 printk("Instruction DUMP:");
1766 for (i = -3; i < 6; i++)
1767 printk("%c%08x%c",i?' ':'<',pc[i],i?' ':'>');
1768 printk("\n");
1769 }
1770
1771 static void user_instruction_dump (unsigned int __user *pc)
1772 {
1773 int i;
1774 unsigned int buf[9];
1775
1776 if ((((unsigned long) pc) & 3))
1777 return;
1778
1779 if (copy_from_user(buf, pc - 3, sizeof(buf)))
1780 return;
1781
1782 printk("Instruction DUMP:");
1783 for (i = 0; i < 9; i++)
1784 printk("%c%08x%c",i==3?' ':'<',buf[i],i==3?' ':'>');
1785 printk("\n");
1786 }
1787
1788 void show_stack(struct task_struct *tsk, unsigned long *_ksp)
1789 {
1790 unsigned long pc, fp, thread_base, ksp;
1791 struct thread_info *tp = tsk->thread_info;
1792 struct reg_window *rw;
1793 int count = 0;
1794
1795 ksp = (unsigned long) _ksp;
1796
1797 if (tp == current_thread_info())
1798 flushw_all();
1799
1800 fp = ksp + STACK_BIAS;
1801 thread_base = (unsigned long) tp;
1802
1803 printk("Call Trace:");
1804 #ifdef CONFIG_KALLSYMS
1805 printk("\n");
1806 #endif
1807 do {
1808 /* Bogus frame pointer? */
1809 if (fp < (thread_base + sizeof(struct thread_info)) ||
1810 fp >= (thread_base + THREAD_SIZE))
1811 break;
1812 rw = (struct reg_window *)fp;
1813 pc = rw->ins[7];
1814 printk(" [%016lx] ", pc);
1815 print_symbol("%s\n", pc);
1816 fp = rw->ins[6] + STACK_BIAS;
1817 } while (++count < 16);
1818 #ifndef CONFIG_KALLSYMS
1819 printk("\n");
1820 #endif
1821 }
1822
1823 void dump_stack(void)
1824 {
1825 unsigned long *ksp;
1826
1827 __asm__ __volatile__("mov %%fp, %0"
1828 : "=r" (ksp));
1829 show_stack(current, ksp);
1830 }
1831
1832 EXPORT_SYMBOL(dump_stack);
1833
1834 static inline int is_kernel_stack(struct task_struct *task,
1835 struct reg_window *rw)
1836 {
1837 unsigned long rw_addr = (unsigned long) rw;
1838 unsigned long thread_base, thread_end;
1839
1840 if (rw_addr < PAGE_OFFSET) {
1841 if (task != &init_task)
1842 return 0;
1843 }
1844
1845 thread_base = (unsigned long) task->thread_info;
1846 thread_end = thread_base + sizeof(union thread_union);
1847 if (rw_addr >= thread_base &&
1848 rw_addr < thread_end &&
1849 !(rw_addr & 0x7UL))
1850 return 1;
1851
1852 return 0;
1853 }
1854
1855 static inline struct reg_window *kernel_stack_up(struct reg_window *rw)
1856 {
1857 unsigned long fp = rw->ins[6];
1858
1859 if (!fp)
1860 return NULL;
1861
1862 return (struct reg_window *) (fp + STACK_BIAS);
1863 }
1864
1865 void die_if_kernel(char *str, struct pt_regs *regs)
1866 {
1867 static int die_counter;
1868 extern void __show_regs(struct pt_regs * regs);
1869 extern void smp_report_regs(void);
1870 int count = 0;
1871
1872 /* Amuse the user. */
1873 printk(
1874 " \\|/ ____ \\|/\n"
1875 " \"@'/ .. \\`@\"\n"
1876 " /_| \\__/ |_\\\n"
1877 " \\__U_/\n");
1878
1879 printk("%s(%d): %s [#%d]\n", current->comm, current->pid, str, ++die_counter);
1880 notify_die(DIE_OOPS, str, regs, 0, 255, SIGSEGV);
1881 __asm__ __volatile__("flushw");
1882 __show_regs(regs);
1883 if (regs->tstate & TSTATE_PRIV) {
1884 struct reg_window *rw = (struct reg_window *)
1885 (regs->u_regs[UREG_FP] + STACK_BIAS);
1886
1887 /* Stop the back trace when we hit userland or we
1888 * find some badly aligned kernel stack.
1889 */
1890 while (rw &&
1891 count++ < 30&&
1892 is_kernel_stack(current, rw)) {
1893 printk("Caller[%016lx]", rw->ins[7]);
1894 print_symbol(": %s", rw->ins[7]);
1895 printk("\n");
1896
1897 rw = kernel_stack_up(rw);
1898 }
1899 instruction_dump ((unsigned int *) regs->tpc);
1900 } else {
1901 if (test_thread_flag(TIF_32BIT)) {
1902 regs->tpc &= 0xffffffff;
1903 regs->tnpc &= 0xffffffff;
1904 }
1905 user_instruction_dump ((unsigned int __user *) regs->tpc);
1906 }
1907 #ifdef CONFIG_SMP
1908 smp_report_regs();
1909 #endif
1910
1911 if (regs->tstate & TSTATE_PRIV)
1912 do_exit(SIGKILL);
1913 do_exit(SIGSEGV);
1914 }
1915
1916 extern int handle_popc(u32 insn, struct pt_regs *regs);
1917 extern int handle_ldf_stq(u32 insn, struct pt_regs *regs);
1918
1919 void do_illegal_instruction(struct pt_regs *regs)
1920 {
1921 unsigned long pc = regs->tpc;
1922 unsigned long tstate = regs->tstate;
1923 u32 insn;
1924 siginfo_t info;
1925
1926 if (notify_die(DIE_TRAP, "illegal instruction", regs,
1927 0, 0x10, SIGILL) == NOTIFY_STOP)
1928 return;
1929
1930 if (tstate & TSTATE_PRIV)
1931 die_if_kernel("Kernel illegal instruction", regs);
1932 if (test_thread_flag(TIF_32BIT))
1933 pc = (u32)pc;
1934 if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
1935 if ((insn & 0xc1ffc000) == 0x81700000) /* POPC */ {
1936 if (handle_popc(insn, regs))
1937 return;
1938 } else if ((insn & 0xc1580000) == 0xc1100000) /* LDQ/STQ */ {
1939 if (handle_ldf_stq(insn, regs))
1940 return;
1941 }
1942 }
1943 info.si_signo = SIGILL;
1944 info.si_errno = 0;
1945 info.si_code = ILL_ILLOPC;
1946 info.si_addr = (void __user *)pc;
1947 info.si_trapno = 0;
1948 force_sig_info(SIGILL, &info, current);
1949 }
1950
1951 void mem_address_unaligned(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
1952 {
1953 siginfo_t info;
1954
1955 if (notify_die(DIE_TRAP, "memory address unaligned", regs,
1956 0, 0x34, SIGSEGV) == NOTIFY_STOP)
1957 return;
1958
1959 if (regs->tstate & TSTATE_PRIV) {
1960 extern void kernel_unaligned_trap(struct pt_regs *regs,
1961 unsigned int insn,
1962 unsigned long sfar,
1963 unsigned long sfsr);
1964
1965 kernel_unaligned_trap(regs, *((unsigned int *)regs->tpc),
1966 sfar, sfsr);
1967 return;
1968 }
1969 info.si_signo = SIGBUS;
1970 info.si_errno = 0;
1971 info.si_code = BUS_ADRALN;
1972 info.si_addr = (void __user *)sfar;
1973 info.si_trapno = 0;
1974 force_sig_info(SIGBUS, &info, current);
1975 }
1976
1977 void do_privop(struct pt_regs *regs)
1978 {
1979 siginfo_t info;
1980
1981 if (notify_die(DIE_TRAP, "privileged operation", regs,
1982 0, 0x11, SIGILL) == NOTIFY_STOP)
1983 return;
1984
1985 if (test_thread_flag(TIF_32BIT)) {
1986 regs->tpc &= 0xffffffff;
1987 regs->tnpc &= 0xffffffff;
1988 }
1989 info.si_signo = SIGILL;
1990 info.si_errno = 0;
1991 info.si_code = ILL_PRVOPC;
1992 info.si_addr = (void __user *)regs->tpc;
1993 info.si_trapno = 0;
1994 force_sig_info(SIGILL, &info, current);
1995 }
1996
1997 void do_privact(struct pt_regs *regs)
1998 {
1999 do_privop(regs);
2000 }
2001
2002 /* Trap level 1 stuff or other traps we should never see... */
2003 void do_cee(struct pt_regs *regs)
2004 {
2005 die_if_kernel("TL0: Cache Error Exception", regs);
2006 }
2007
2008 void do_cee_tl1(struct pt_regs *regs)
2009 {
2010 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2011 die_if_kernel("TL1: Cache Error Exception", regs);
2012 }
2013
2014 void do_dae_tl1(struct pt_regs *regs)
2015 {
2016 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2017 die_if_kernel("TL1: Data Access Exception", regs);
2018 }
2019
2020 void do_iae_tl1(struct pt_regs *regs)
2021 {
2022 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2023 die_if_kernel("TL1: Instruction Access Exception", regs);
2024 }
2025
2026 void do_div0_tl1(struct pt_regs *regs)
2027 {
2028 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2029 die_if_kernel("TL1: DIV0 Exception", regs);
2030 }
2031
2032 void do_fpdis_tl1(struct pt_regs *regs)
2033 {
2034 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2035 die_if_kernel("TL1: FPU Disabled", regs);
2036 }
2037
2038 void do_fpieee_tl1(struct pt_regs *regs)
2039 {
2040 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2041 die_if_kernel("TL1: FPU IEEE Exception", regs);
2042 }
2043
2044 void do_fpother_tl1(struct pt_regs *regs)
2045 {
2046 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2047 die_if_kernel("TL1: FPU Other Exception", regs);
2048 }
2049
2050 void do_ill_tl1(struct pt_regs *regs)
2051 {
2052 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2053 die_if_kernel("TL1: Illegal Instruction Exception", regs);
2054 }
2055
2056 void do_irq_tl1(struct pt_regs *regs)
2057 {
2058 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2059 die_if_kernel("TL1: IRQ Exception", regs);
2060 }
2061
2062 void do_lddfmna_tl1(struct pt_regs *regs)
2063 {
2064 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2065 die_if_kernel("TL1: LDDF Exception", regs);
2066 }
2067
2068 void do_stdfmna_tl1(struct pt_regs *regs)
2069 {
2070 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2071 die_if_kernel("TL1: STDF Exception", regs);
2072 }
2073
2074 void do_paw(struct pt_regs *regs)
2075 {
2076 die_if_kernel("TL0: Phys Watchpoint Exception", regs);
2077 }
2078
2079 void do_paw_tl1(struct pt_regs *regs)
2080 {
2081 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2082 die_if_kernel("TL1: Phys Watchpoint Exception", regs);
2083 }
2084
2085 void do_vaw(struct pt_regs *regs)
2086 {
2087 die_if_kernel("TL0: Virt Watchpoint Exception", regs);
2088 }
2089
2090 void do_vaw_tl1(struct pt_regs *regs)
2091 {
2092 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2093 die_if_kernel("TL1: Virt Watchpoint Exception", regs);
2094 }
2095
2096 void do_tof_tl1(struct pt_regs *regs)
2097 {
2098 dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
2099 die_if_kernel("TL1: Tag Overflow Exception", regs);
2100 }
2101
2102 void do_getpsr(struct pt_regs *regs)
2103 {
2104 regs->u_regs[UREG_I0] = tstate_to_psr(regs->tstate);
2105 regs->tpc = regs->tnpc;
2106 regs->tnpc += 4;
2107 if (test_thread_flag(TIF_32BIT)) {
2108 regs->tpc &= 0xffffffff;
2109 regs->tnpc &= 0xffffffff;
2110 }
2111 }
2112
2113 extern void thread_info_offsets_are_bolixed_dave(void);
2114
2115 /* Only invoked on boot processor. */
2116 void __init trap_init(void)
2117 {
2118 /* Compile time sanity check. */
2119 if (TI_TASK != offsetof(struct thread_info, task) ||
2120 TI_FLAGS != offsetof(struct thread_info, flags) ||
2121 TI_CPU != offsetof(struct thread_info, cpu) ||
2122 TI_FPSAVED != offsetof(struct thread_info, fpsaved) ||
2123 TI_KSP != offsetof(struct thread_info, ksp) ||
2124 TI_FAULT_ADDR != offsetof(struct thread_info, fault_address) ||
2125 TI_KREGS != offsetof(struct thread_info, kregs) ||
2126 TI_UTRAPS != offsetof(struct thread_info, utraps) ||
2127 TI_EXEC_DOMAIN != offsetof(struct thread_info, exec_domain) ||
2128 TI_REG_WINDOW != offsetof(struct thread_info, reg_window) ||
2129 TI_RWIN_SPTRS != offsetof(struct thread_info, rwbuf_stkptrs) ||
2130 TI_GSR != offsetof(struct thread_info, gsr) ||
2131 TI_XFSR != offsetof(struct thread_info, xfsr) ||
2132 TI_USER_CNTD0 != offsetof(struct thread_info, user_cntd0) ||
2133 TI_USER_CNTD1 != offsetof(struct thread_info, user_cntd1) ||
2134 TI_KERN_CNTD0 != offsetof(struct thread_info, kernel_cntd0) ||
2135 TI_KERN_CNTD1 != offsetof(struct thread_info, kernel_cntd1) ||
2136 TI_PCR != offsetof(struct thread_info, pcr_reg) ||
2137 TI_CEE_STUFF != offsetof(struct thread_info, cee_stuff) ||
2138 TI_PRE_COUNT != offsetof(struct thread_info, preempt_count) ||
2139 TI_NEW_CHILD != offsetof(struct thread_info, new_child) ||
2140 TI_SYS_NOERROR != offsetof(struct thread_info, syscall_noerror) ||
2141 TI_RESTART_BLOCK != offsetof(struct thread_info, restart_block) ||
2142 TI_KUNA_REGS != offsetof(struct thread_info, kern_una_regs) ||
2143 TI_KUNA_INSN != offsetof(struct thread_info, kern_una_insn) ||
2144 TI_FPREGS != offsetof(struct thread_info, fpregs) ||
2145 (TI_FPREGS & (64 - 1)))
2146 thread_info_offsets_are_bolixed_dave();
2147
2148 /* Attach to the address space of init_task. On SMP we
2149 * do this in smp.c:smp_callin for other cpus.
2150 */
2151 atomic_inc(&init_mm.mm_count);
2152 current->active_mm = &init_mm;
2153 }
WandBoard kernel