2 * Support for the interrupt controllers found on Power Macintosh,
3 * currently Apple's "Grand Central" interrupt controller in all
4 * it's incarnations. OpenPIC support used on newer machines is
7 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
9 * Maintained by Benjamin Herrenschmidt (benh@kernel.crashing.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
18 #include <linux/config.h>
19 #include <linux/stddef.h>
20 #include <linux/init.h>
21 #include <linux/sched.h>
22 #include <linux/signal.h>
23 #include <linux/pci.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysdev.h>
26 #include <linux/adb.h>
27 #include <linux/pmu.h>
28 #include <linux/module.h>
30 #include <asm/sections.h>
34 #include <asm/pci-bridge.h>
36 #include <asm/pmac_feature.h>
42 * XXX this should be in xmon.h, but putting it there means xmon.h
43 * has to include <linux/interrupt.h> (to get irqreturn_t), which
44 * causes all sorts of problems. -- paulus
46 extern irqreturn_t
xmon_irq(int, void *, struct pt_regs
*);
56 /* Default addresses */
57 static volatile struct pmac_irq_hw
*pmac_irq_hw
[4] = {
58 (struct pmac_irq_hw
*) 0xf3000020,
59 (struct pmac_irq_hw
*) 0xf3000010,
60 (struct pmac_irq_hw
*) 0xf4000020,
61 (struct pmac_irq_hw
*) 0xf4000010,
64 #define GC_LEVEL_MASK 0x3ff00000
65 #define OHARE_LEVEL_MASK 0x1ff00000
66 #define HEATHROW_LEVEL_MASK 0x1ff00000
69 static int max_real_irqs
;
70 static u32 level_mask
[4];
72 static DEFINE_SPINLOCK(pmac_pic_lock
);
74 /* XXX here for now, should move to arch/powerpc/kernel/irq.c */
75 int ppc_do_canonicalize_irqs
;
76 EXPORT_SYMBOL(ppc_do_canonicalize_irqs
);
78 #define GATWICK_IRQ_POOL_SIZE 10
79 static struct interrupt_info gatwick_int_pool
[GATWICK_IRQ_POOL_SIZE
];
82 * Mark an irq as "lost". This is only used on the pmac
83 * since it can lose interrupts (see pmac_set_irq_mask).
87 __set_lost(unsigned long irq_nr
, int nokick
)
89 if (!test_and_set_bit(irq_nr
, ppc_lost_interrupts
)) {
90 atomic_inc(&ppc_n_lost_interrupts
);
97 pmac_mask_and_ack_irq(unsigned int irq_nr
)
99 unsigned long bit
= 1UL << (irq_nr
& 0x1f);
103 if ((unsigned)irq_nr
>= max_irqs
)
106 clear_bit(irq_nr
, ppc_cached_irq_mask
);
107 if (test_and_clear_bit(irq_nr
, ppc_lost_interrupts
))
108 atomic_dec(&ppc_n_lost_interrupts
);
109 spin_lock_irqsave(&pmac_pic_lock
, flags
);
110 out_le32(&pmac_irq_hw
[i
]->enable
, ppc_cached_irq_mask
[i
]);
111 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
113 /* make sure ack gets to controller before we enable
116 } while((in_le32(&pmac_irq_hw
[i
]->enable
) & bit
)
117 != (ppc_cached_irq_mask
[i
] & bit
));
118 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
121 static void pmac_set_irq_mask(unsigned int irq_nr
, int nokicklost
)
123 unsigned long bit
= 1UL << (irq_nr
& 0x1f);
127 if ((unsigned)irq_nr
>= max_irqs
)
130 spin_lock_irqsave(&pmac_pic_lock
, flags
);
131 /* enable unmasked interrupts */
132 out_le32(&pmac_irq_hw
[i
]->enable
, ppc_cached_irq_mask
[i
]);
135 /* make sure mask gets to controller before we
138 } while((in_le32(&pmac_irq_hw
[i
]->enable
) & bit
)
139 != (ppc_cached_irq_mask
[i
] & bit
));
142 * Unfortunately, setting the bit in the enable register
143 * when the device interrupt is already on *doesn't* set
144 * the bit in the flag register or request another interrupt.
146 if (bit
& ppc_cached_irq_mask
[i
] & in_le32(&pmac_irq_hw
[i
]->level
))
147 __set_lost((ulong
)irq_nr
, nokicklost
);
148 spin_unlock_irqrestore(&pmac_pic_lock
, flags
);
151 /* When an irq gets requested for the first client, if it's an
152 * edge interrupt, we clear any previous one on the controller
154 static unsigned int pmac_startup_irq(unsigned int irq_nr
)
156 unsigned long bit
= 1UL << (irq_nr
& 0x1f);
159 if ((irq_desc
[irq_nr
].status
& IRQ_LEVEL
) == 0)
160 out_le32(&pmac_irq_hw
[i
]->ack
, bit
);
161 set_bit(irq_nr
, ppc_cached_irq_mask
);
162 pmac_set_irq_mask(irq_nr
, 0);
167 static void pmac_mask_irq(unsigned int irq_nr
)
169 clear_bit(irq_nr
, ppc_cached_irq_mask
);
170 pmac_set_irq_mask(irq_nr
, 0);
174 static void pmac_unmask_irq(unsigned int irq_nr
)
176 set_bit(irq_nr
, ppc_cached_irq_mask
);
177 pmac_set_irq_mask(irq_nr
, 0);
180 static void pmac_end_irq(unsigned int irq_nr
)
182 if (!(irq_desc
[irq_nr
].status
& (IRQ_DISABLED
|IRQ_INPROGRESS
))
183 && irq_desc
[irq_nr
].action
) {
184 set_bit(irq_nr
, ppc_cached_irq_mask
);
185 pmac_set_irq_mask(irq_nr
, 1);
190 struct hw_interrupt_type pmac_pic
= {
191 .typename
= " PMAC-PIC ",
192 .startup
= pmac_startup_irq
,
193 .enable
= pmac_unmask_irq
,
194 .disable
= pmac_mask_irq
,
195 .ack
= pmac_mask_and_ack_irq
,
199 struct hw_interrupt_type gatwick_pic
= {
200 .typename
= " GATWICK ",
201 .startup
= pmac_startup_irq
,
202 .enable
= pmac_unmask_irq
,
203 .disable
= pmac_mask_irq
,
204 .ack
= pmac_mask_and_ack_irq
,
208 static irqreturn_t
gatwick_action(int cpl
, void *dev_id
, struct pt_regs
*regs
)
212 for (irq
= max_irqs
; (irq
-= 32) >= max_real_irqs
; ) {
214 bits
= in_le32(&pmac_irq_hw
[i
]->event
) | ppc_lost_interrupts
[i
];
215 /* We must read level interrupts from the level register */
216 bits
|= (in_le32(&pmac_irq_hw
[i
]->level
) & level_mask
[i
]);
217 bits
&= ppc_cached_irq_mask
[i
];
220 irq
+= __ilog2(bits
);
224 printk("gatwick irq not from gatwick pic\n");
229 pmac_get_irq(struct pt_regs
*regs
)
232 unsigned long bits
= 0;
235 void psurge_smp_message_recv(struct pt_regs
*);
237 /* IPI's are a hack on the powersurge -- Cort */
238 if ( smp_processor_id() != 0 ) {
239 psurge_smp_message_recv(regs
);
240 return -2; /* ignore, already handled */
242 #endif /* CONFIG_SMP */
243 for (irq
= max_real_irqs
; (irq
-= 32) >= 0; ) {
245 bits
= in_le32(&pmac_irq_hw
[i
]->event
) | ppc_lost_interrupts
[i
];
246 /* We must read level interrupts from the level register */
247 bits
|= (in_le32(&pmac_irq_hw
[i
]->level
) & level_mask
[i
]);
248 bits
&= ppc_cached_irq_mask
[i
];
251 irq
+= __ilog2(bits
);
258 /* This routine will fix some missing interrupt values in the device tree
259 * on the gatwick mac-io controller used by some PowerBooks
262 pmac_fix_gatwick_interrupts(struct device_node
*gw
, int irq_base
)
264 struct device_node
*node
;
267 memset(gatwick_int_pool
, 0, sizeof(gatwick_int_pool
));
273 if (strcasecmp(node
->name
, "escc") == 0)
275 if (node
->child
->n_intrs
< 3) {
276 node
->child
->intrs
= &gatwick_int_pool
[count
];
279 node
->child
->n_intrs
= 3;
280 node
->child
->intrs
[0].line
= 15+irq_base
;
281 node
->child
->intrs
[1].line
= 4+irq_base
;
282 node
->child
->intrs
[2].line
= 5+irq_base
;
283 printk(KERN_INFO
"irq: fixed SCC on second controller (%d,%d,%d)\n",
284 node
->child
->intrs
[0].line
,
285 node
->child
->intrs
[1].line
,
286 node
->child
->intrs
[2].line
);
288 /* Fix media-bay & left SWIM */
289 if (strcasecmp(node
->name
, "media-bay") == 0) {
290 struct device_node
* ya_node
;
292 if (node
->n_intrs
== 0)
293 node
->intrs
= &gatwick_int_pool
[count
++];
295 node
->intrs
[0].line
= 29+irq_base
;
296 printk(KERN_INFO
"irq: fixed media-bay on second controller (%d)\n",
297 node
->intrs
[0].line
);
299 ya_node
= node
->child
;
302 if (strcasecmp(ya_node
->name
, "floppy") == 0) {
303 if (ya_node
->n_intrs
< 2) {
304 ya_node
->intrs
= &gatwick_int_pool
[count
];
307 ya_node
->n_intrs
= 2;
308 ya_node
->intrs
[0].line
= 19+irq_base
;
309 ya_node
->intrs
[1].line
= 1+irq_base
;
310 printk(KERN_INFO
"irq: fixed floppy on second controller (%d,%d)\n",
311 ya_node
->intrs
[0].line
, ya_node
->intrs
[1].line
);
313 if (strcasecmp(ya_node
->name
, "ata4") == 0) {
314 if (ya_node
->n_intrs
< 2) {
315 ya_node
->intrs
= &gatwick_int_pool
[count
];
318 ya_node
->n_intrs
= 2;
319 ya_node
->intrs
[0].line
= 14+irq_base
;
320 ya_node
->intrs
[1].line
= 3+irq_base
;
321 printk(KERN_INFO
"irq: fixed ide on second controller (%d,%d)\n",
322 ya_node
->intrs
[0].line
, ya_node
->intrs
[1].line
);
324 ya_node
= ya_node
->sibling
;
327 node
= node
->sibling
;
330 printk("WARNING !! Gatwick interrupt pool overflow\n");
331 printk(" GATWICK_IRQ_POOL_SIZE = %d\n", GATWICK_IRQ_POOL_SIZE
);
332 printk(" requested = %d\n", count
);
337 * The PowerBook 3400/2400/3500 can have a combo ethernet/modem
338 * card which includes an ohare chip that acts as a second interrupt
339 * controller. If we find this second ohare, set it up and fix the
340 * interrupt value in the device tree for the ethernet chip.
342 static int __init
enable_second_ohare(void)
344 unsigned char bus
, devfn
;
347 struct device_node
*irqctrler
= find_devices("pci106b,7");
348 struct device_node
*ether
;
350 if (irqctrler
== NULL
|| irqctrler
->n_addrs
<= 0)
352 addr
= (unsigned long) ioremap(irqctrler
->addrs
[0].address
, 0x40);
353 pmac_irq_hw
[1] = (volatile struct pmac_irq_hw
*)(addr
+ 0x20);
355 if (pci_device_from_OF_node(irqctrler
, &bus
, &devfn
) == 0) {
356 struct pci_controller
* hose
= pci_find_hose_for_OF_device(irqctrler
);
358 printk(KERN_ERR
"Can't find PCI hose for OHare2 !\n");
360 early_read_config_word(hose
, bus
, devfn
, PCI_COMMAND
, &cmd
);
361 cmd
|= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
;
362 cmd
&= ~PCI_COMMAND_IO
;
363 early_write_config_word(hose
, bus
, devfn
, PCI_COMMAND
, cmd
);
367 /* Fix interrupt for the modem/ethernet combo controller. The number
368 in the device tree (27) is bogus (correct for the ethernet-only
369 board but not the combo ethernet/modem board).
370 The real interrupt is 28 on the second controller -> 28+32 = 60.
372 ether
= find_devices("pci1011,14");
373 if (ether
&& ether
->n_intrs
> 0) {
374 ether
->intrs
[0].line
= 60;
375 printk(KERN_INFO
"irq: Fixed ethernet IRQ to %d\n",
376 ether
->intrs
[0].line
);
379 /* Return the interrupt number of the cascade */
380 return irqctrler
->intrs
[0].line
;
384 static struct irqaction xmon_action
= {
387 .mask
= CPU_MASK_NONE
,
392 static struct irqaction gatwick_cascade_action
= {
393 .handler
= gatwick_action
,
394 .flags
= SA_INTERRUPT
,
395 .mask
= CPU_MASK_NONE
,
398 #endif /* CONFIG_PPC32 */
400 static int pmac_u3_cascade(struct pt_regs
*regs
, void *data
)
402 return mpic_get_one_irq((struct mpic
*)data
, regs
);
405 void __init
pmac_pic_init(void)
407 struct device_node
*irqctrler
= NULL
;
408 struct device_node
*irqctrler2
= NULL
;
409 struct device_node
*np
;
413 int irq_cascade
= -1;
415 struct mpic
*mpic1
, *mpic2
;
417 /* We first try to detect Apple's new Core99 chipset, since mac-io
418 * is quite different on those machines and contains an IBM MPIC2.
420 np
= find_type_devices("open-pic");
422 if (np
->parent
&& !strcmp(np
->parent
->name
, "u3"))
428 if (irqctrler
!= NULL
&& irqctrler
->n_addrs
> 0) {
429 unsigned char senses
[128];
431 printk(KERN_INFO
"PowerMac using OpenPIC irq controller at 0x%08x\n",
432 (unsigned int)irqctrler
->addrs
[0].address
);
433 ppc_md
.get_irq
= mpic_get_irq
;
434 pmac_call_feature(PMAC_FTR_ENABLE_MPIC
, irqctrler
, 0, 0);
436 prom_get_irq_senses(senses
, 0, 128);
437 mpic1
= mpic_alloc(irqctrler
->addrs
[0].address
,
438 MPIC_PRIMARY
| MPIC_WANTS_RESET
,
439 0, 0, 128, 252, senses
, 128, " OpenPIC ");
440 BUG_ON(mpic1
== NULL
);
443 if (irqctrler2
!= NULL
&& irqctrler2
->n_intrs
> 0 &&
444 irqctrler2
->n_addrs
> 0) {
445 printk(KERN_INFO
"Slave OpenPIC at 0x%08x hooked on IRQ %d\n",
446 (u32
)irqctrler2
->addrs
[0].address
,
447 irqctrler2
->intrs
[0].line
);
449 pmac_call_feature(PMAC_FTR_ENABLE_MPIC
, irqctrler2
, 0, 0);
450 prom_get_irq_senses(senses
, 128, 128 + 124);
452 /* We don't need to set MPIC_BROKEN_U3 here since we don't have
453 * hypertransport interrupts routed to it
455 mpic2
= mpic_alloc(irqctrler2
->addrs
[0].address
,
456 MPIC_BIG_ENDIAN
| MPIC_WANTS_RESET
,
457 0, 128, 124, 0, senses
, 124,
459 BUG_ON(mpic2
== NULL
);
461 mpic_setup_cascade(irqctrler2
->intrs
[0].line
,
462 pmac_u3_cascade
, mpic2
);
464 #if defined(CONFIG_XMON) && defined(CONFIG_PPC32)
466 struct device_node
* pswitch
;
469 pswitch
= find_devices("programmer-switch");
470 if (pswitch
&& pswitch
->n_intrs
) {
471 nmi_irq
= pswitch
->intrs
[0].line
;
472 mpic_irq_set_priority(nmi_irq
, 9);
473 setup_irq(nmi_irq
, &xmon_action
);
476 #endif /* CONFIG_XMON */
482 /* Get the level/edge settings, assume if it's not
483 * a Grand Central nor an OHare, then it's an Heathrow
486 if (find_devices("gc"))
487 level_mask
[0] = GC_LEVEL_MASK
;
488 else if (find_devices("ohare")) {
489 level_mask
[0] = OHARE_LEVEL_MASK
;
490 /* We might have a second cascaded ohare */
491 level_mask
[1] = OHARE_LEVEL_MASK
;
493 level_mask
[0] = HEATHROW_LEVEL_MASK
;
495 /* We might have a second cascaded heathrow */
496 level_mask
[2] = HEATHROW_LEVEL_MASK
;
501 * G3 powermacs and 1999 G3 PowerBooks have 64 interrupts,
502 * 1998 G3 Series PowerBooks have 128,
503 * other powermacs have 32.
504 * The combo ethernet/modem card for the Powerstar powerbooks
505 * (2400/3400/3500, ohare based) has a second ohare chip
506 * effectively making a total of 64.
508 max_irqs
= max_real_irqs
= 32;
509 irqctrler
= find_devices("mac-io");
518 for ( i
= 0; i
< max_real_irqs
; i
++ )
519 irq_desc
[i
].handler
= &pmac_pic
;
521 /* get addresses of first controller */
523 if (irqctrler
->n_addrs
> 0) {
524 addr
= (unsigned long)
525 ioremap(irqctrler
->addrs
[0].address
, 0x40);
526 for (i
= 0; i
< 2; ++i
)
527 pmac_irq_hw
[i
] = (volatile struct pmac_irq_hw
*)
528 (addr
+ (2 - i
) * 0x10);
531 /* get addresses of second controller */
532 irqctrler
= irqctrler
->next
;
533 if (irqctrler
&& irqctrler
->n_addrs
> 0) {
534 addr
= (unsigned long)
535 ioremap(irqctrler
->addrs
[0].address
, 0x40);
536 for (i
= 2; i
< 4; ++i
)
537 pmac_irq_hw
[i
] = (volatile struct pmac_irq_hw
*)
538 (addr
+ (4 - i
) * 0x10);
539 irq_cascade
= irqctrler
->intrs
[0].line
;
540 if (device_is_compatible(irqctrler
, "gatwick"))
541 pmac_fix_gatwick_interrupts(irqctrler
, max_real_irqs
);
544 /* older powermacs have a GC (grand central) or ohare at
545 f3000000, with interrupt control registers at f3000020. */
546 addr
= (unsigned long) ioremap(0xf3000000, 0x40);
547 pmac_irq_hw
[0] = (volatile struct pmac_irq_hw
*) (addr
+ 0x20);
550 /* PowerBooks 3400 and 3500 can have a second controller in a second
551 ohare chip, on the combo ethernet/modem card */
552 if (machine_is_compatible("AAPL,3400/2400")
553 || machine_is_compatible("AAPL,3500"))
554 irq_cascade
= enable_second_ohare();
556 /* disable all interrupts in all controllers */
557 for (i
= 0; i
* 32 < max_irqs
; ++i
)
558 out_le32(&pmac_irq_hw
[i
]->enable
, 0);
559 /* mark level interrupts */
560 for (i
= 0; i
< max_irqs
; i
++)
561 if (level_mask
[i
>> 5] & (1UL << (i
& 0x1f)))
562 irq_desc
[i
].status
= IRQ_LEVEL
;
564 /* get interrupt line of secondary interrupt controller */
565 if (irq_cascade
>= 0) {
566 printk(KERN_INFO
"irq: secondary controller on irq %d\n",
568 for ( i
= max_real_irqs
; i
< max_irqs
; i
++ )
569 irq_desc
[i
].handler
= &gatwick_pic
;
570 setup_irq(irq_cascade
, &gatwick_cascade_action
);
572 printk("System has %d possible interrupts\n", max_irqs
);
573 if (max_irqs
!= max_real_irqs
)
574 printk(KERN_DEBUG
"%d interrupts on main controller\n",
578 setup_irq(20, &xmon_action
);
579 #endif /* CONFIG_XMON */
580 #endif /* CONFIG_PPC32 */
585 * These procedures are used in implementing sleep on the powerbooks.
586 * sleep_save_intrs() saves the states of all interrupt enables
587 * and disables all interrupts except for the nominated one.
588 * sleep_restore_intrs() restores the states of all interrupt enables.
590 unsigned long sleep_save_mask
[2];
592 /* This used to be passed by the PMU driver but that link got
593 * broken with the new driver model. We use this tweak for now...
595 static int pmacpic_find_viaint(void)
599 #ifdef CONFIG_ADB_PMU
600 struct device_node
*np
;
602 if (pmu_get_model() != PMU_OHARE_BASED
)
604 np
= of_find_node_by_name(NULL
, "via-pmu");
607 viaint
= np
->intrs
[0].line
;
608 #endif /* CONFIG_ADB_PMU */
614 static int pmacpic_suspend(struct sys_device
*sysdev
, pm_message_t state
)
616 int viaint
= pmacpic_find_viaint();
618 sleep_save_mask
[0] = ppc_cached_irq_mask
[0];
619 sleep_save_mask
[1] = ppc_cached_irq_mask
[1];
620 ppc_cached_irq_mask
[0] = 0;
621 ppc_cached_irq_mask
[1] = 0;
623 set_bit(viaint
, ppc_cached_irq_mask
);
624 out_le32(&pmac_irq_hw
[0]->enable
, ppc_cached_irq_mask
[0]);
625 if (max_real_irqs
> 32)
626 out_le32(&pmac_irq_hw
[1]->enable
, ppc_cached_irq_mask
[1]);
627 (void)in_le32(&pmac_irq_hw
[0]->event
);
628 /* make sure mask gets to controller before we return to caller */
630 (void)in_le32(&pmac_irq_hw
[0]->enable
);
635 static int pmacpic_resume(struct sys_device
*sysdev
)
639 out_le32(&pmac_irq_hw
[0]->enable
, 0);
640 if (max_real_irqs
> 32)
641 out_le32(&pmac_irq_hw
[1]->enable
, 0);
643 for (i
= 0; i
< max_real_irqs
; ++i
)
644 if (test_bit(i
, sleep_save_mask
))
650 #endif /* CONFIG_PM */
652 static struct sysdev_class pmacpic_sysclass
= {
653 set_kset_name("pmac_pic"),
656 static struct sys_device device_pmacpic
= {
658 .cls
= &pmacpic_sysclass
,
661 static struct sysdev_driver driver_pmacpic
= {
663 .suspend
= &pmacpic_suspend
,
664 .resume
= &pmacpic_resume
,
665 #endif /* CONFIG_PM */
668 static int __init
init_pmacpic_sysfs(void)
674 printk(KERN_DEBUG
"Registering pmac pic with sysfs...\n");
675 sysdev_class_register(&pmacpic_sysclass
);
676 sysdev_register(&device_pmacpic
);
677 sysdev_driver_register(&pmacpic_sysclass
, &driver_pmacpic
);
681 subsys_initcall(init_pmacpic_sysfs
);